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Searched refs:WREG32_SOC15_IP (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v6_0.c214 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, in sdma_v6_0_ring_set_wptr()
217 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, in sdma_v6_0_ring_set_wptr()
389 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); in sdma_v6_0_gfx_stop()
392 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl); in sdma_v6_0_gfx_stop()
455 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), f32_cntl); in sdma_v6_0_enable()
482 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); in sdma_v6_0_gfx_resume()
494 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); in sdma_v6_0_gfx_resume()
497 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0); in sdma_v6_0_gfx_resume()
498 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0); in sdma_v6_0_gfx_resume()
499 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0); in sdma_v6_0_gfx_resume()
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H A Dsdma_v5_2.c384 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); in sdma_v5_2_gfx_stop()
387 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); in sdma_v5_2_gfx_stop()
442 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), in sdma_v5_2_ctx_switch_enable()
444 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), in sdma_v5_2_ctx_switch_enable()
446 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), in sdma_v5_2_ctx_switch_enable()
511 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); in sdma_v5_2_gfx_resume()
522 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); in sdma_v5_2_gfx_resume()
525 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); in sdma_v5_2_gfx_resume()
526 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); in sdma_v5_2_gfx_resume()
527 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); in sdma_v5_2_gfx_resume()
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H A Dsdma_v5_0.c389 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, in sdma_v5_0_ring_set_wptr()
392 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, in sdma_v5_0_ring_set_wptr()
567 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); in sdma_v5_0_gfx_stop()
570 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); in sdma_v5_0_gfx_stop()
631 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), in sdma_v5_0_ctx_switch_enable()
633 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), in sdma_v5_0_ctx_switch_enable()
635 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), in sdma_v5_0_ctx_switch_enable()
707 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); in sdma_v5_0_gfx_resume()
710 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); in sdma_v5_0_gfx_resume()
711 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); in sdma_v5_0_gfx_resume()
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H A Damdgpu_gmc.c682 WREG32_SOC15_IP(GC, reg, tmp) : in amdgpu_gmc_set_vm_fault_masks()
683 WREG32_SOC15_IP(MMHUB, reg, tmp); in amdgpu_gmc_set_vm_fault_masks()
H A Dgmc_v9_0.c505 WREG32_SOC15_IP(MMHUB, reg, tmp); in gmc_v9_0_vm_fault_interrupt_state()
507 WREG32_SOC15_IP(GC, reg, tmp); in gmc_v9_0_vm_fault_interrupt_state()
533 WREG32_SOC15_IP(MMHUB, reg, tmp); in gmc_v9_0_vm_fault_interrupt_state()
535 WREG32_SOC15_IP(GC, reg, tmp); in gmc_v9_0_vm_fault_interrupt_state()
H A Dsoc15_common.h86 #define WREG32_SOC15_IP(ip, reg, value) \ macro
H A Damdgpu_amdkfd_gfx_v10_3.c214 WREG32_SOC15_IP(GC, reg, mqd_hqd[reg - hqd_base]); in hqd_load_v10_3()
H A Damdgpu_amdkfd_gfx_v10.c228 WREG32_SOC15_IP(GC, reg, mqd_hqd[reg - hqd_base]); in kgd_hqd_load()
H A Dgfx_v11_0.c5740 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v11_0_set_gfx_eop_interrupt_state()
5748 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v11_0_set_gfx_eop_interrupt_state()
5797 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v11_0_set_compute_eop_interrupt_state()
5805 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v11_0_set_compute_eop_interrupt_state()
6021 WREG32_SOC15_IP(GC, target, tmp);
6031 WREG32_SOC15_IP(GC, target, tmp);
H A Dsoc15.c476 WREG32_SOC15_IP(GC, reg, tmp) : WREG32(reg, tmp); in soc15_program_register_sequence()
H A Dgfx_v10_0.c8785 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v10_0_set_gfx_eop_interrupt_state()
8791 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v10_0_set_gfx_eop_interrupt_state()
8838 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v10_0_set_compute_eop_interrupt_state()
8844 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v10_0_set_compute_eop_interrupt_state()
9063 WREG32_SOC15_IP(GC, target, tmp); in gfx_v10_0_kiq_set_interrupt_state()
9073 WREG32_SOC15_IP(GC, target, tmp); in gfx_v10_0_kiq_set_interrupt_state()
H A Dgfx_v9_0.c5772 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v9_0_set_compute_eop_interrupt_state()
5778 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v9_0_set_compute_eop_interrupt_state()