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Searched refs:VM_CONTEXT0_CNTL (Results 1 – 20 of 20) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfxhub_v1_0.c223 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in gfxhub_v1_0_enable_system_domain()
224 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, in gfxhub_v1_0_enable_system_domain()
226 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE, in gfxhub_v1_0_enable_system_domain()
228 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, in gfxhub_v1_0_enable_system_domain()
H A Dgfxhub_v1_2.c277 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in gfxhub_v1_2_xcc_enable_system_domain()
278 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, in gfxhub_v1_2_xcc_enable_system_domain()
280 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE, in gfxhub_v1_2_xcc_enable_system_domain()
282 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, in gfxhub_v1_2_xcc_enable_system_domain()
H A Dmmhub_v1_8.c285 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in mmhub_v1_8_enable_system_domain()
286 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, in mmhub_v1_8_enable_system_domain()
289 VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE, in mmhub_v1_8_enable_system_domain()
291 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, in mmhub_v1_8_enable_system_domain()
H A Dmmhub_v1_0.c204 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in mmhub_v1_0_enable_system_domain()
205 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); in mmhub_v1_0_enable_system_domain()
206 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, in mmhub_v1_0_enable_system_domain()
H A Dmmhub_v1_7.c231 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in mmhub_v1_7_enable_system_domain()
232 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, in mmhub_v1_7_enable_system_domain()
234 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE, in mmhub_v1_7_enable_system_domain()
236 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, in mmhub_v1_7_enable_system_domain()
H A Dgmc_v7_0.c654 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in gmc_v7_0_gart_enable()
655 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); in gmc_v7_0_gart_enable()
656 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); in gmc_v7_0_gart_enable()
H A Dgmc_v8_0.c885 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in gmc_v8_0_gart_enable()
886 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); in gmc_v8_0_gart_enable()
887 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); in gmc_v8_0_gart_enable()
H A Dsid.h393 #define VM_CONTEXT0_CNTL 0x504 macro
/openbmc/linux/drivers/gpu/drm/radeon/
H A Drv770.c929 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in rv770_pcie_gart_enable()
934 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); in rv770_pcie_gart_enable()
951 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); in rv770_pcie_gart_disable()
1002 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); in rv770_agp_enable()
H A Drv770d.h634 #define VM_CONTEXT0_CNTL 0x1410 macro
H A Dni.c1298 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in cayman_pcie_gart_enable()
1355 WREG32(VM_CONTEXT0_CNTL, 0); in cayman_pcie_gart_disable()
H A Dnid.h127 #define VM_CONTEXT0_CNTL 0x1410 macro
H A Dr600.c1171 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in r600_pcie_gart_enable()
1176 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); in r600_pcie_gart_enable()
1193 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); in r600_pcie_gart_disable()
1259 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); in r600_agp_enable()
H A Dsid.h392 #define VM_CONTEXT0_CNTL 0x1410 macro
H A Dcikd.h510 #define VM_CONTEXT0_CNTL 0x1410 macro
H A Devergreen.c2443 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in evergreen_pcie_gart_enable()
2462 WREG32(VM_CONTEXT0_CNTL, 0); in evergreen_pcie_gart_disable()
2512 WREG32(VM_CONTEXT0_CNTL, 0); in evergreen_agp_enable()
H A Devergreend.h1136 #define VM_CONTEXT0_CNTL 0x1410 macro
H A Dr600d.h573 #define VM_CONTEXT0_CNTL 0x1410 macro
H A Dsi.c4321 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in si_pcie_gart_enable()
4386 WREG32(VM_CONTEXT0_CNTL, 0); in si_pcie_gart_disable()
H A Dcik.c5456 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in cik_pcie_gart_enable()
5550 WREG32(VM_CONTEXT0_CNTL, 0); in cik_pcie_gart_disable()