Home
last modified time | relevance | path

Searched refs:VIVS_HI_CLOCK_CONTROL (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/drivers/gpu/drm/etnaviv/
H A Detnaviv_gpu.c475 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock | in etnaviv_gpu_load_clock()
477 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); in etnaviv_gpu_load_clock()
490 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in etnaviv_gpu_update_clock()
523 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
531 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
539 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
543 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
555 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in etnaviv_hw_reset()
566 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
574 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in etnaviv_hw_reset()
[all …]
H A Detnaviv_perfmon.c54 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); in pipe_select()
61 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in pipe_perf_reg_read()
80 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in pipe_reg_read()
H A Detnaviv_dump.c29 VIVS_HI_CLOCK_CONTROL,
H A Dstate_hi.xml.h56 #define VIVS_HI_CLOCK_CONTROL 0x00000000 macro