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Searched refs:VCS1 (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/drivers/gpu/drm/i915/gvt/
H A Dmmio_context.c133 {VCS1, RING_EXCC(GEN8_BSD2_RING_BASE), 0xffff, false}, /* 0x1c028 */
161 [VCS1] = 0xca00,
348 [VCS1] = 0x4268,
405 [VCS1] = 0xca00, in switch_mocs()
H A Dexeclist.c52 [VCS1] = VCS2_AS_CONTEXT_SWITCH,
H A Dinterrupt.c581 if (HAS_ENGINE(gvt->gt, VCS1)) { in gen8_init_irq()
H A Dcmd_parser.c427 #define R_VCS2 BIT(VCS1)
641 [VCS1] = {
1167 [VCS1] = {
H A Dhandlers.c342 engine_mask |= BIT(VCS1); in gdrst_mmio_write()
2087 id = VCS1; in gvt_reg_tlb_control_handler()
2163 if (HAS_ENGINE(gvt->gt, VCS1)) \
/openbmc/linux/drivers/gpu/drm/i915/
H A Di915_pci.c454 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
506 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
569 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
590 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
749 BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) |
H A Dintel_gvt_mmio_table.c40 if (HAS_ENGINE(to_gt(iter->i915), VCS1)) \
/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dintel_engine_types.h124 VCS1, enumerator
H A Dintel_engine_cs.c143 [VCS1] = {
414 [VCS1] = GEN11_GRDOM_MEDIA2, in get_reset_domain()
439 [VCS1] = GEN8_GRDOM_MEDIA2, in get_reset_domain()
1709 [VCS1] = MSG_IDLE_VCS1, in __cs_pending_mi_force_wakes()
H A Dintel_mocs.c622 [VCS1] = __GEN9_VCS1_MOCS0, in mocs_offset()
H A Dintel_execlists_submission.c3505 [VCS1] = GEN8_VCS1_IRQ_SHIFT, in logical_ring_default_irqs()