| /openbmc/linux/drivers/usb/cdns3/ |
| H A D | Kconfig | 17 tristate "Cadence USB3 Dual-Role Controller"
20 Say Y here if your system has a Cadence USB3 dual-role controller.
30 bool "Cadence USB3 device controller"
40 bool "Cadence USB3 host controller"
51 tristate "Cadence USB3 support on PCIe-based platforms"
62 tristate "Cadence USB3 support on TI platforms"
67 platforms that contain Cadence USB3 controller core.
72 tristate "Cadence USB3 support on NXP i.MX platforms"
77 platforms that contain Cadence USB3 controller core.
82 tristate "Cadence USB3 support on StarFive SoC platforms"
[all …]
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| /openbmc/linux/arch/arm64/boot/dts/amlogic/ |
| H A D | meson-g12b-s922x-khadas-vim3.dts | 19 * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential
21 * an USB3.0 Type A connector and a M.2 Key M slot.
23 * the USB3.0 controller and the PCIe Controller, thus only
25 * If the MCU is configured to mux the PCIe/USB3.0 differential lines
27 * USB3.0 from the USB Complex and enable the PCIe controller.
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| H A D | meson-g12b-a311d-khadas-vim3.dts | 19 * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential
21 * an USB3.0 Type A connector and a M.2 Key M slot.
23 * the USB3.0 controller and the PCIe Controller, thus only
25 * If the MCU is configured to mux the PCIe/USB3.0 differential lines
27 * USB3.0 from the USB Complex and enable the PCIe controller.
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| H A D | meson-sm1-khadas-vim3l.dts | 87 * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential
89 * an USB3.0 Type A connector and a M.2 Key M slot.
91 * the USB3.0 controller and the PCIe Controller, thus only
93 * If the MCU is configured to mux the PCIe/USB3.0 differential lines
95 * USB3.0 from the USB Complex and enable the PCIe controller.
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| /openbmc/linux/drivers/phy/socionext/ |
| H A D | Kconfig | 17 of USB3 HS-PHY.
20 tristate "UniPhier USB3 PHY driver"
25 Enable this to support USB PHY implemented in USB3 controller
26 on UniPhier SoCs. This controller supports USB3.0 and lower speed.
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| /openbmc/linux/drivers/usb/dwc3/ |
| H A D | Kconfig | 4 tristate "DesignWare USB3 DRD Core Support"
11 USB controller based on the DesignWare USB3 IP Core.
74 Exynos5800, Exynos5433, Exynos7) ship with one DesignWare Core USB3
118 Currently supports Xilinx and Qualcomm DWC USB3 IP.
126 STMicroelectronics SoCs with one DesignWare Core USB3 IP
158 Support Xilinx SoCs with DesignWare Core USB3 IP.
167 Support TI's AM62 platforms with DesignWare Core USB3 IP.
168 The Designware Core USB3 IP is programmed to operate in
177 Support Cavium Octeon platforms with DesignWare Core USB3 IP.
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| /openbmc/u-boot/arch/arm/mach-tegra/tegra210/ |
| H A D | Kconfig | 20 HDMI, USB micro-B port, Ethernet via USB3, USB3 host port, SATA,
29 card slot, HDMI, USB micro-B port, Ethernet via USB3, USB3 host
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| /openbmc/u-boot/drivers/usb/dwc3/ |
| H A D | Kconfig | 2 bool "DesignWare USB3 DRD Core Support"
6 USB controller based on the DesignWare USB3 IP Core.
48 bool "DesignWare USB3 Host Support on UniPhier Platforms"
59 Enable single driver for both USB2 PHY programming and USB3 PHY
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| /openbmc/linux/drivers/usb/gadget/udc/bdc/ |
| H A D | Kconfig | 4 tristate "Broadcom USB3.0 device controller IP driver(BDC)"
9 BDC is Broadcom's USB3.0 device controller IP. If your SOC has a BDC IP
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | mvebu-gated-clock.txt | 39 16 usb3 USB3 Host
65 9 usb3h0 USB3 Host 0
66 10 usb3h1 USB3 Host 1
67 11 usb3d USB3 Device
88 9 usb3h0 USB3 Host 0
89 10 usb3h1 USB3 Host 1
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| /openbmc/u-boot/arch/arm/mach-mediatek/ |
| H A D | Kconfig | 21 Peripherals include Gigabit Ethernet, switch, USB3.0 and OTG, PCIe,
32 switch, USB3.0, PCIe, UART, SPI, I2C and PWM.
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| /openbmc/linux/Documentation/driver-api/usb/ |
| H A D | usb3-debug-port.rst | 2 USB3 debug port
11 This is a HOWTO for using the USB3 debug port on x86 systems.
13 Before using any kernel debugging functionality based on USB3
16 1) check whether any USB3 debug port is available in
29 device through the debug port (normally the first USB3
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| /openbmc/linux/Documentation/devicetree/bindings/phy/ |
| H A D | phy-mvebu.txt | 26 Armada 375 comes with an USB2 host and device controller and an USB3
35 values are 1 (USB2), 2 (USB3).
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| H A D | phy-miphy28lp.txt | 5 for SATA, PCIe or USB3.
10 which contain the SATA, PCIe or USB3 mode setting bits.
27 registers used as glue-logic to setup the device for SATA/PCIe or USB3
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| H A D | phy-mvebu-comphy.txt | 21 * Lane 0 (USB3/GbE)
22 * Lane 2 (SATA/USB3)
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| /openbmc/u-boot/board/theobroma-systems/puma_rk3399/ |
| H A D | README | 17 * USB3.0 dual role port
18 * 2x USB3.0 host, 1x USB2.0 host via onboard USB3.0 hub
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| /openbmc/linux/drivers/phy/allwinner/ |
| H A D | Kconfig | 50 tristate "Allwinner H6 SoC USB3 PHY driver"
56 Enable this to support the USB3.0-capable transceiver that is
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| /openbmc/linux/drivers/phy/st/ |
| H A D | Kconfig | 10 Enable this to support the miphy transceiver (for SATA/PCIE/USB3)
34 and USB3 controllers on STMicroelectronics STiH407 SoC families.
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| /openbmc/linux/drivers/usb/mtu3/ |
| H A D | Kconfig | 3 # For MTK USB3.0 IP
6 tristate "MediaTek USB3 Dual Role controller"
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| /openbmc/linux/arch/arm/boot/dts/marvell/ |
| H A D | armada-388-clearfog.dts | 66 * 5-USB3 overcurrent
67 * 6-USB3 power
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| /openbmc/linux/drivers/phy/mediatek/ |
| H A D | Kconfig | 49 USB3.1 GEN2 controllers on MediaTek chips. The driver supports
50 multiple USB2.0, USB3.1 GEN2 ports.
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| /openbmc/linux/arch/arm/boot/dts/ti/omap/ |
| H A D | am5718.dtsi | 20 * USB3
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| H A D | am5728.dtsi | 21 * USB3, USB4
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| H A D | am5748.dtsi | 21 * USB3, USB4
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| /openbmc/linux/drivers/phy/qualcomm/ |
| H A D | Kconfig | 69 with USB3 and DisplayPort controllers on Qualcomm chips.
103 with USB3 controllers on Qualcomm chips.
111 PHY transceivers working only in USB3 mode on Qualcomm chips. This
210 Qualcomm USB3.0 DWC3 controller on ipq806x SoC. This driver supports
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