Searched refs:TSR_WIS (Results 1 – 9 of 9) sorted by relevance
71 #define TSR_WIS (1U << 30) /* Watchdog Timer Interrupt Status */ macro95 (env->spr[SPR_BOOKE_TSR] & TSR_WIS in booke_update_irq()256 TSR_WIS); in booke_wdt_cb()276 if (val & TSR_WIS) { in store_booke_tsr()281 TSR_WIS); in store_booke_tsr()308 TSR_WIS); in store_booke_tcr()341 store_booke_tsr(env, TSR_ENW | TSR_WIS | TSR_WRS_MASK); in cpu_state_change_handler()
126 mtspr(SPRN_TSR, TSR_ENW|TSR_WIS); in __booke_wdt_ping()
613 if ((vcpu->arch.tsr & (TSR_ENW | TSR_WIS)) != (TSR_ENW | TSR_WIS)) in arm_next_watchdog()641 if (tsr & TSR_WIS) in kvmppc_watchdog_func()644 new_tsr = tsr | TSR_WIS; in kvmppc_watchdog_func()650 if (new_tsr & TSR_WIS) { in kvmppc_watchdog_func()684 if ((vcpu->arch.tcr & TCR_WIE) && (vcpu->arch.tsr & TSR_WIS)) in update_timer_ints()1422 if ((old_tsr ^ vcpu->arch.tsr) & (TSR_ENW | TSR_WIS)) in kvmppc_set_tsr()1885 if (tsr_bits & (TSR_ENW | TSR_WIS)) in kvmppc_clr_tsr_bits()
241 lis r0, (TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS)@h
185 lis r4, (TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS)@h
680 mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS); in start_cpu_decrementer()
557 #define TSR_WIS 0x40000000 /* WDT Interrupt Status */ macro
355 mtspr(SPRN_TSR, TSR_WIS); in reset_85xx_watchdog()
417 #define TSR_WIS 0x40000000 /* WDT Interrupt Status */ macro