Home
last modified time | relevance | path

Searched refs:TRAINING_DBG_3_REG (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dmv_ddr_regs.h261 #define TRAINING_DBG_3_REG 0x15c8 macro
H A Dmv_ddr_plat.c1254 reg_val = reg_read(TRAINING_DBG_3_REG); in mv_ddr_pre_training_soc_config()
1271 reg_write(TRAINING_DBG_3_REG, reg_val); in mv_ddr_pre_training_soc_config()
H A Dddr3_training_leveling.c152 TRAINING_DBG_3_REG, (0x7f << 24), in ddr3_tip_dynamic_read_leveling()
524 TRAINING_DBG_3_REG, (0x7f << 24), in ddr3_tip_dynamic_per_bit_read_leveling()