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Searched refs:TM_QW3_NSR_HE_POOL (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/arch/powerpc/include/asm/
H A Dxive-regs.h128 #define TM_QW3_NSR_HE_POOL 1 macro
/openbmc/qemu/include/hw/ppc/
H A Dxive_regs.h154 #define TM_QW3_NSR_HE_POOL 1 macro
/openbmc/linux/arch/powerpc/sysdev/xive/
H A Dnative.c378 case TM_QW3_NSR_HE_POOL: /* HV Pool interrupt (unused) */ in xive_native_update_pending()
/openbmc/qemu/hw/intc/
H A Dxive.c81 if ((ring == TM_QW3_HV_PHYS) && (nsr & (TM_QW3_NSR_HE_POOL << 6))) { in xive_tctx_accept()
117 alt_regs[TM_NSR] = (TM_QW3_NSR_HE_POOL << 6); in xive_tctx_notify()