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Searched refs:TM_QW1_OS (Results 1 – 9 of 9) sorted by relevance

/openbmc/qemu/hw/intc/
H A Dxive.c43 case TM_QW1_OS: in exception_mask()
57 case TM_QW1_OS: in xive_tctx_output()
113 case TM_QW1_OS: in xive_tctx_notify()
391 return xive_tctx_accept(tctx, TM_QW1_OS); in xive_tm_ack_os_reg()
397 xive_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff); in xive_tm_set_os_cppr()
410 xive_tctx_set_lgs(tctx, TM_QW1_OS, value & 0xff); in xive_tm_set_os_lgs()
420 xive_tctx_ipb_update(tctx, TM_QW1_OS, xive_priority_to_ipb(value & 0xff)); in xive_tm_set_os_pending()
440 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); in xive_tctx_get_os_cam()
449 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); in xive_tctx_set_os_cam()
472 xive_tctx_reset_signal(tctx, TM_QW1_OS); in xive_tm_pull_os_ctx()
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H A Dxive2.c389 for (cur_ring = TM_QW1_OS; cur_ring <= ring; in xive2_tm_pull_ctx()
399 return xive2_tm_pull_ctx(xptr, tctx, offset, size, TM_QW1_OS); in xive2_tm_pull_os_ctx()
419 data[0x4] = regs[TM_QW1_OS + TM_ACK_CNT]; in xive2_tm_report_line_gen1()
424 data[0x7] |= (regs[TM_QW1_OS + TM_WORD2] & 0x80) >> 2; in xive2_tm_report_line_gen1()
426 data[0x8] = regs[TM_QW1_OS + TM_NSR]; in xive2_tm_report_line_gen1()
427 data[0x9] = regs[TM_QW1_OS + TM_CPPR]; in xive2_tm_report_line_gen1()
428 data[0xA] = regs[TM_QW1_OS + TM_IPB]; in xive2_tm_report_line_gen1()
429 data[0xB] = regs[TM_QW1_OS + TM_LGS]; in xive2_tm_report_line_gen1()
501 xive2_tm_pull_ctx_ol(xptr, tctx, offset, value, size, TM_QW1_OS); in xive2_tm_pull_os_ctx_ol()
529 tctx->regs[TM_QW1_OS + TM_CPPR] = cppr; in xive2_tctx_restore_os_ctx()
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H A Dspapr_xive_kvm.c86 state[0] = *((uint64_t *) &tctx->regs[TM_QW1_OS]); in kvmppc_xive_cpu_set_state()
116 *((uint64_t *) &tctx->regs[TM_QW1_OS]) = state[0]; in kvmppc_xive_cpu_get_state()
H A Dspapr_xive.c658 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); in xive_tctx_set_os_cam()
/openbmc/qemu/tests/qtest/
H A Dpnv-xive2-test.c288 qw1w0 = get_tima32(qts, target_pir, TM_QW1_OS + TM_WORD0); in test_pull_thread_ctx_to_odd_thread_cl()
290 qw1w2 = get_tima32(qts, target_pir, TM_QW1_OS + TM_WORD2); in test_pull_thread_ctx_to_odd_thread_cl()
299 memcpy(&cl_word, &cl_pair[XIVE_ODD_CL + TM_QW1_OS + TM_WORD0], 4); in test_pull_thread_ctx_to_odd_thread_cl()
303 memcpy(&cl_word, &cl_pair[XIVE_ODD_CL + TM_QW1_OS + TM_WORD2], 4); in test_pull_thread_ctx_to_odd_thread_cl()
311 word2 = get_tima32(qts, target_pir, TM_QW1_OS + TM_WORD2); in test_pull_thread_ctx_to_odd_thread_cl()
/openbmc/linux/arch/powerpc/include/asm/
H A Dxive-regs.h58 #define TM_QW1_OS 0x010 /* Ring 0..2 */ macro
/openbmc/linux/arch/powerpc/sysdev/xive/
H A Dspapr.c650 in_be32(xive_tima + TM_QW1_OS + TM_WORD0), in xive_spapr_setup_cpu()
651 in_be32(xive_tima + TM_QW1_OS + TM_WORD1), in xive_spapr_setup_cpu()
652 in_be32(xive_tima + TM_QW1_OS + TM_WORD2)); in xive_spapr_setup_cpu()
875 if (!xive_core_init(np, &xive_spapr_ops, tima, TM_QW1_OS, max_prio)) in xive_spapr_init()
/openbmc/linux/arch/powerpc/kvm/
H A Dbook3s_xive.c281 __raw_writeb(xc->cppr, xive_tima + TM_QW1_OS + TM_CPPR); in xive_vm_scan_interrupts()
357 __be64 qw1 = __raw_readq(xive_tima + TM_QW1_OS); in xive_vm_h_ipoll()
510 __raw_writeb(cppr, xive_tima + TM_QW1_OS + TM_CPPR); in xive_vm_h_cppr()
615 __raw_writeb(xc->cppr, xive_tima + TM_QW1_OS + TM_CPPR); in xive_vm_h_eoi()
701 __raw_writeq(vcpu->arch.xive_saved_state.w01, tima + TM_QW1_OS); in kvmppc_xive_push_vcpu()
702 __raw_writel(vcpu->arch.xive_cam_word, tima + TM_QW1_OS + TM_WORD2); in kvmppc_xive_push_vcpu()
774 vcpu->arch.xive_saved_state.w01 = __raw_readq(tima + TM_QW1_OS); in kvmppc_xive_pull_vcpu()
/openbmc/qemu/include/hw/ppc/
H A Dxive_regs.h69 #define TM_QW1_OS 0x010 /* Ring 0..2 */ macro