Searched refs:TMU_RTR_CS_3_TS_PACKET_INTERVAL_MASK (Results 1 – 2 of 2) sorted by relevance
255 #define TMU_RTR_CS_3_TS_PACKET_INTERVAL_MASK GENMASK(31, 16) macro
159 val &= ~TMU_RTR_CS_3_TS_PACKET_INTERVAL_MASK; in tb_switch_tmu_rate_write()