1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * STM32 Timer Encoder and Counter driver
4 *
5 * Copyright (C) STMicroelectronics 2018
6 *
7 * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
8 *
9 */
10 #include <linux/counter.h>
11 #include <linux/mfd/stm32-timers.h>
12 #include <linux/mod_devicetable.h>
13 #include <linux/module.h>
14 #include <linux/pinctrl/consumer.h>
15 #include <linux/platform_device.h>
16 #include <linux/types.h>
17
18 #define TIM_CCMR_CCXS (BIT(8) | BIT(0))
19 #define TIM_CCMR_MASK (TIM_CCMR_CC1S | TIM_CCMR_CC2S | \
20 TIM_CCMR_IC1F | TIM_CCMR_IC2F)
21 #define TIM_CCER_MASK (TIM_CCER_CC1P | TIM_CCER_CC1NP | \
22 TIM_CCER_CC2P | TIM_CCER_CC2NP)
23
24 struct stm32_timer_regs {
25 u32 cr1;
26 u32 cnt;
27 u32 smcr;
28 u32 arr;
29 };
30
31 struct stm32_timer_cnt {
32 struct regmap *regmap;
33 struct clk *clk;
34 u32 max_arr;
35 bool enabled;
36 struct stm32_timer_regs bak;
37 };
38
39 static const enum counter_function stm32_count_functions[] = {
40 COUNTER_FUNCTION_INCREASE,
41 COUNTER_FUNCTION_QUADRATURE_X2_A,
42 COUNTER_FUNCTION_QUADRATURE_X2_B,
43 COUNTER_FUNCTION_QUADRATURE_X4,
44 };
45
stm32_count_read(struct counter_device * counter,struct counter_count * count,u64 * val)46 static int stm32_count_read(struct counter_device *counter,
47 struct counter_count *count, u64 *val)
48 {
49 struct stm32_timer_cnt *const priv = counter_priv(counter);
50 u32 cnt;
51
52 regmap_read(priv->regmap, TIM_CNT, &cnt);
53 *val = cnt;
54
55 return 0;
56 }
57
stm32_count_write(struct counter_device * counter,struct counter_count * count,const u64 val)58 static int stm32_count_write(struct counter_device *counter,
59 struct counter_count *count, const u64 val)
60 {
61 struct stm32_timer_cnt *const priv = counter_priv(counter);
62 u32 ceiling;
63
64 regmap_read(priv->regmap, TIM_ARR, &ceiling);
65 if (val > ceiling)
66 return -EINVAL;
67
68 return regmap_write(priv->regmap, TIM_CNT, val);
69 }
70
stm32_count_function_read(struct counter_device * counter,struct counter_count * count,enum counter_function * function)71 static int stm32_count_function_read(struct counter_device *counter,
72 struct counter_count *count,
73 enum counter_function *function)
74 {
75 struct stm32_timer_cnt *const priv = counter_priv(counter);
76 u32 smcr;
77
78 regmap_read(priv->regmap, TIM_SMCR, &smcr);
79
80 switch (smcr & TIM_SMCR_SMS) {
81 case TIM_SMCR_SMS_SLAVE_MODE_DISABLED:
82 *function = COUNTER_FUNCTION_INCREASE;
83 return 0;
84 case TIM_SMCR_SMS_ENCODER_MODE_1:
85 *function = COUNTER_FUNCTION_QUADRATURE_X2_A;
86 return 0;
87 case TIM_SMCR_SMS_ENCODER_MODE_2:
88 *function = COUNTER_FUNCTION_QUADRATURE_X2_B;
89 return 0;
90 case TIM_SMCR_SMS_ENCODER_MODE_3:
91 *function = COUNTER_FUNCTION_QUADRATURE_X4;
92 return 0;
93 default:
94 return -EINVAL;
95 }
96 }
97
stm32_count_function_write(struct counter_device * counter,struct counter_count * count,enum counter_function function)98 static int stm32_count_function_write(struct counter_device *counter,
99 struct counter_count *count,
100 enum counter_function function)
101 {
102 struct stm32_timer_cnt *const priv = counter_priv(counter);
103 u32 cr1, sms;
104
105 switch (function) {
106 case COUNTER_FUNCTION_INCREASE:
107 sms = TIM_SMCR_SMS_SLAVE_MODE_DISABLED;
108 break;
109 case COUNTER_FUNCTION_QUADRATURE_X2_A:
110 sms = TIM_SMCR_SMS_ENCODER_MODE_1;
111 break;
112 case COUNTER_FUNCTION_QUADRATURE_X2_B:
113 sms = TIM_SMCR_SMS_ENCODER_MODE_2;
114 break;
115 case COUNTER_FUNCTION_QUADRATURE_X4:
116 sms = TIM_SMCR_SMS_ENCODER_MODE_3;
117 break;
118 default:
119 return -EINVAL;
120 }
121
122 /* Store enable status */
123 regmap_read(priv->regmap, TIM_CR1, &cr1);
124
125 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
126
127 regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms);
128
129 /* Make sure that registers are updated */
130 regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
131
132 /* Restore the enable status */
133 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, cr1);
134
135 return 0;
136 }
137
stm32_count_direction_read(struct counter_device * counter,struct counter_count * count,enum counter_count_direction * direction)138 static int stm32_count_direction_read(struct counter_device *counter,
139 struct counter_count *count,
140 enum counter_count_direction *direction)
141 {
142 struct stm32_timer_cnt *const priv = counter_priv(counter);
143 u32 cr1;
144
145 regmap_read(priv->regmap, TIM_CR1, &cr1);
146 *direction = (cr1 & TIM_CR1_DIR) ? COUNTER_COUNT_DIRECTION_BACKWARD :
147 COUNTER_COUNT_DIRECTION_FORWARD;
148
149 return 0;
150 }
151
stm32_count_ceiling_read(struct counter_device * counter,struct counter_count * count,u64 * ceiling)152 static int stm32_count_ceiling_read(struct counter_device *counter,
153 struct counter_count *count, u64 *ceiling)
154 {
155 struct stm32_timer_cnt *const priv = counter_priv(counter);
156 u32 arr;
157
158 regmap_read(priv->regmap, TIM_ARR, &arr);
159
160 *ceiling = arr;
161
162 return 0;
163 }
164
stm32_count_ceiling_write(struct counter_device * counter,struct counter_count * count,u64 ceiling)165 static int stm32_count_ceiling_write(struct counter_device *counter,
166 struct counter_count *count, u64 ceiling)
167 {
168 struct stm32_timer_cnt *const priv = counter_priv(counter);
169
170 if (ceiling > priv->max_arr)
171 return -ERANGE;
172
173 /* TIMx_ARR register shouldn't be buffered (ARPE=0) */
174 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
175 regmap_write(priv->regmap, TIM_ARR, ceiling);
176
177 return 0;
178 }
179
stm32_count_enable_read(struct counter_device * counter,struct counter_count * count,u8 * enable)180 static int stm32_count_enable_read(struct counter_device *counter,
181 struct counter_count *count, u8 *enable)
182 {
183 struct stm32_timer_cnt *const priv = counter_priv(counter);
184 u32 cr1;
185
186 regmap_read(priv->regmap, TIM_CR1, &cr1);
187
188 *enable = cr1 & TIM_CR1_CEN;
189
190 return 0;
191 }
192
stm32_count_enable_write(struct counter_device * counter,struct counter_count * count,u8 enable)193 static int stm32_count_enable_write(struct counter_device *counter,
194 struct counter_count *count, u8 enable)
195 {
196 struct stm32_timer_cnt *const priv = counter_priv(counter);
197 u32 cr1;
198 int ret;
199
200 if (enable) {
201 regmap_read(priv->regmap, TIM_CR1, &cr1);
202 if (!(cr1 & TIM_CR1_CEN)) {
203 ret = clk_enable(priv->clk);
204 if (ret) {
205 dev_err(counter->parent, "Cannot enable clock %d\n", ret);
206 return ret;
207 }
208 }
209
210 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
211 TIM_CR1_CEN);
212 } else {
213 regmap_read(priv->regmap, TIM_CR1, &cr1);
214 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
215 if (cr1 & TIM_CR1_CEN)
216 clk_disable(priv->clk);
217 }
218
219 /* Keep enabled state to properly handle low power states */
220 priv->enabled = enable;
221
222 return 0;
223 }
224
225 static struct counter_comp stm32_count_ext[] = {
226 COUNTER_COMP_DIRECTION(stm32_count_direction_read),
227 COUNTER_COMP_ENABLE(stm32_count_enable_read, stm32_count_enable_write),
228 COUNTER_COMP_CEILING(stm32_count_ceiling_read,
229 stm32_count_ceiling_write),
230 };
231
232 static const enum counter_synapse_action stm32_synapse_actions[] = {
233 COUNTER_SYNAPSE_ACTION_NONE,
234 COUNTER_SYNAPSE_ACTION_BOTH_EDGES
235 };
236
stm32_action_read(struct counter_device * counter,struct counter_count * count,struct counter_synapse * synapse,enum counter_synapse_action * action)237 static int stm32_action_read(struct counter_device *counter,
238 struct counter_count *count,
239 struct counter_synapse *synapse,
240 enum counter_synapse_action *action)
241 {
242 enum counter_function function;
243 int err;
244
245 err = stm32_count_function_read(counter, count, &function);
246 if (err)
247 return err;
248
249 switch (function) {
250 case COUNTER_FUNCTION_INCREASE:
251 /* counts on internal clock when CEN=1 */
252 *action = COUNTER_SYNAPSE_ACTION_NONE;
253 return 0;
254 case COUNTER_FUNCTION_QUADRATURE_X2_A:
255 /* counts up/down on TI1FP1 edge depending on TI2FP2 level */
256 if (synapse->signal->id == count->synapses[0].signal->id)
257 *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
258 else
259 *action = COUNTER_SYNAPSE_ACTION_NONE;
260 return 0;
261 case COUNTER_FUNCTION_QUADRATURE_X2_B:
262 /* counts up/down on TI2FP2 edge depending on TI1FP1 level */
263 if (synapse->signal->id == count->synapses[1].signal->id)
264 *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
265 else
266 *action = COUNTER_SYNAPSE_ACTION_NONE;
267 return 0;
268 case COUNTER_FUNCTION_QUADRATURE_X4:
269 /* counts up/down on both TI1FP1 and TI2FP2 edges */
270 *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
271 return 0;
272 default:
273 return -EINVAL;
274 }
275 }
276
277 static const struct counter_ops stm32_timer_cnt_ops = {
278 .count_read = stm32_count_read,
279 .count_write = stm32_count_write,
280 .function_read = stm32_count_function_read,
281 .function_write = stm32_count_function_write,
282 .action_read = stm32_action_read,
283 };
284
285 static struct counter_signal stm32_signals[] = {
286 {
287 .id = 0,
288 .name = "Channel 1 Quadrature A"
289 },
290 {
291 .id = 1,
292 .name = "Channel 1 Quadrature B"
293 }
294 };
295
296 static struct counter_synapse stm32_count_synapses[] = {
297 {
298 .actions_list = stm32_synapse_actions,
299 .num_actions = ARRAY_SIZE(stm32_synapse_actions),
300 .signal = &stm32_signals[0]
301 },
302 {
303 .actions_list = stm32_synapse_actions,
304 .num_actions = ARRAY_SIZE(stm32_synapse_actions),
305 .signal = &stm32_signals[1]
306 }
307 };
308
309 static struct counter_count stm32_counts = {
310 .id = 0,
311 .name = "Channel 1 Count",
312 .functions_list = stm32_count_functions,
313 .num_functions = ARRAY_SIZE(stm32_count_functions),
314 .synapses = stm32_count_synapses,
315 .num_synapses = ARRAY_SIZE(stm32_count_synapses),
316 .ext = stm32_count_ext,
317 .num_ext = ARRAY_SIZE(stm32_count_ext)
318 };
319
stm32_timer_cnt_probe(struct platform_device * pdev)320 static int stm32_timer_cnt_probe(struct platform_device *pdev)
321 {
322 struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
323 struct device *dev = &pdev->dev;
324 struct stm32_timer_cnt *priv;
325 struct counter_device *counter;
326 int ret;
327
328 if (IS_ERR_OR_NULL(ddata))
329 return -EINVAL;
330
331 counter = devm_counter_alloc(dev, sizeof(*priv));
332 if (!counter)
333 return -ENOMEM;
334
335 priv = counter_priv(counter);
336
337 priv->regmap = ddata->regmap;
338 priv->clk = ddata->clk;
339 priv->max_arr = ddata->max_arr;
340
341 counter->name = dev_name(dev);
342 counter->parent = dev;
343 counter->ops = &stm32_timer_cnt_ops;
344 counter->counts = &stm32_counts;
345 counter->num_counts = 1;
346 counter->signals = stm32_signals;
347 counter->num_signals = ARRAY_SIZE(stm32_signals);
348
349 platform_set_drvdata(pdev, priv);
350
351 /* Reset input selector to its default input */
352 regmap_write(priv->regmap, TIM_TISEL, 0x0);
353
354 /* Register Counter device */
355 ret = devm_counter_add(dev, counter);
356 if (ret < 0)
357 dev_err_probe(dev, ret, "Failed to add counter\n");
358
359 return ret;
360 }
361
stm32_timer_cnt_suspend(struct device * dev)362 static int __maybe_unused stm32_timer_cnt_suspend(struct device *dev)
363 {
364 struct stm32_timer_cnt *priv = dev_get_drvdata(dev);
365
366 /* Only take care of enabled counter: don't disturb other MFD child */
367 if (priv->enabled) {
368 /* Backup registers that may get lost in low power mode */
369 regmap_read(priv->regmap, TIM_SMCR, &priv->bak.smcr);
370 regmap_read(priv->regmap, TIM_ARR, &priv->bak.arr);
371 regmap_read(priv->regmap, TIM_CNT, &priv->bak.cnt);
372 regmap_read(priv->regmap, TIM_CR1, &priv->bak.cr1);
373
374 /* Disable the counter */
375 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
376 clk_disable(priv->clk);
377 }
378
379 return pinctrl_pm_select_sleep_state(dev);
380 }
381
stm32_timer_cnt_resume(struct device * dev)382 static int __maybe_unused stm32_timer_cnt_resume(struct device *dev)
383 {
384 struct stm32_timer_cnt *priv = dev_get_drvdata(dev);
385 int ret;
386
387 ret = pinctrl_pm_select_default_state(dev);
388 if (ret)
389 return ret;
390
391 if (priv->enabled) {
392 ret = clk_enable(priv->clk);
393 if (ret) {
394 dev_err(dev, "Cannot enable clock %d\n", ret);
395 return ret;
396 }
397
398 /* Restore registers that may have been lost */
399 regmap_write(priv->regmap, TIM_SMCR, priv->bak.smcr);
400 regmap_write(priv->regmap, TIM_ARR, priv->bak.arr);
401 regmap_write(priv->regmap, TIM_CNT, priv->bak.cnt);
402
403 /* Also re-enables the counter */
404 regmap_write(priv->regmap, TIM_CR1, priv->bak.cr1);
405 }
406
407 return 0;
408 }
409
410 static SIMPLE_DEV_PM_OPS(stm32_timer_cnt_pm_ops, stm32_timer_cnt_suspend,
411 stm32_timer_cnt_resume);
412
413 static const struct of_device_id stm32_timer_cnt_of_match[] = {
414 { .compatible = "st,stm32-timer-counter", },
415 {},
416 };
417 MODULE_DEVICE_TABLE(of, stm32_timer_cnt_of_match);
418
419 static struct platform_driver stm32_timer_cnt_driver = {
420 .probe = stm32_timer_cnt_probe,
421 .driver = {
422 .name = "stm32-timer-counter",
423 .of_match_table = stm32_timer_cnt_of_match,
424 .pm = &stm32_timer_cnt_pm_ops,
425 },
426 };
427 module_platform_driver(stm32_timer_cnt_driver);
428
429 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
430 MODULE_ALIAS("platform:stm32-timer-counter");
431 MODULE_DESCRIPTION("STMicroelectronics STM32 TIMER counter driver");
432 MODULE_LICENSE("GPL v2");
433 MODULE_IMPORT_NS(COUNTER);
434