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Searched refs:TEGRA30_CLK_PLL_P (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/drivers/clk/tegra/
H A Dclk-tegra30.c540 { .con_id = "pll_p", .dt_id = TEGRA30_CLK_PLL_P },
800 [tegra_clk_pll_p] = { .dt_id = TEGRA30_CLK_PLL_P, .present = true },
1199 { TEGRA30_CLK_UARTA, TEGRA30_CLK_PLL_P, 408000000, 0 },
1200 { TEGRA30_CLK_UARTB, TEGRA30_CLK_PLL_P, 408000000, 0 },
1201 { TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0 },
1202 { TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 0 },
1203 { TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0 },
1211 { TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0 },
1212 { TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 48000000, 0 },
1213 { TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0 },
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/openbmc/u-boot/include/dt-bindings/clock/
H A Dtegra30-car.h203 #define TEGRA30_CLK_PLL_P 179 macro
/openbmc/linux/include/dt-bindings/clock/
H A Dtegra30-car.h206 #define TEGRA30_CLK_PLL_P 179 macro
/openbmc/u-boot/arch/arm/dts/
H A Dtegra30.dtsi165 <&tegra_car TEGRA30_CLK_PLL_P>;
184 <&tegra_car TEGRA30_CLK_PLL_P>;
/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30.dtsi233 <&tegra_car TEGRA30_CLK_PLL_P>;
265 <&tegra_car TEGRA30_CLK_PLL_P>;
H A Dtegra30-asus-transformer-common.dtsi112 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>;
H A Dtegra30-pegatron-chagall.dts94 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>;