Searched refs:TEGRA210_CLK_PLL_C4_OUT0 (Results 1 – 4 of 4) sorted by relevance
338 #define TEGRA210_CLK_PLL_C4_OUT0 308 macro
342 #define TEGRA210_CLK_PLL_C4_OUT0 308 macro
145 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;1224 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,1226 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;1290 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;1291 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
2534 [tegra_clk_pll_c4_out0] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT0, .present = true },2619 { .con_id = "pll_c4_out0", .dt_id = TEGRA210_CLK_PLL_C4_OUT0 },3373 clks[TEGRA210_CLK_PLL_C4_OUT0] = clk; in tegra210_pll_init()