xref: /openbmc/linux/drivers/gpu/drm/amd/include/soc21_enum.h (revision 4f2c0a4acffbec01079c28f839422e64ddeff004)
1  /*
2   * Copyright 2021 Advanced Micro Devices, Inc.
3   *
4   * Permission is hereby granted, free of charge, to any person obtaining a
5   * copy of this software and associated documentation files (the "Software"),
6   * to deal in the Software without restriction, including without limitation
7   * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8   * and/or sell copies of the Software, and to permit persons to whom the
9   * Software is furnished to do so, subject to the following conditions:
10   *
11   * The above copyright notice and this permission notice shall be included in
12   * all copies or substantial portions of the Software.
13   *
14   * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15   * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16   * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17   * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18   * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19   * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20   * OTHER DEALINGS IN THE SOFTWARE.
21   *
22   */
23  #if !defined (_soc21_ENUM_HEADER)
24  #define _soc21_ENUM_HEADER
25  
26  #ifndef _DRIVER_BUILD
27  #ifndef GL_ZERO
28  #define GL__ZERO                      BLEND_ZERO
29  #define GL__ONE                       BLEND_ONE
30  #define GL__SRC_COLOR                 BLEND_SRC_COLOR
31  #define GL__ONE_MINUS_SRC_COLOR       BLEND_ONE_MINUS_SRC_COLOR
32  #define GL__DST_COLOR                 BLEND_DST_COLOR
33  #define GL__ONE_MINUS_DST_COLOR       BLEND_ONE_MINUS_DST_COLOR
34  #define GL__SRC_ALPHA                 BLEND_SRC_ALPHA
35  #define GL__ONE_MINUS_SRC_ALPHA       BLEND_ONE_MINUS_SRC_ALPHA
36  #define GL__DST_ALPHA                 BLEND_DST_ALPHA
37  #define GL__ONE_MINUS_DST_ALPHA       BLEND_ONE_MINUS_DST_ALPHA
38  #define GL__SRC_ALPHA_SATURATE        BLEND_SRC_ALPHA_SATURATE
39  #define GL__CONSTANT_COLOR            BLEND_CONSTANT_COLOR
40  #define GL__ONE_MINUS_CONSTANT_COLOR  BLEND_ONE_MINUS_CONSTANT_COLOR
41  #define GL__CONSTANT_ALPHA            BLEND_CONSTANT_ALPHA
42  #define GL__ONE_MINUS_CONSTANT_ALPHA  BLEND_ONE_MINUS_CONSTANT_ALPHA
43  #endif
44  #endif
45  
46  /*******************************************************
47   * Chip Enums
48   *******************************************************/
49  
50  /*
51   * DSM_DATA_SEL enum
52   */
53  
54  typedef enum DSM_DATA_SEL {
55  DSM_DATA_SEL_DISABLE                     = 0x00000000,
56  DSM_DATA_SEL_0                           = 0x00000001,
57  DSM_DATA_SEL_1                           = 0x00000002,
58  DSM_DATA_SEL_BOTH                        = 0x00000003,
59  } DSM_DATA_SEL;
60  
61  /*
62   * DSM_ENABLE_ERROR_INJECT enum
63   */
64  
65  typedef enum DSM_ENABLE_ERROR_INJECT {
66  DSM_ENABLE_ERROR_INJECT_FED_IN           = 0x00000000,
67  DSM_ENABLE_ERROR_INJECT_SINGLE           = 0x00000001,
68  DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE    = 0x00000002,
69  DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED = 0x00000003,
70  } DSM_ENABLE_ERROR_INJECT;
71  
72  /*
73   * DSM_SELECT_INJECT_DELAY enum
74   */
75  
76  typedef enum DSM_SELECT_INJECT_DELAY {
77  DSM_SELECT_INJECT_DELAY_NO_DELAY         = 0x00000000,
78  DSM_SELECT_INJECT_DELAY_DELAY_ERROR      = 0x00000001,
79  } DSM_SELECT_INJECT_DELAY;
80  
81  /*
82   * DSM_SINGLE_WRITE enum
83   */
84  
85  typedef enum DSM_SINGLE_WRITE {
86  DSM_SINGLE_WRITE_DIS                     = 0x00000000,
87  DSM_SINGLE_WRITE_EN                      = 0x00000001,
88  } DSM_SINGLE_WRITE;
89  
90  /*
91   * ENUM_NUM_SIMD_PER_CU enum
92   */
93  
94  typedef enum ENUM_NUM_SIMD_PER_CU {
95  NUM_SIMD_PER_CU                          = 0x00000004,
96  } ENUM_NUM_SIMD_PER_CU;
97  
98  /*
99   * GATCL1RequestType enum
100   */
101  
102  typedef enum GATCL1RequestType {
103  GATCL1_TYPE_NORMAL                       = 0x00000000,
104  GATCL1_TYPE_SHOOTDOWN                    = 0x00000001,
105  GATCL1_TYPE_BYPASS                       = 0x00000002,
106  } GATCL1RequestType;
107  
108  /*
109   * GL0V_CACHE_POLICIES enum
110   */
111  
112  typedef enum GL0V_CACHE_POLICIES {
113  GL0V_CACHE_POLICY_MISS_LRU               = 0x00000000,
114  GL0V_CACHE_POLICY_MISS_EVICT             = 0x00000001,
115  GL0V_CACHE_POLICY_HIT_LRU                = 0x00000002,
116  GL0V_CACHE_POLICY_HIT_EVICT              = 0x00000003,
117  } GL0V_CACHE_POLICIES;
118  
119  /*
120   * GL1_CACHE_POLICIES enum
121   */
122  
123  typedef enum GL1_CACHE_POLICIES {
124  GL1_CACHE_POLICY_MISS_LRU                = 0x00000000,
125  GL1_CACHE_POLICY_MISS_EVICT              = 0x00000001,
126  GL1_CACHE_POLICY_HIT_LRU                 = 0x00000002,
127  GL1_CACHE_POLICY_HIT_EVICT               = 0x00000003,
128  } GL1_CACHE_POLICIES;
129  
130  /*
131   * GL1_CACHE_STORE_POLICIES enum
132   */
133  
134  typedef enum GL1_CACHE_STORE_POLICIES {
135  GL1_CACHE_STORE_POLICY_BYPASS            = 0x00000000,
136  } GL1_CACHE_STORE_POLICIES;
137  
138  /*
139   * GL2_CACHE_POLICIES enum
140   */
141  
142  typedef enum GL2_CACHE_POLICIES {
143  GL2_CACHE_POLICY_LRU                     = 0x00000000,
144  GL2_CACHE_POLICY_STREAM                  = 0x00000001,
145  GL2_CACHE_POLICY_NOA                     = 0x00000002,
146  GL2_CACHE_POLICY_BYPASS                  = 0x00000003,
147  } GL2_CACHE_POLICIES;
148  
149  /*
150   * Hdp_SurfaceEndian enum
151   */
152  
153  typedef enum Hdp_SurfaceEndian {
154  HDP_ENDIAN_NONE                          = 0x00000000,
155  HDP_ENDIAN_8IN16                         = 0x00000001,
156  HDP_ENDIAN_8IN32                         = 0x00000002,
157  HDP_ENDIAN_8IN64                         = 0x00000003,
158  } Hdp_SurfaceEndian;
159  
160  /*
161   * MTYPE enum
162   */
163  
164  typedef enum MTYPE {
165  MTYPE_C_RW_US                            = 0x00000000,
166  MTYPE_RESERVED_1                         = 0x00000001,
167  MTYPE_C_RO_S                             = 0x00000002,
168  MTYPE_UC                                 = 0x00000003,
169  MTYPE_C_RW_S                             = 0x00000004,
170  MTYPE_RESERVED_5                         = 0x00000005,
171  MTYPE_C_RO_US                            = 0x00000006,
172  MTYPE_RESERVED_7                         = 0x00000007,
173  } MTYPE;
174  
175  /*
176   * PERFMON_COUNTER_MODE enum
177   */
178  
179  typedef enum PERFMON_COUNTER_MODE {
180  PERFMON_COUNTER_MODE_ACCUM               = 0x00000000,
181  PERFMON_COUNTER_MODE_ACTIVE_CYCLES       = 0x00000001,
182  PERFMON_COUNTER_MODE_MAX                 = 0x00000002,
183  PERFMON_COUNTER_MODE_DIRTY               = 0x00000003,
184  PERFMON_COUNTER_MODE_SAMPLE              = 0x00000004,
185  PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x00000005,
186  PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x00000006,
187  PERFMON_COUNTER_MODE_CYCLES_GE_HI        = 0x00000007,
188  PERFMON_COUNTER_MODE_CYCLES_EQ_HI        = 0x00000008,
189  PERFMON_COUNTER_MODE_INACTIVE_CYCLES     = 0x00000009,
190  PERFMON_COUNTER_MODE_RESERVED            = 0x0000000f,
191  } PERFMON_COUNTER_MODE;
192  
193  /*
194   * PERFMON_SPM_MODE enum
195   */
196  
197  typedef enum PERFMON_SPM_MODE {
198  PERFMON_SPM_MODE_OFF                     = 0x00000000,
199  PERFMON_SPM_MODE_16BIT_CLAMP             = 0x00000001,
200  PERFMON_SPM_MODE_16BIT_NO_CLAMP          = 0x00000002,
201  PERFMON_SPM_MODE_32BIT_CLAMP             = 0x00000003,
202  PERFMON_SPM_MODE_32BIT_NO_CLAMP          = 0x00000004,
203  PERFMON_SPM_MODE_RESERVED_5              = 0x00000005,
204  PERFMON_SPM_MODE_RESERVED_6              = 0x00000006,
205  PERFMON_SPM_MODE_RESERVED_7              = 0x00000007,
206  PERFMON_SPM_MODE_TEST_MODE_0             = 0x00000008,
207  PERFMON_SPM_MODE_TEST_MODE_1             = 0x00000009,
208  PERFMON_SPM_MODE_TEST_MODE_2             = 0x0000000a,
209  } PERFMON_SPM_MODE;
210  
211  /*
212   * RMI_CID enum
213   */
214  
215  typedef enum RMI_CID {
216  RMI_CID_CC                               = 0x00000000,
217  RMI_CID_FC                               = 0x00000001,
218  RMI_CID_CM                               = 0x00000002,
219  RMI_CID_DC                               = 0x00000003,
220  RMI_CID_Z                                = 0x00000004,
221  RMI_CID_S                                = 0x00000005,
222  RMI_CID_TILE                             = 0x00000006,
223  RMI_CID_ZPCPSD                           = 0x00000007,
224  } RMI_CID;
225  
226  /*
227   * ReadPolicy enum
228   */
229  
230  typedef enum ReadPolicy {
231  CACHE_LRU_RD                             = 0x00000000,
232  CACHE_STREAM_RD                          = 0x00000001,
233  CACHE_NOA                                = 0x00000002,
234  RESERVED_RDPOLICY                        = 0x00000003,
235  } ReadPolicy;
236  
237  /*
238   * SDMA_PERFMON_SEL enum
239   */
240  
241  typedef enum SDMA_PERFMON_SEL {
242  SDMA_PERFMON_SEL_CYCLE                   = 0x00000000,
243  SDMA_PERFMON_SEL_IDLE                    = 0x00000001,
244  SDMA_PERFMON_SEL_REG_IDLE                = 0x00000002,
245  SDMA_PERFMON_SEL_RB_EMPTY                = 0x00000003,
246  SDMA_PERFMON_SEL_RB_FULL                 = 0x00000004,
247  SDMA_PERFMON_SEL_RB_WPTR_WRAP            = 0x00000005,
248  SDMA_PERFMON_SEL_RB_RPTR_WRAP            = 0x00000006,
249  SDMA_PERFMON_SEL_RB_WPTR_POLL_READ       = 0x00000007,
250  SDMA_PERFMON_SEL_RB_RPTR_WB              = 0x00000008,
251  SDMA_PERFMON_SEL_RB_CMD_IDLE             = 0x00000009,
252  SDMA_PERFMON_SEL_RB_CMD_FULL             = 0x0000000a,
253  SDMA_PERFMON_SEL_IB_CMD_IDLE             = 0x0000000b,
254  SDMA_PERFMON_SEL_IB_CMD_FULL             = 0x0000000c,
255  SDMA_PERFMON_SEL_EX_IDLE                 = 0x0000000d,
256  SDMA_PERFMON_SEL_SRBM_REG_SEND           = 0x0000000e,
257  SDMA_PERFMON_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0x0000000f,
258  SDMA_PERFMON_SEL_WR_BA_RTR               = 0x00000010,
259  SDMA_PERFMON_SEL_MC_WR_IDLE              = 0x00000011,
260  SDMA_PERFMON_SEL_MC_WR_COUNT             = 0x00000012,
261  SDMA_PERFMON_SEL_RD_BA_RTR               = 0x00000013,
262  SDMA_PERFMON_SEL_MC_RD_IDLE              = 0x00000014,
263  SDMA_PERFMON_SEL_MC_RD_COUNT             = 0x00000015,
264  SDMA_PERFMON_SEL_MC_RD_RET_STALL         = 0x00000016,
265  SDMA_PERFMON_SEL_MC_RD_NO_POLL_IDLE      = 0x00000017,
266  SDMA_PERFMON_SEL_SEM_IDLE                = 0x0000001a,
267  SDMA_PERFMON_SEL_SEM_REQ_STALL           = 0x0000001b,
268  SDMA_PERFMON_SEL_SEM_REQ_COUNT           = 0x0000001c,
269  SDMA_PERFMON_SEL_SEM_RESP_INCOMPLETE     = 0x0000001d,
270  SDMA_PERFMON_SEL_SEM_RESP_FAIL           = 0x0000001e,
271  SDMA_PERFMON_SEL_SEM_RESP_PASS           = 0x0000001f,
272  SDMA_PERFMON_SEL_INT_IDLE                = 0x00000020,
273  SDMA_PERFMON_SEL_INT_REQ_STALL           = 0x00000021,
274  SDMA_PERFMON_SEL_INT_REQ_COUNT           = 0x00000022,
275  SDMA_PERFMON_SEL_INT_RESP_ACCEPTED       = 0x00000023,
276  SDMA_PERFMON_SEL_INT_RESP_RETRY          = 0x00000024,
277  SDMA_PERFMON_SEL_NUM_PACKET              = 0x00000025,
278  SDMA_PERFMON_SEL_CE_WREQ_IDLE            = 0x00000027,
279  SDMA_PERFMON_SEL_CE_WR_IDLE              = 0x00000028,
280  SDMA_PERFMON_SEL_CE_SPLIT_IDLE           = 0x00000029,
281  SDMA_PERFMON_SEL_CE_RREQ_IDLE            = 0x0000002a,
282  SDMA_PERFMON_SEL_CE_OUT_IDLE             = 0x0000002b,
283  SDMA_PERFMON_SEL_CE_IN_IDLE              = 0x0000002c,
284  SDMA_PERFMON_SEL_CE_DST_IDLE             = 0x0000002d,
285  SDMA_PERFMON_SEL_CE_AFIFO_FULL           = 0x00000030,
286  SDMA_PERFMON_SEL_CE_INFO_FULL            = 0x00000033,
287  SDMA_PERFMON_SEL_CE_INFO1_FULL           = 0x00000034,
288  SDMA_PERFMON_SEL_CE_RD_STALL             = 0x00000035,
289  SDMA_PERFMON_SEL_CE_WR_STALL             = 0x00000036,
290  SDMA_PERFMON_SEL_GFX_SELECT              = 0x00000037,
291  SDMA_PERFMON_SEL_RLC0_SELECT             = 0x00000038,
292  SDMA_PERFMON_SEL_RLC1_SELECT             = 0x00000039,
293  SDMA_PERFMON_SEL_PAGE_SELECT             = 0x0000003a,
294  SDMA_PERFMON_SEL_CTX_CHANGE              = 0x0000003b,
295  SDMA_PERFMON_SEL_CTX_CHANGE_EXPIRED      = 0x0000003c,
296  SDMA_PERFMON_SEL_CTX_CHANGE_EXCEPTION    = 0x0000003d,
297  SDMA_PERFMON_SEL_DOORBELL                = 0x0000003e,
298  SDMA_PERFMON_SEL_F32_L1_WR_VLD           = 0x0000003f,
299  SDMA_PERFMON_SEL_CE_L1_WR_VLD            = 0x00000040,
300  SDMA_PERFMON_SEL_CPF_SDMA_INVREQ         = 0x00000041,
301  SDMA_PERFMON_SEL_SDMA_CPF_INVACK         = 0x00000042,
302  SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ       = 0x00000043,
303  SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK       = 0x00000044,
304  SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ_ALL   = 0x00000045,
305  SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK_ALL   = 0x00000046,
306  SDMA_PERFMON_SEL_UTCL2_RET_XNACK         = 0x00000047,
307  SDMA_PERFMON_SEL_UTCL2_RET_ACK           = 0x00000048,
308  SDMA_PERFMON_SEL_UTCL2_FREE              = 0x00000049,
309  SDMA_PERFMON_SEL_SDMA_UTCL2_SEND         = 0x0000004a,
310  SDMA_PERFMON_SEL_DMA_L1_WR_SEND          = 0x0000004b,
311  SDMA_PERFMON_SEL_DMA_L1_RD_SEND          = 0x0000004c,
312  SDMA_PERFMON_SEL_DMA_MC_WR_SEND          = 0x0000004d,
313  SDMA_PERFMON_SEL_DMA_MC_RD_SEND          = 0x0000004e,
314  SDMA_PERFMON_SEL_GPUVM_INV_HIGH          = 0x0000004f,
315  SDMA_PERFMON_SEL_GPUVM_INV_LOW           = 0x00000050,
316  SDMA_PERFMON_SEL_L1_WRL2_IDLE            = 0x00000051,
317  SDMA_PERFMON_SEL_L1_RDL2_IDLE            = 0x00000052,
318  SDMA_PERFMON_SEL_L1_WRMC_IDLE            = 0x00000053,
319  SDMA_PERFMON_SEL_L1_RDMC_IDLE            = 0x00000054,
320  SDMA_PERFMON_SEL_L1_WR_INV_IDLE          = 0x00000055,
321  SDMA_PERFMON_SEL_L1_RD_INV_IDLE          = 0x00000056,
322  SDMA_PERFMON_SEL_META_L2_REQ_SEND        = 0x00000057,
323  SDMA_PERFMON_SEL_L2_META_RET_VLD         = 0x00000058,
324  SDMA_PERFMON_SEL_SDMA_UTCL2_RD_SEND      = 0x00000059,
325  SDMA_PERFMON_SEL_UTCL2_SDMA_RD_RTN       = 0x0000005a,
326  SDMA_PERFMON_SEL_SDMA_UTCL2_WR_SEND      = 0x0000005b,
327  SDMA_PERFMON_SEL_UTCL2_SDMA_WR_RTN       = 0x0000005c,
328  SDMA_PERFMON_SEL_META_REQ_SEND           = 0x0000005d,
329  SDMA_PERFMON_SEL_META_RTN_VLD            = 0x0000005e,
330  SDMA_PERFMON_SEL_TLBI_SEND               = 0x0000005f,
331  SDMA_PERFMON_SEL_TLBI_RTN                = 0x00000060,
332  SDMA_PERFMON_SEL_GCR_SEND                = 0x00000061,
333  SDMA_PERFMON_SEL_GCR_RTN                 = 0x00000062,
334  SDMA_PERFMON_SEL_UTCL1_TAG_DELAY_COUNTER = 0x00000063,
335  SDMA_PERFMON_SEL_MMHUB_TAG_DELAY_COUNTER = 0x00000064,
336  } SDMA_PERFMON_SEL;
337  
338  /*
339   * SDMA_PERF_SEL enum
340   */
341  
342  typedef enum SDMA_PERF_SEL {
343  SDMA_PERF_SEL_CYCLE                      = 0x00000000,
344  SDMA_PERF_SEL_IDLE                       = 0x00000001,
345  SDMA_PERF_SEL_REG_IDLE                   = 0x00000002,
346  SDMA_PERF_SEL_RB_EMPTY                   = 0x00000003,
347  SDMA_PERF_SEL_RB_FULL                    = 0x00000004,
348  SDMA_PERF_SEL_RB_WPTR_WRAP               = 0x00000005,
349  SDMA_PERF_SEL_RB_RPTR_WRAP               = 0x00000006,
350  SDMA_PERF_SEL_RB_WPTR_POLL_READ          = 0x00000007,
351  SDMA_PERF_SEL_RB_RPTR_WB                 = 0x00000008,
352  SDMA_PERF_SEL_RB_CMD_IDLE                = 0x00000009,
353  SDMA_PERF_SEL_RB_CMD_FULL                = 0x0000000a,
354  SDMA_PERF_SEL_IB_CMD_IDLE                = 0x0000000b,
355  SDMA_PERF_SEL_IB_CMD_FULL                = 0x0000000c,
356  SDMA_PERF_SEL_EX_IDLE                    = 0x0000000d,
357  SDMA_PERF_SEL_SRBM_REG_SEND              = 0x0000000e,
358  SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE  = 0x0000000f,
359  SDMA_PERF_SEL_MC_WR_IDLE                 = 0x00000010,
360  SDMA_PERF_SEL_MC_WR_COUNT                = 0x00000011,
361  SDMA_PERF_SEL_MC_RD_IDLE                 = 0x00000012,
362  SDMA_PERF_SEL_MC_RD_COUNT                = 0x00000013,
363  SDMA_PERF_SEL_MC_RD_RET_STALL            = 0x00000014,
364  SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE         = 0x00000015,
365  SDMA_PERF_SEL_SEM_IDLE                   = 0x00000018,
366  SDMA_PERF_SEL_SEM_REQ_STALL              = 0x00000019,
367  SDMA_PERF_SEL_SEM_REQ_COUNT              = 0x0000001a,
368  SDMA_PERF_SEL_SEM_RESP_INCOMPLETE        = 0x0000001b,
369  SDMA_PERF_SEL_SEM_RESP_FAIL              = 0x0000001c,
370  SDMA_PERF_SEL_SEM_RESP_PASS              = 0x0000001d,
371  SDMA_PERF_SEL_INT_IDLE                   = 0x0000001e,
372  SDMA_PERF_SEL_INT_REQ_STALL              = 0x0000001f,
373  SDMA_PERF_SEL_INT_REQ_COUNT              = 0x00000020,
374  SDMA_PERF_SEL_INT_RESP_ACCEPTED          = 0x00000021,
375  SDMA_PERF_SEL_INT_RESP_RETRY             = 0x00000022,
376  SDMA_PERF_SEL_NUM_PACKET                 = 0x00000023,
377  SDMA_PERF_SEL_CE_WREQ_IDLE               = 0x00000025,
378  SDMA_PERF_SEL_CE_WR_IDLE                 = 0x00000026,
379  SDMA_PERF_SEL_CE_SPLIT_IDLE              = 0x00000027,
380  SDMA_PERF_SEL_CE_RREQ_IDLE               = 0x00000028,
381  SDMA_PERF_SEL_CE_OUT_IDLE                = 0x00000029,
382  SDMA_PERF_SEL_CE_IN_IDLE                 = 0x0000002a,
383  SDMA_PERF_SEL_CE_DST_IDLE                = 0x0000002b,
384  SDMA_PERF_SEL_CE_AFIFO_FULL              = 0x0000002e,
385  SDMA_PERF_SEL_CE_INFO_FULL               = 0x00000031,
386  SDMA_PERF_SEL_CE_INFO1_FULL              = 0x00000032,
387  SDMA_PERF_SEL_CE_RD_STALL                = 0x00000033,
388  SDMA_PERF_SEL_CE_WR_STALL                = 0x00000034,
389  SDMA_PERF_SEL_GFX_SELECT                 = 0x00000035,
390  SDMA_PERF_SEL_RLC0_SELECT                = 0x00000036,
391  SDMA_PERF_SEL_RLC1_SELECT                = 0x00000037,
392  SDMA_PERF_SEL_PAGE_SELECT                = 0x00000038,
393  SDMA_PERF_SEL_CTX_CHANGE                 = 0x00000039,
394  SDMA_PERF_SEL_CTX_CHANGE_EXPIRED         = 0x0000003a,
395  SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION       = 0x0000003b,
396  SDMA_PERF_SEL_DOORBELL                   = 0x0000003c,
397  SDMA_PERF_SEL_RD_BA_RTR                  = 0x0000003d,
398  SDMA_PERF_SEL_WR_BA_RTR                  = 0x0000003e,
399  SDMA_PERF_SEL_F32_L1_WR_VLD              = 0x0000003f,
400  SDMA_PERF_SEL_CE_L1_WR_VLD               = 0x00000040,
401  SDMA_PERF_SEL_CPF_SDMA_INVREQ            = 0x00000041,
402  SDMA_PERF_SEL_SDMA_CPF_INVACK            = 0x00000042,
403  SDMA_PERF_SEL_UTCL2_SDMA_INVREQ          = 0x00000043,
404  SDMA_PERF_SEL_SDMA_UTCL2_INVACK          = 0x00000044,
405  SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL      = 0x00000045,
406  SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL      = 0x00000046,
407  SDMA_PERF_SEL_UTCL2_RET_XNACK            = 0x00000047,
408  SDMA_PERF_SEL_UTCL2_RET_ACK              = 0x00000048,
409  SDMA_PERF_SEL_UTCL2_FREE                 = 0x00000049,
410  SDMA_PERF_SEL_SDMA_UTCL2_SEND            = 0x0000004a,
411  SDMA_PERF_SEL_DMA_L1_WR_SEND             = 0x0000004b,
412  SDMA_PERF_SEL_DMA_L1_RD_SEND             = 0x0000004c,
413  SDMA_PERF_SEL_DMA_MC_WR_SEND             = 0x0000004d,
414  SDMA_PERF_SEL_DMA_MC_RD_SEND             = 0x0000004e,
415  SDMA_PERF_SEL_GPUVM_INV_HIGH             = 0x0000004f,
416  SDMA_PERF_SEL_GPUVM_INV_LOW              = 0x00000050,
417  SDMA_PERF_SEL_L1_WRL2_IDLE               = 0x00000051,
418  SDMA_PERF_SEL_L1_RDL2_IDLE               = 0x00000052,
419  SDMA_PERF_SEL_L1_WRMC_IDLE               = 0x00000053,
420  SDMA_PERF_SEL_L1_RDMC_IDLE               = 0x00000054,
421  SDMA_PERF_SEL_L1_WR_INV_IDLE             = 0x00000055,
422  SDMA_PERF_SEL_L1_RD_INV_IDLE             = 0x00000056,
423  SDMA_PERF_SEL_META_L2_REQ_SEND           = 0x00000057,
424  SDMA_PERF_SEL_L2_META_RET_VLD            = 0x00000058,
425  SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND         = 0x00000059,
426  SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN          = 0x0000005a,
427  SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND         = 0x0000005b,
428  SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN          = 0x0000005c,
429  SDMA_PERF_SEL_META_REQ_SEND              = 0x0000005d,
430  SDMA_PERF_SEL_META_RTN_VLD               = 0x0000005e,
431  SDMA_PERF_SEL_TLBI_SEND                  = 0x0000005f,
432  SDMA_PERF_SEL_TLBI_RTN                   = 0x00000060,
433  SDMA_PERF_SEL_GCR_SEND                   = 0x00000061,
434  SDMA_PERF_SEL_GCR_RTN                    = 0x00000062,
435  SDMA_PERF_SEL_CGCG_FENCE                 = 0x00000063,
436  SDMA_PERF_SEL_CE_CH_WR_REQ               = 0x00000064,
437  SDMA_PERF_SEL_CE_CH_WR_RET               = 0x00000065,
438  SDMA_PERF_SEL_F32_CH_WR_REQ              = 0x00000066,
439  SDMA_PERF_SEL_F32_CH_WR_RET              = 0x00000067,
440  SDMA_PERF_SEL_CE_OR_F32_CH_RD_REQ        = 0x00000068,
441  SDMA_PERF_SEL_CE_OR_F32_CH_RD_RET        = 0x00000069,
442  SDMA_PERF_SEL_RB_CH_RD_REQ               = 0x0000006a,
443  SDMA_PERF_SEL_RB_CH_RD_RET               = 0x0000006b,
444  SDMA_PERF_SEL_IB_CH_RD_REQ               = 0x0000006c,
445  SDMA_PERF_SEL_IB_CH_RD_RET               = 0x0000006d,
446  SDMA_PERF_SEL_WPTR_CH_RD_REQ             = 0x0000006e,
447  SDMA_PERF_SEL_WPTR_CH_RD_RET             = 0x0000006f,
448  SDMA_PERF_SEL_UTCL1_UTCL2_REQ            = 0x00000070,
449  SDMA_PERF_SEL_UTCL1_UTCL2_RET            = 0x00000071,
450  SDMA_PERF_SEL_CMD_OP_MATCH               = 0x00000072,
451  SDMA_PERF_SEL_CMD_OP_START               = 0x00000073,
452  SDMA_PERF_SEL_CMD_OP_END                 = 0x00000074,
453  SDMA_PERF_SEL_CE_BUSY                    = 0x00000075,
454  SDMA_PERF_SEL_CE_BUSY_START              = 0x00000076,
455  SDMA_PERF_SEL_CE_BUSY_END                = 0x00000077,
456  SDMA_PERF_SEL_F32_PERFCNT_TRIGGER        = 0x00000078,
457  SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START  = 0x00000079,
458  SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END    = 0x0000007a,
459  SDMA_PERF_SEL_CE_CH_WRREQ_SEND           = 0x0000007b,
460  SDMA_PERF_SEL_CH_CE_WRRET_VALID          = 0x0000007c,
461  SDMA_PERF_SEL_CE_CH_RDREQ_SEND           = 0x0000007d,
462  SDMA_PERF_SEL_CH_CE_RDRET_VALID          = 0x0000007e,
463  } SDMA_PERF_SEL;
464  
465  /*
466   * TCC_CACHE_POLICIES enum
467   */
468  
469  typedef enum TCC_CACHE_POLICIES {
470  TCC_CACHE_POLICY_LRU                     = 0x00000000,
471  TCC_CACHE_POLICY_STREAM                  = 0x00000001,
472  } TCC_CACHE_POLICIES;
473  
474  /*
475   * TCC_MTYPE enum
476   */
477  
478  typedef enum TCC_MTYPE {
479  MTYPE_NC                                 = 0x00000000,
480  MTYPE_WC                                 = 0x00000001,
481  MTYPE_CC                                 = 0x00000002,
482  } TCC_MTYPE;
483  
484  /*
485   * UTCL0FaultType enum
486   */
487  
488  typedef enum UTCL0FaultType {
489  UTCL0_XNACK_SUCCESS                      = 0x00000000,
490  UTCL0_XNACK_RETRY                        = 0x00000001,
491  UTCL0_XNACK_PRT                          = 0x00000002,
492  UTCL0_XNACK_NO_RETRY                     = 0x00000003,
493  } UTCL0FaultType;
494  
495  /*
496   * UTCL0RequestType enum
497   */
498  
499  typedef enum UTCL0RequestType {
500  UTCL0_TYPE_NORMAL                        = 0x00000000,
501  UTCL0_TYPE_SHOOTDOWN                     = 0x00000001,
502  UTCL0_TYPE_BYPASS                        = 0x00000002,
503  } UTCL0RequestType;
504  
505  /*
506   * UTCL1FaultType enum
507   */
508  
509  typedef enum UTCL1FaultType {
510  UTCL1_XNACK_SUCCESS                      = 0x00000000,
511  UTCL1_XNACK_RETRY                        = 0x00000001,
512  UTCL1_XNACK_PRT                          = 0x00000002,
513  UTCL1_XNACK_NO_RETRY                     = 0x00000003,
514  } UTCL1FaultType;
515  
516  /*
517   * UTCL1RequestType enum
518   */
519  
520  typedef enum UTCL1RequestType {
521  UTCL1_TYPE_NORMAL                        = 0x00000000,
522  UTCL1_TYPE_SHOOTDOWN                     = 0x00000001,
523  UTCL1_TYPE_BYPASS                        = 0x00000002,
524  } UTCL1RequestType;
525  
526  /*
527   * VMEMCMD_RETURN_ORDER enum
528   */
529  
530  typedef enum VMEMCMD_RETURN_ORDER {
531  VMEMCMD_RETURN_OUT_OF_ORDER              = 0x00000000,
532  VMEMCMD_RETURN_IN_ORDER                  = 0x00000001,
533  VMEMCMD_RETURN_IN_ORDER_READ             = 0x00000002,
534  } VMEMCMD_RETURN_ORDER;
535  
536  /*
537   * WritePolicy enum
538   */
539  
540  typedef enum WritePolicy {
541  CACHE_LRU_WR                             = 0x00000000,
542  CACHE_STREAM                             = 0x00000001,
543  CACHE_NOA_WR                             = 0x00000002,
544  CACHE_BYPASS                             = 0x00000003,
545  } WritePolicy;
546  
547  /*******************************************************
548   * CNVC_CFG Enums
549   *******************************************************/
550  
551  /*
552   * CNVC_BYPASS enum
553   */
554  
555  typedef enum CNVC_BYPASS {
556  CNVC_BYPASS_DISABLE                      = 0x00000000,
557  CNVC_BYPASS_EN                           = 0x00000001,
558  } CNVC_BYPASS;
559  
560  /*
561   * CNVC_COEF_FORMAT_ENUM enum
562   */
563  
564  typedef enum CNVC_COEF_FORMAT_ENUM {
565  CNVC_FIX_S2_13                           = 0x00000000,
566  CNVC_FIX_S3_12                           = 0x00000001,
567  } CNVC_COEF_FORMAT_ENUM;
568  
569  /*
570   * CNVC_ENABLE enum
571   */
572  
573  typedef enum CNVC_ENABLE {
574  CNVC_DIS                                 = 0x00000000,
575  CNVC_EN                                  = 0x00000001,
576  } CNVC_ENABLE;
577  
578  /*
579   * CNVC_PENDING enum
580   */
581  
582  typedef enum CNVC_PENDING {
583  CNVC_NOT_PENDING                         = 0x00000000,
584  CNVC_YES_PENDING                         = 0x00000001,
585  } CNVC_PENDING;
586  
587  /*
588   * COLOR_KEYER_MODE enum
589   */
590  
591  typedef enum COLOR_KEYER_MODE {
592  FORCE_00                                 = 0x00000000,
593  FORCE_FF                                 = 0x00000001,
594  RANGE_00                                 = 0x00000002,
595  RANGE_FF                                 = 0x00000003,
596  } COLOR_KEYER_MODE;
597  
598  /*
599   * DENORM_TRUNCATE enum
600   */
601  
602  typedef enum DENORM_TRUNCATE {
603  CNVC_ROUND                               = 0x00000000,
604  CNVC_TRUNCATE                            = 0x00000001,
605  } DENORM_TRUNCATE;
606  
607  /*
608   * FORMAT_CROSSBAR enum
609   */
610  
611  typedef enum FORMAT_CROSSBAR {
612  FORMAT_CROSSBAR_R                        = 0x00000000,
613  FORMAT_CROSSBAR_G                        = 0x00000001,
614  FORMAT_CROSSBAR_B                        = 0x00000002,
615  } FORMAT_CROSSBAR;
616  
617  /*
618   * PIX_EXPAND_MODE enum
619   */
620  
621  typedef enum PIX_EXPAND_MODE {
622  PIX_DYNAMIC_EXPANSION                    = 0x00000000,
623  PIX_ZERO_EXPANSION                       = 0x00000001,
624  } PIX_EXPAND_MODE;
625  
626  /*
627   * PRE_CSC_MODE_ENUM enum
628   */
629  
630  typedef enum PRE_CSC_MODE_ENUM {
631  PRE_CSC_BYPASS                           = 0x00000000,
632  PRE_CSC_SET_A                            = 0x00000001,
633  PRE_CSC_SET_B                            = 0x00000002,
634  } PRE_CSC_MODE_ENUM;
635  
636  /*
637   * PRE_DEGAM_MODE enum
638   */
639  
640  typedef enum PRE_DEGAM_MODE {
641  PRE_DEGAM_BYPASS                         = 0x00000000,
642  PRE_DEGAM_ENABLE                         = 0x00000001,
643  } PRE_DEGAM_MODE;
644  
645  /*
646   * PRE_DEGAM_SELECT enum
647   */
648  
649  typedef enum PRE_DEGAM_SELECT {
650  PRE_DEGAM_SRGB                           = 0x00000000,
651  PRE_DEGAM_GAMMA_22                       = 0x00000001,
652  PRE_DEGAM_GAMMA_24                       = 0x00000002,
653  PRE_DEGAM_GAMMA_26                       = 0x00000003,
654  PRE_DEGAM_BT2020                         = 0x00000004,
655  PRE_DEGAM_BT2100PQ                       = 0x00000005,
656  PRE_DEGAM_BT2100HLG                      = 0x00000006,
657  } PRE_DEGAM_SELECT;
658  
659  /*
660   * SURFACE_PIXEL_FORMAT enum
661   */
662  
663  typedef enum SURFACE_PIXEL_FORMAT {
664  ARGB1555                                 = 0x00000001,
665  RGBA5551                                 = 0x00000002,
666  RGB565                                   = 0x00000003,
667  BGR565                                   = 0x00000004,
668  ARGB4444                                 = 0x00000005,
669  RGBA4444                                 = 0x00000006,
670  ARGB8888                                 = 0x00000008,
671  RGBA8888                                 = 0x00000009,
672  ARGB2101010                              = 0x0000000a,
673  RGBA1010102                              = 0x0000000b,
674  AYCrCb8888                               = 0x0000000c,
675  YCrCbA8888                               = 0x0000000d,
676  ACrYCb8888                               = 0x0000000e,
677  CrYCbA8888                               = 0x0000000f,
678  ARGB16161616_10MSB                       = 0x00000010,
679  RGBA16161616_10MSB                       = 0x00000011,
680  ARGB16161616_10LSB                       = 0x00000012,
681  RGBA16161616_10LSB                       = 0x00000013,
682  ARGB16161616_12MSB                       = 0x00000014,
683  RGBA16161616_12MSB                       = 0x00000015,
684  ARGB16161616_12LSB                       = 0x00000016,
685  RGBA16161616_12LSB                       = 0x00000017,
686  ARGB16161616_FLOAT                       = 0x00000018,
687  RGBA16161616_FLOAT                       = 0x00000019,
688  ARGB16161616_UNORM                       = 0x0000001a,
689  RGBA16161616_UNORM                       = 0x0000001b,
690  ARGB16161616_SNORM                       = 0x0000001c,
691  RGBA16161616_SNORM                       = 0x0000001d,
692  AYCrCb16161616_10MSB                     = 0x00000020,
693  AYCrCb16161616_10LSB                     = 0x00000021,
694  YCrCbA16161616_10MSB                     = 0x00000022,
695  YCrCbA16161616_10LSB                     = 0x00000023,
696  ACrYCb16161616_10MSB                     = 0x00000024,
697  ACrYCb16161616_10LSB                     = 0x00000025,
698  CrYCbA16161616_10MSB                     = 0x00000026,
699  CrYCbA16161616_10LSB                     = 0x00000027,
700  AYCrCb16161616_12MSB                     = 0x00000028,
701  AYCrCb16161616_12LSB                     = 0x00000029,
702  YCrCbA16161616_12MSB                     = 0x0000002a,
703  YCrCbA16161616_12LSB                     = 0x0000002b,
704  ACrYCb16161616_12MSB                     = 0x0000002c,
705  ACrYCb16161616_12LSB                     = 0x0000002d,
706  CrYCbA16161616_12MSB                     = 0x0000002e,
707  CrYCbA16161616_12LSB                     = 0x0000002f,
708  Y8_CrCb88_420_PLANAR                     = 0x00000040,
709  Y8_CbCr88_420_PLANAR                     = 0x00000041,
710  Y10_CrCb1010_420_PLANAR                  = 0x00000042,
711  Y10_CbCr1010_420_PLANAR                  = 0x00000043,
712  Y12_CrCb1212_420_PLANAR                  = 0x00000044,
713  Y12_CbCr1212_420_PLANAR                  = 0x00000045,
714  YCrYCb8888_422_PACKED                    = 0x00000048,
715  YCbYCr8888_422_PACKED                    = 0x00000049,
716  CrYCbY8888_422_PACKED                    = 0x0000004a,
717  CbYCrY8888_422_PACKED                    = 0x0000004b,
718  YCrYCb10101010_422_PACKED                = 0x0000004c,
719  YCbYCr10101010_422_PACKED                = 0x0000004d,
720  CrYCbY10101010_422_PACKED                = 0x0000004e,
721  CbYCrY10101010_422_PACKED                = 0x0000004f,
722  YCrYCb12121212_422_PACKED                = 0x00000050,
723  YCbYCr12121212_422_PACKED                = 0x00000051,
724  CrYCbY12121212_422_PACKED                = 0x00000052,
725  CbYCrY12121212_422_PACKED                = 0x00000053,
726  RGB111110_FIX                            = 0x00000070,
727  BGR101111_FIX                            = 0x00000071,
728  ACrYCb2101010                            = 0x00000072,
729  CrYCbA1010102                            = 0x00000073,
730  RGBE                                     = 0x00000074,
731  RGB111110_FLOAT                          = 0x00000076,
732  BGR101111_FLOAT                          = 0x00000077,
733  MONO_8                                   = 0x00000078,
734  MONO_10MSB                               = 0x00000079,
735  MONO_10LSB                               = 0x0000007a,
736  MONO_12MSB                               = 0x0000007b,
737  MONO_12LSB                               = 0x0000007c,
738  MONO_16                                  = 0x0000007d,
739  } SURFACE_PIXEL_FORMAT;
740  
741  /*
742   * XNORM enum
743   */
744  
745  typedef enum XNORM {
746  XNORM_A                                  = 0x00000000,
747  XNORM_B                                  = 0x00000001,
748  } XNORM;
749  
750  /*******************************************************
751   * CNVC_CUR Enums
752   *******************************************************/
753  
754  /*
755   * CUR_ENABLE enum
756   */
757  
758  typedef enum CUR_ENABLE {
759  CUR_DIS                                  = 0x00000000,
760  CUR_EN                                   = 0x00000001,
761  } CUR_ENABLE;
762  
763  /*
764   * CUR_EXPAND_MODE enum
765   */
766  
767  typedef enum CUR_EXPAND_MODE {
768  CUR_DYNAMIC_EXPANSION                    = 0x00000000,
769  CUR_ZERO_EXPANSION                       = 0x00000001,
770  } CUR_EXPAND_MODE;
771  
772  /*
773   * CUR_INV_CLAMP enum
774   */
775  
776  typedef enum CUR_INV_CLAMP {
777  CUR_CLAMP_DIS                            = 0x00000000,
778  CUR_CLAMP_EN                             = 0x00000001,
779  } CUR_INV_CLAMP;
780  
781  /*
782   * CUR_MODE enum
783   */
784  
785  typedef enum CUR_MODE {
786  MONO_2BIT                                = 0x00000000,
787  COLOR_24BIT_1BIT_AND                     = 0x00000001,
788  COLOR_24BIT_8BIT_ALPHA_PREMULT           = 0x00000002,
789  COLOR_24BIT_8BIT_ALPHA_UNPREMULT         = 0x00000003,
790  COLOR_64BIT_FP_PREMULT                   = 0x00000004,
791  COLOR_64BIT_FP_UNPREMULT                 = 0x00000005,
792  } CUR_MODE;
793  
794  /*
795   * CUR_PENDING enum
796   */
797  
798  typedef enum CUR_PENDING {
799  CUR_NOT_PENDING                          = 0x00000000,
800  CUR_YES_PENDING                          = 0x00000001,
801  } CUR_PENDING;
802  
803  /*
804   * CUR_ROM_EN enum
805   */
806  
807  typedef enum CUR_ROM_EN {
808  CUR_FP_NO_ROM                            = 0x00000000,
809  CUR_FP_USE_ROM                           = 0x00000001,
810  } CUR_ROM_EN;
811  
812  /*******************************************************
813   * DSCL Enums
814   *******************************************************/
815  
816  /*
817   * COEF_RAM_SELECT_RD enum
818   */
819  
820  typedef enum COEF_RAM_SELECT_RD {
821  COEF_RAM_SELECT_BACK                     = 0x00000000,
822  COEF_RAM_SELECT_CURRENT                  = 0x00000001,
823  } COEF_RAM_SELECT_RD;
824  
825  /*
826   * DSCL_MODE_SEL enum
827   */
828  
829  typedef enum DSCL_MODE_SEL {
830  DSCL_MODE_SCALING_444_BYPASS             = 0x00000000,
831  DSCL_MODE_SCALING_444_RGB_ENABLE         = 0x00000001,
832  DSCL_MODE_SCALING_444_YCBCR_ENABLE       = 0x00000002,
833  DSCL_MODE_SCALING_YCBCR_ENABLE           = 0x00000003,
834  DSCL_MODE_LUMA_SCALING_BYPASS            = 0x00000004,
835  DSCL_MODE_CHROMA_SCALING_BYPASS          = 0x00000005,
836  DSCL_MODE_DSCL_BYPASS                    = 0x00000006,
837  } DSCL_MODE_SEL;
838  
839  /*
840   * LB_ALPHA_EN enum
841   */
842  
843  typedef enum LB_ALPHA_EN {
844  LB_ALPHA_DISABLE                         = 0x00000000,
845  LB_ALPHA_ENABLE                          = 0x00000001,
846  } LB_ALPHA_EN;
847  
848  /*
849   * LB_INTERLEAVE_EN enum
850   */
851  
852  typedef enum LB_INTERLEAVE_EN {
853  LB_INTERLEAVE_DISABLE                    = 0x00000000,
854  LB_INTERLEAVE_ENABLE                     = 0x00000001,
855  } LB_INTERLEAVE_EN;
856  
857  /*
858   * LB_MEMORY_CONFIG enum
859   */
860  
861  typedef enum LB_MEMORY_CONFIG {
862  LB_MEMORY_CONFIG_0                       = 0x00000000,
863  LB_MEMORY_CONFIG_1                       = 0x00000001,
864  LB_MEMORY_CONFIG_2                       = 0x00000002,
865  LB_MEMORY_CONFIG_3                       = 0x00000003,
866  } LB_MEMORY_CONFIG;
867  
868  /*
869   * OBUF_BYPASS_SEL enum
870   */
871  
872  typedef enum OBUF_BYPASS_SEL {
873  OBUF_BYPASS_DIS                          = 0x00000000,
874  OBUF_BYPASS_EN                           = 0x00000001,
875  } OBUF_BYPASS_SEL;
876  
877  /*
878   * OBUF_IS_HALF_RECOUT_WIDTH_SEL enum
879   */
880  
881  typedef enum OBUF_IS_HALF_RECOUT_WIDTH_SEL {
882  OBUF_FULL_RECOUT                         = 0x00000000,
883  OBUF_HALF_RECOUT                         = 0x00000001,
884  } OBUF_IS_HALF_RECOUT_WIDTH_SEL;
885  
886  /*
887   * OBUF_USE_FULL_BUFFER_SEL enum
888   */
889  
890  typedef enum OBUF_USE_FULL_BUFFER_SEL {
891  OBUF_RECOUT                              = 0x00000000,
892  OBUF_FULL                                = 0x00000001,
893  } OBUF_USE_FULL_BUFFER_SEL;
894  
895  /*
896   * SCL_2TAP_HARDCODE enum
897   */
898  
899  typedef enum SCL_2TAP_HARDCODE {
900  SCL_COEF_2TAP_HARDCODE_OFF               = 0x00000000,
901  SCL_COEF_2TAP_HARDCODE_ON                = 0x00000001,
902  } SCL_2TAP_HARDCODE;
903  
904  /*
905   * SCL_ALPHA_COEF enum
906   */
907  
908  typedef enum SCL_ALPHA_COEF {
909  SCL_ALPHA_COEF_FIRST                     = 0x00000000,
910  SCL_ALPHA_COEF_SECOND                    = 0x00000001,
911  } SCL_ALPHA_COEF;
912  
913  /*
914   * SCL_AUTOCAL_MODE enum
915   */
916  
917  typedef enum SCL_AUTOCAL_MODE {
918  AUTOCAL_MODE_OFF                         = 0x00000000,
919  AUTOCAL_MODE_AUTOSCALE                   = 0x00000001,
920  AUTOCAL_MODE_AUTOCENTER                  = 0x00000002,
921  AUTOCAL_MODE_AUTOREPLICATE               = 0x00000003,
922  } SCL_AUTOCAL_MODE;
923  
924  /*
925   * SCL_BOUNDARY enum
926   */
927  
928  typedef enum SCL_BOUNDARY {
929  SCL_BOUNDARY_EDGE                        = 0x00000000,
930  SCL_BOUNDARY_BLACK                       = 0x00000001,
931  } SCL_BOUNDARY;
932  
933  /*
934   * SCL_CHROMA_COEF enum
935   */
936  
937  typedef enum SCL_CHROMA_COEF {
938  SCL_CHROMA_COEF_FIRST                    = 0x00000000,
939  SCL_CHROMA_COEF_SECOND                   = 0x00000001,
940  } SCL_CHROMA_COEF;
941  
942  /*
943   * SCL_COEF_FILTER_TYPE_SEL enum
944   */
945  
946  typedef enum SCL_COEF_FILTER_TYPE_SEL {
947  SCL_COEF_LUMA_VERT_FILTER                = 0x00000000,
948  SCL_COEF_LUMA_HORZ_FILTER                = 0x00000001,
949  SCL_COEF_CHROMA_VERT_FILTER              = 0x00000002,
950  SCL_COEF_CHROMA_HORZ_FILTER              = 0x00000003,
951  } SCL_COEF_FILTER_TYPE_SEL;
952  
953  /*
954   * SCL_COEF_RAM_SEL enum
955   */
956  
957  typedef enum SCL_COEF_RAM_SEL {
958  SCL_COEF_RAM_SEL_0                       = 0x00000000,
959  SCL_COEF_RAM_SEL_1                       = 0x00000001,
960  } SCL_COEF_RAM_SEL;
961  
962  /*
963   * SCL_SHARP_EN enum
964   */
965  
966  typedef enum SCL_SHARP_EN {
967  SCL_SHARP_DISABLE                        = 0x00000000,
968  SCL_SHARP_ENABLE                         = 0x00000001,
969  } SCL_SHARP_EN;
970  
971  /*******************************************************
972   * CM Enums
973   *******************************************************/
974  
975  /*
976   * CMC_3DLUT_30BIT_ENUM enum
977   */
978  
979  typedef enum CMC_3DLUT_30BIT_ENUM {
980  CMC_3DLUT_36BIT                          = 0x00000000,
981  CMC_3DLUT_30BIT                          = 0x00000001,
982  } CMC_3DLUT_30BIT_ENUM;
983  
984  /*
985   * CMC_3DLUT_RAM_SEL enum
986   */
987  
988  typedef enum CMC_3DLUT_RAM_SEL {
989  CMC_RAM0_ACCESS                          = 0x00000000,
990  CMC_RAM1_ACCESS                          = 0x00000001,
991  CMC_RAM2_ACCESS                          = 0x00000002,
992  CMC_RAM3_ACCESS                          = 0x00000003,
993  } CMC_3DLUT_RAM_SEL;
994  
995  /*
996   * CMC_3DLUT_SIZE_ENUM enum
997   */
998  
999  typedef enum CMC_3DLUT_SIZE_ENUM {
1000  CMC_3DLUT_17CUBE                         = 0x00000000,
1001  CMC_3DLUT_9CUBE                          = 0x00000001,
1002  } CMC_3DLUT_SIZE_ENUM;
1003  
1004  /*
1005   * CMC_LUT_2_CONFIG_ENUM enum
1006   */
1007  
1008  typedef enum CMC_LUT_2_CONFIG_ENUM {
1009  CMC_LUT_2CFG_NO_MEMORY                   = 0x00000000,
1010  CMC_LUT_2CFG_MEMORY_A                    = 0x00000001,
1011  CMC_LUT_2CFG_MEMORY_B                    = 0x00000002,
1012  } CMC_LUT_2_CONFIG_ENUM;
1013  
1014  /*
1015   * CMC_LUT_2_MODE_ENUM enum
1016   */
1017  
1018  typedef enum CMC_LUT_2_MODE_ENUM {
1019  CMC_LUT_2_MODE_BYPASS                    = 0x00000000,
1020  CMC_LUT_2_MODE_RAMA_LUT                  = 0x00000001,
1021  CMC_LUT_2_MODE_RAMB_LUT                  = 0x00000002,
1022  } CMC_LUT_2_MODE_ENUM;
1023  
1024  /*
1025   * CMC_LUT_NUM_SEG enum
1026   */
1027  
1028  typedef enum CMC_LUT_NUM_SEG {
1029  CMC_SEGMENTS_1                           = 0x00000000,
1030  CMC_SEGMENTS_2                           = 0x00000001,
1031  CMC_SEGMENTS_4                           = 0x00000002,
1032  CMC_SEGMENTS_8                           = 0x00000003,
1033  CMC_SEGMENTS_16                          = 0x00000004,
1034  CMC_SEGMENTS_32                          = 0x00000005,
1035  CMC_SEGMENTS_64                          = 0x00000006,
1036  CMC_SEGMENTS_128                         = 0x00000007,
1037  } CMC_LUT_NUM_SEG;
1038  
1039  /*
1040   * CMC_LUT_RAM_SEL enum
1041   */
1042  
1043  typedef enum CMC_LUT_RAM_SEL {
1044  CMC_RAMA_ACCESS                          = 0x00000000,
1045  CMC_RAMB_ACCESS                          = 0x00000001,
1046  } CMC_LUT_RAM_SEL;
1047  
1048  /*
1049   * CM_BYPASS enum
1050   */
1051  
1052  typedef enum CM_BYPASS {
1053  NON_BYPASS                               = 0x00000000,
1054  BYPASS_EN                                = 0x00000001,
1055  } CM_BYPASS;
1056  
1057  /*
1058   * CM_COEF_FORMAT_ENUM enum
1059   */
1060  
1061  typedef enum CM_COEF_FORMAT_ENUM {
1062  FIX_S2_13                                = 0x00000000,
1063  FIX_S3_12                                = 0x00000001,
1064  } CM_COEF_FORMAT_ENUM;
1065  
1066  /*
1067   * CM_DATA_SIGNED enum
1068   */
1069  
1070  typedef enum CM_DATA_SIGNED {
1071  UNSIGNED                                 = 0x00000000,
1072  SIGNED                                   = 0x00000001,
1073  } CM_DATA_SIGNED;
1074  
1075  /*
1076   * CM_EN enum
1077   */
1078  
1079  typedef enum CM_EN {
1080  CM_DISABLE                               = 0x00000000,
1081  CM_ENABLE                                = 0x00000001,
1082  } CM_EN;
1083  
1084  /*
1085   * CM_GAMMA_LUT_MODE_ENUM enum
1086   */
1087  
1088  typedef enum CM_GAMMA_LUT_MODE_ENUM {
1089  BYPASS                                   = 0x00000000,
1090  RESERVED_1                               = 0x00000001,
1091  RAM_LUT                                  = 0x00000002,
1092  RESERVED_3                               = 0x00000003,
1093  } CM_GAMMA_LUT_MODE_ENUM;
1094  
1095  /*
1096   * CM_GAMMA_LUT_PWL_DISABLE_ENUM enum
1097   */
1098  
1099  typedef enum CM_GAMMA_LUT_PWL_DISABLE_ENUM {
1100  ENABLE_PWL                               = 0x00000000,
1101  DISABLE_PWL                              = 0x00000001,
1102  } CM_GAMMA_LUT_PWL_DISABLE_ENUM;
1103  
1104  /*
1105   * CM_GAMMA_LUT_SEL_ENUM enum
1106   */
1107  
1108  typedef enum CM_GAMMA_LUT_SEL_ENUM {
1109  RAMA                                     = 0x00000000,
1110  RAMB                                     = 0x00000001,
1111  } CM_GAMMA_LUT_SEL_ENUM;
1112  
1113  /*
1114   * CM_GAMUT_REMAP_MODE_ENUM enum
1115   */
1116  
1117  typedef enum CM_GAMUT_REMAP_MODE_ENUM {
1118  BYPASS_GAMUT                             = 0x00000000,
1119  GAMUT_COEF                               = 0x00000001,
1120  GAMUT_COEF_B                             = 0x00000002,
1121  } CM_GAMUT_REMAP_MODE_ENUM;
1122  
1123  /*
1124   * CM_LUT_2_CONFIG_ENUM enum
1125   */
1126  
1127  typedef enum CM_LUT_2_CONFIG_ENUM {
1128  LUT_2CFG_NO_MEMORY                       = 0x00000000,
1129  LUT_2CFG_MEMORY_A                        = 0x00000001,
1130  LUT_2CFG_MEMORY_B                        = 0x00000002,
1131  } CM_LUT_2_CONFIG_ENUM;
1132  
1133  /*
1134   * CM_LUT_2_MODE_ENUM enum
1135   */
1136  
1137  typedef enum CM_LUT_2_MODE_ENUM {
1138  LUT_2_MODE_BYPASS                        = 0x00000000,
1139  LUT_2_MODE_RAMA_LUT                      = 0x00000001,
1140  LUT_2_MODE_RAMB_LUT                      = 0x00000002,
1141  } CM_LUT_2_MODE_ENUM;
1142  
1143  /*
1144   * CM_LUT_4_CONFIG_ENUM enum
1145   */
1146  
1147  typedef enum CM_LUT_4_CONFIG_ENUM {
1148  LUT_4CFG_NO_MEMORY                       = 0x00000000,
1149  LUT_4CFG_ROM_A                           = 0x00000001,
1150  LUT_4CFG_ROM_B                           = 0x00000002,
1151  LUT_4CFG_MEMORY_A                        = 0x00000003,
1152  LUT_4CFG_MEMORY_B                        = 0x00000004,
1153  } CM_LUT_4_CONFIG_ENUM;
1154  
1155  /*
1156   * CM_LUT_4_MODE_ENUM enum
1157   */
1158  
1159  typedef enum CM_LUT_4_MODE_ENUM {
1160  LUT_4_MODE_BYPASS                        = 0x00000000,
1161  LUT_4_MODE_ROMA_LUT                      = 0x00000001,
1162  LUT_4_MODE_ROMB_LUT                      = 0x00000002,
1163  LUT_4_MODE_RAMA_LUT                      = 0x00000003,
1164  LUT_4_MODE_RAMB_LUT                      = 0x00000004,
1165  } CM_LUT_4_MODE_ENUM;
1166  
1167  /*
1168   * CM_LUT_CONFIG_MODE enum
1169   */
1170  
1171  typedef enum CM_LUT_CONFIG_MODE {
1172  DIFFERENT_RGB                            = 0x00000000,
1173  ALL_USE_R                                = 0x00000001,
1174  } CM_LUT_CONFIG_MODE;
1175  
1176  /*
1177   * CM_LUT_NUM_SEG enum
1178   */
1179  
1180  typedef enum CM_LUT_NUM_SEG {
1181  SEGMENTS_1                               = 0x00000000,
1182  SEGMENTS_2                               = 0x00000001,
1183  SEGMENTS_4                               = 0x00000002,
1184  SEGMENTS_8                               = 0x00000003,
1185  SEGMENTS_16                              = 0x00000004,
1186  SEGMENTS_32                              = 0x00000005,
1187  SEGMENTS_64                              = 0x00000006,
1188  SEGMENTS_128                             = 0x00000007,
1189  } CM_LUT_NUM_SEG;
1190  
1191  /*
1192   * CM_LUT_RAM_SEL enum
1193   */
1194  
1195  typedef enum CM_LUT_RAM_SEL {
1196  RAMA_ACCESS                              = 0x00000000,
1197  RAMB_ACCESS                              = 0x00000001,
1198  } CM_LUT_RAM_SEL;
1199  
1200  /*
1201   * CM_LUT_READ_COLOR_SEL enum
1202   */
1203  
1204  typedef enum CM_LUT_READ_COLOR_SEL {
1205  BLUE_LUT                                 = 0x00000000,
1206  GREEN_LUT                                = 0x00000001,
1207  RED_LUT                                  = 0x00000002,
1208  } CM_LUT_READ_COLOR_SEL;
1209  
1210  /*
1211   * CM_LUT_READ_DBG enum
1212   */
1213  
1214  typedef enum CM_LUT_READ_DBG {
1215  DISABLE_DEBUG                            = 0x00000000,
1216  ENABLE_DEBUG                             = 0x00000001,
1217  } CM_LUT_READ_DBG;
1218  
1219  /*
1220   * CM_PENDING enum
1221   */
1222  
1223  typedef enum CM_PENDING {
1224  CM_NOT_PENDING                           = 0x00000000,
1225  CM_YES_PENDING                           = 0x00000001,
1226  } CM_PENDING;
1227  
1228  /*
1229   * CM_POST_CSC_MODE_ENUM enum
1230   */
1231  
1232  typedef enum CM_POST_CSC_MODE_ENUM {
1233  BYPASS_POST_CSC                          = 0x00000000,
1234  COEF_POST_CSC                            = 0x00000001,
1235  COEF_POST_CSC_B                          = 0x00000002,
1236  } CM_POST_CSC_MODE_ENUM;
1237  
1238  /*
1239   * CM_WRITE_BASE_ONLY enum
1240   */
1241  
1242  typedef enum CM_WRITE_BASE_ONLY {
1243  WRITE_BOTH                               = 0x00000000,
1244  WRITE_BASE_ONLY                          = 0x00000001,
1245  } CM_WRITE_BASE_ONLY;
1246  
1247  /*******************************************************
1248   * DPP_TOP Enums
1249   *******************************************************/
1250  
1251  /*
1252   * CRC_CUR_SEL enum
1253   */
1254  
1255  typedef enum CRC_CUR_SEL {
1256  CRC_CUR_0                                = 0x00000000,
1257  CRC_CUR_1                                = 0x00000001,
1258  } CRC_CUR_SEL;
1259  
1260  /*
1261   * CRC_INTERLACE_SEL enum
1262   */
1263  
1264  typedef enum CRC_INTERLACE_SEL {
1265  CRC_INTERLACE_0                          = 0x00000000,
1266  CRC_INTERLACE_1                          = 0x00000001,
1267  CRC_INTERLACE_2                          = 0x00000002,
1268  CRC_INTERLACE_3                          = 0x00000003,
1269  } CRC_INTERLACE_SEL;
1270  
1271  /*
1272   * CRC_IN_CUR_SEL enum
1273   */
1274  
1275  typedef enum CRC_IN_CUR_SEL {
1276  CRC_IN_CUR_0                             = 0x00000000,
1277  CRC_IN_CUR_1                             = 0x00000001,
1278  CRC_IN_CUR_2                             = 0x00000002,
1279  CRC_IN_CUR_3                             = 0x00000003,
1280  } CRC_IN_CUR_SEL;
1281  
1282  /*
1283   * CRC_IN_PIX_SEL enum
1284   */
1285  
1286  typedef enum CRC_IN_PIX_SEL {
1287  CRC_IN_PIX_0                             = 0x00000000,
1288  CRC_IN_PIX_1                             = 0x00000001,
1289  CRC_IN_PIX_2                             = 0x00000002,
1290  CRC_IN_PIX_3                             = 0x00000003,
1291  CRC_IN_PIX_4                             = 0x00000004,
1292  CRC_IN_PIX_5                             = 0x00000005,
1293  CRC_IN_PIX_6                             = 0x00000006,
1294  CRC_IN_PIX_7                             = 0x00000007,
1295  } CRC_IN_PIX_SEL;
1296  
1297  /*
1298   * CRC_SRC_SEL enum
1299   */
1300  
1301  typedef enum CRC_SRC_SEL {
1302  CRC_SRC_0                                = 0x00000000,
1303  CRC_SRC_1                                = 0x00000001,
1304  CRC_SRC_2                                = 0x00000002,
1305  CRC_SRC_3                                = 0x00000003,
1306  } CRC_SRC_SEL;
1307  
1308  /*
1309   * CRC_STEREO_SEL enum
1310   */
1311  
1312  typedef enum CRC_STEREO_SEL {
1313  CRC_STEREO_0                             = 0x00000000,
1314  CRC_STEREO_1                             = 0x00000001,
1315  CRC_STEREO_2                             = 0x00000002,
1316  CRC_STEREO_3                             = 0x00000003,
1317  } CRC_STEREO_SEL;
1318  
1319  /*
1320   * TEST_CLK_SEL enum
1321   */
1322  
1323  typedef enum TEST_CLK_SEL {
1324  TEST_CLK_SEL_0                           = 0x00000000,
1325  TEST_CLK_SEL_1                           = 0x00000001,
1326  TEST_CLK_SEL_2                           = 0x00000002,
1327  TEST_CLK_SEL_3                           = 0x00000003,
1328  TEST_CLK_SEL_4                           = 0x00000004,
1329  TEST_CLK_SEL_5                           = 0x00000005,
1330  TEST_CLK_SEL_6                           = 0x00000006,
1331  TEST_CLK_SEL_7                           = 0x00000007,
1332  } TEST_CLK_SEL;
1333  
1334  /*******************************************************
1335   * DC_PERFMON Enums
1336   *******************************************************/
1337  
1338  /*
1339   * PERFCOUNTER_ACTIVE enum
1340   */
1341  
1342  typedef enum PERFCOUNTER_ACTIVE {
1343  PERFCOUNTER_IS_IDLE                      = 0x00000000,
1344  PERFCOUNTER_IS_ACTIVE                    = 0x00000001,
1345  } PERFCOUNTER_ACTIVE;
1346  
1347  /*
1348   * PERFCOUNTER_CNT0_STATE enum
1349   */
1350  
1351  typedef enum PERFCOUNTER_CNT0_STATE {
1352  PERFCOUNTER_CNT0_STATE_RESET             = 0x00000000,
1353  PERFCOUNTER_CNT0_STATE_START             = 0x00000001,
1354  PERFCOUNTER_CNT0_STATE_FREEZE            = 0x00000002,
1355  PERFCOUNTER_CNT0_STATE_HW                = 0x00000003,
1356  } PERFCOUNTER_CNT0_STATE;
1357  
1358  /*
1359   * PERFCOUNTER_CNT1_STATE enum
1360   */
1361  
1362  typedef enum PERFCOUNTER_CNT1_STATE {
1363  PERFCOUNTER_CNT1_STATE_RESET             = 0x00000000,
1364  PERFCOUNTER_CNT1_STATE_START             = 0x00000001,
1365  PERFCOUNTER_CNT1_STATE_FREEZE            = 0x00000002,
1366  PERFCOUNTER_CNT1_STATE_HW                = 0x00000003,
1367  } PERFCOUNTER_CNT1_STATE;
1368  
1369  /*
1370   * PERFCOUNTER_CNT2_STATE enum
1371   */
1372  
1373  typedef enum PERFCOUNTER_CNT2_STATE {
1374  PERFCOUNTER_CNT2_STATE_RESET             = 0x00000000,
1375  PERFCOUNTER_CNT2_STATE_START             = 0x00000001,
1376  PERFCOUNTER_CNT2_STATE_FREEZE            = 0x00000002,
1377  PERFCOUNTER_CNT2_STATE_HW                = 0x00000003,
1378  } PERFCOUNTER_CNT2_STATE;
1379  
1380  /*
1381   * PERFCOUNTER_CNT3_STATE enum
1382   */
1383  
1384  typedef enum PERFCOUNTER_CNT3_STATE {
1385  PERFCOUNTER_CNT3_STATE_RESET             = 0x00000000,
1386  PERFCOUNTER_CNT3_STATE_START             = 0x00000001,
1387  PERFCOUNTER_CNT3_STATE_FREEZE            = 0x00000002,
1388  PERFCOUNTER_CNT3_STATE_HW                = 0x00000003,
1389  } PERFCOUNTER_CNT3_STATE;
1390  
1391  /*
1392   * PERFCOUNTER_CNT4_STATE enum
1393   */
1394  
1395  typedef enum PERFCOUNTER_CNT4_STATE {
1396  PERFCOUNTER_CNT4_STATE_RESET             = 0x00000000,
1397  PERFCOUNTER_CNT4_STATE_START             = 0x00000001,
1398  PERFCOUNTER_CNT4_STATE_FREEZE            = 0x00000002,
1399  PERFCOUNTER_CNT4_STATE_HW                = 0x00000003,
1400  } PERFCOUNTER_CNT4_STATE;
1401  
1402  /*
1403   * PERFCOUNTER_CNT5_STATE enum
1404   */
1405  
1406  typedef enum PERFCOUNTER_CNT5_STATE {
1407  PERFCOUNTER_CNT5_STATE_RESET             = 0x00000000,
1408  PERFCOUNTER_CNT5_STATE_START             = 0x00000001,
1409  PERFCOUNTER_CNT5_STATE_FREEZE            = 0x00000002,
1410  PERFCOUNTER_CNT5_STATE_HW                = 0x00000003,
1411  } PERFCOUNTER_CNT5_STATE;
1412  
1413  /*
1414   * PERFCOUNTER_CNT6_STATE enum
1415   */
1416  
1417  typedef enum PERFCOUNTER_CNT6_STATE {
1418  PERFCOUNTER_CNT6_STATE_RESET             = 0x00000000,
1419  PERFCOUNTER_CNT6_STATE_START             = 0x00000001,
1420  PERFCOUNTER_CNT6_STATE_FREEZE            = 0x00000002,
1421  PERFCOUNTER_CNT6_STATE_HW                = 0x00000003,
1422  } PERFCOUNTER_CNT6_STATE;
1423  
1424  /*
1425   * PERFCOUNTER_CNT7_STATE enum
1426   */
1427  
1428  typedef enum PERFCOUNTER_CNT7_STATE {
1429  PERFCOUNTER_CNT7_STATE_RESET             = 0x00000000,
1430  PERFCOUNTER_CNT7_STATE_START             = 0x00000001,
1431  PERFCOUNTER_CNT7_STATE_FREEZE            = 0x00000002,
1432  PERFCOUNTER_CNT7_STATE_HW                = 0x00000003,
1433  } PERFCOUNTER_CNT7_STATE;
1434  
1435  /*
1436   * PERFCOUNTER_CNTL_SEL enum
1437   */
1438  
1439  typedef enum PERFCOUNTER_CNTL_SEL {
1440  PERFCOUNTER_CNTL_SEL_0                   = 0x00000000,
1441  PERFCOUNTER_CNTL_SEL_1                   = 0x00000001,
1442  PERFCOUNTER_CNTL_SEL_2                   = 0x00000002,
1443  PERFCOUNTER_CNTL_SEL_3                   = 0x00000003,
1444  PERFCOUNTER_CNTL_SEL_4                   = 0x00000004,
1445  PERFCOUNTER_CNTL_SEL_5                   = 0x00000005,
1446  PERFCOUNTER_CNTL_SEL_6                   = 0x00000006,
1447  PERFCOUNTER_CNTL_SEL_7                   = 0x00000007,
1448  } PERFCOUNTER_CNTL_SEL;
1449  
1450  /*
1451   * PERFCOUNTER_CNTOFF_START_DIS enum
1452   */
1453  
1454  typedef enum PERFCOUNTER_CNTOFF_START_DIS {
1455  PERFCOUNTER_CNTOFF_START_ENABLE          = 0x00000000,
1456  PERFCOUNTER_CNTOFF_START_DISABLE         = 0x00000001,
1457  } PERFCOUNTER_CNTOFF_START_DIS;
1458  
1459  /*
1460   * PERFCOUNTER_COUNTED_VALUE_TYPE enum
1461   */
1462  
1463  typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE {
1464  PERFCOUNTER_COUNTED_VALUE_TYPE_ACC       = 0x00000000,
1465  PERFCOUNTER_COUNTED_VALUE_TYPE_MAX       = 0x00000001,
1466  PERFCOUNTER_COUNTED_VALUE_TYPE_MIN       = 0x00000002,
1467  } PERFCOUNTER_COUNTED_VALUE_TYPE;
1468  
1469  /*
1470   * PERFCOUNTER_CVALUE_SEL enum
1471   */
1472  
1473  typedef enum PERFCOUNTER_CVALUE_SEL {
1474  PERFCOUNTER_CVALUE_SEL_47_0              = 0x00000000,
1475  PERFCOUNTER_CVALUE_SEL_15_0              = 0x00000001,
1476  PERFCOUNTER_CVALUE_SEL_31_16             = 0x00000002,
1477  PERFCOUNTER_CVALUE_SEL_47_32             = 0x00000003,
1478  PERFCOUNTER_CVALUE_SEL_11_0              = 0x00000004,
1479  PERFCOUNTER_CVALUE_SEL_23_12             = 0x00000005,
1480  PERFCOUNTER_CVALUE_SEL_35_24             = 0x00000006,
1481  PERFCOUNTER_CVALUE_SEL_47_36             = 0x00000007,
1482  } PERFCOUNTER_CVALUE_SEL;
1483  
1484  /*
1485   * PERFCOUNTER_HW_CNTL_SEL enum
1486   */
1487  
1488  typedef enum PERFCOUNTER_HW_CNTL_SEL {
1489  PERFCOUNTER_HW_CNTL_SEL_RUNEN            = 0x00000000,
1490  PERFCOUNTER_HW_CNTL_SEL_CNTOFF           = 0x00000001,
1491  } PERFCOUNTER_HW_CNTL_SEL;
1492  
1493  /*
1494   * PERFCOUNTER_HW_STOP1_SEL enum
1495   */
1496  
1497  typedef enum PERFCOUNTER_HW_STOP1_SEL {
1498  PERFCOUNTER_HW_STOP1_0                   = 0x00000000,
1499  PERFCOUNTER_HW_STOP1_1                   = 0x00000001,
1500  } PERFCOUNTER_HW_STOP1_SEL;
1501  
1502  /*
1503   * PERFCOUNTER_HW_STOP2_SEL enum
1504   */
1505  
1506  typedef enum PERFCOUNTER_HW_STOP2_SEL {
1507  PERFCOUNTER_HW_STOP2_0                   = 0x00000000,
1508  PERFCOUNTER_HW_STOP2_1                   = 0x00000001,
1509  } PERFCOUNTER_HW_STOP2_SEL;
1510  
1511  /*
1512   * PERFCOUNTER_INC_MODE enum
1513   */
1514  
1515  typedef enum PERFCOUNTER_INC_MODE {
1516  PERFCOUNTER_INC_MODE_MULTI_BIT           = 0x00000000,
1517  PERFCOUNTER_INC_MODE_BOTH_EDGE           = 0x00000001,
1518  PERFCOUNTER_INC_MODE_LSB                 = 0x00000002,
1519  PERFCOUNTER_INC_MODE_POS_EDGE            = 0x00000003,
1520  PERFCOUNTER_INC_MODE_NEG_EDGE            = 0x00000004,
1521  } PERFCOUNTER_INC_MODE;
1522  
1523  /*
1524   * PERFCOUNTER_INT_EN enum
1525   */
1526  
1527  typedef enum PERFCOUNTER_INT_EN {
1528  PERFCOUNTER_INT_DISABLE                  = 0x00000000,
1529  PERFCOUNTER_INT_ENABLE                   = 0x00000001,
1530  } PERFCOUNTER_INT_EN;
1531  
1532  /*
1533   * PERFCOUNTER_INT_TYPE enum
1534   */
1535  
1536  typedef enum PERFCOUNTER_INT_TYPE {
1537  PERFCOUNTER_INT_TYPE_LEVEL               = 0x00000000,
1538  PERFCOUNTER_INT_TYPE_PULSE               = 0x00000001,
1539  } PERFCOUNTER_INT_TYPE;
1540  
1541  /*
1542   * PERFCOUNTER_OFF_MASK enum
1543   */
1544  
1545  typedef enum PERFCOUNTER_OFF_MASK {
1546  PERFCOUNTER_OFF_MASK_DISABLE             = 0x00000000,
1547  PERFCOUNTER_OFF_MASK_ENABLE              = 0x00000001,
1548  } PERFCOUNTER_OFF_MASK;
1549  
1550  /*
1551   * PERFCOUNTER_RESTART_EN enum
1552   */
1553  
1554  typedef enum PERFCOUNTER_RESTART_EN {
1555  PERFCOUNTER_RESTART_DISABLE              = 0x00000000,
1556  PERFCOUNTER_RESTART_ENABLE               = 0x00000001,
1557  } PERFCOUNTER_RESTART_EN;
1558  
1559  /*
1560   * PERFCOUNTER_RUNEN_MODE enum
1561   */
1562  
1563  typedef enum PERFCOUNTER_RUNEN_MODE {
1564  PERFCOUNTER_RUNEN_MODE_LEVEL             = 0x00000000,
1565  PERFCOUNTER_RUNEN_MODE_EDGE              = 0x00000001,
1566  } PERFCOUNTER_RUNEN_MODE;
1567  
1568  /*
1569   * PERFCOUNTER_STATE_SEL0 enum
1570   */
1571  
1572  typedef enum PERFCOUNTER_STATE_SEL0 {
1573  PERFCOUNTER_STATE_SEL0_GLOBAL            = 0x00000000,
1574  PERFCOUNTER_STATE_SEL0_LOCAL             = 0x00000001,
1575  } PERFCOUNTER_STATE_SEL0;
1576  
1577  /*
1578   * PERFCOUNTER_STATE_SEL1 enum
1579   */
1580  
1581  typedef enum PERFCOUNTER_STATE_SEL1 {
1582  PERFCOUNTER_STATE_SEL1_GLOBAL            = 0x00000000,
1583  PERFCOUNTER_STATE_SEL1_LOCAL             = 0x00000001,
1584  } PERFCOUNTER_STATE_SEL1;
1585  
1586  /*
1587   * PERFCOUNTER_STATE_SEL2 enum
1588   */
1589  
1590  typedef enum PERFCOUNTER_STATE_SEL2 {
1591  PERFCOUNTER_STATE_SEL2_GLOBAL            = 0x00000000,
1592  PERFCOUNTER_STATE_SEL2_LOCAL             = 0x00000001,
1593  } PERFCOUNTER_STATE_SEL2;
1594  
1595  /*
1596   * PERFCOUNTER_STATE_SEL3 enum
1597   */
1598  
1599  typedef enum PERFCOUNTER_STATE_SEL3 {
1600  PERFCOUNTER_STATE_SEL3_GLOBAL            = 0x00000000,
1601  PERFCOUNTER_STATE_SEL3_LOCAL             = 0x00000001,
1602  } PERFCOUNTER_STATE_SEL3;
1603  
1604  /*
1605   * PERFCOUNTER_STATE_SEL4 enum
1606   */
1607  
1608  typedef enum PERFCOUNTER_STATE_SEL4 {
1609  PERFCOUNTER_STATE_SEL4_GLOBAL            = 0x00000000,
1610  PERFCOUNTER_STATE_SEL4_LOCAL             = 0x00000001,
1611  } PERFCOUNTER_STATE_SEL4;
1612  
1613  /*
1614   * PERFCOUNTER_STATE_SEL5 enum
1615   */
1616  
1617  typedef enum PERFCOUNTER_STATE_SEL5 {
1618  PERFCOUNTER_STATE_SEL5_GLOBAL            = 0x00000000,
1619  PERFCOUNTER_STATE_SEL5_LOCAL             = 0x00000001,
1620  } PERFCOUNTER_STATE_SEL5;
1621  
1622  /*
1623   * PERFCOUNTER_STATE_SEL6 enum
1624   */
1625  
1626  typedef enum PERFCOUNTER_STATE_SEL6 {
1627  PERFCOUNTER_STATE_SEL6_GLOBAL            = 0x00000000,
1628  PERFCOUNTER_STATE_SEL6_LOCAL             = 0x00000001,
1629  } PERFCOUNTER_STATE_SEL6;
1630  
1631  /*
1632   * PERFCOUNTER_STATE_SEL7 enum
1633   */
1634  
1635  typedef enum PERFCOUNTER_STATE_SEL7 {
1636  PERFCOUNTER_STATE_SEL7_GLOBAL            = 0x00000000,
1637  PERFCOUNTER_STATE_SEL7_LOCAL             = 0x00000001,
1638  } PERFCOUNTER_STATE_SEL7;
1639  
1640  /*
1641   * PERFMON_CNTOFF_AND_OR enum
1642   */
1643  
1644  typedef enum PERFMON_CNTOFF_AND_OR {
1645  PERFMON_CNTOFF_OR                        = 0x00000000,
1646  PERFMON_CNTOFF_AND                       = 0x00000001,
1647  } PERFMON_CNTOFF_AND_OR;
1648  
1649  /*
1650   * PERFMON_CNTOFF_INT_EN enum
1651   */
1652  
1653  typedef enum PERFMON_CNTOFF_INT_EN {
1654  PERFMON_CNTOFF_INT_DISABLE               = 0x00000000,
1655  PERFMON_CNTOFF_INT_ENABLE                = 0x00000001,
1656  } PERFMON_CNTOFF_INT_EN;
1657  
1658  /*
1659   * PERFMON_CNTOFF_INT_TYPE enum
1660   */
1661  
1662  typedef enum PERFMON_CNTOFF_INT_TYPE {
1663  PERFMON_CNTOFF_INT_TYPE_LEVEL            = 0x00000000,
1664  PERFMON_CNTOFF_INT_TYPE_PULSE            = 0x00000001,
1665  } PERFMON_CNTOFF_INT_TYPE;
1666  
1667  /*
1668   * PERFMON_STATE enum
1669   */
1670  
1671  typedef enum PERFMON_STATE {
1672  PERFMON_STATE_RESET                      = 0x00000000,
1673  PERFMON_STATE_START                      = 0x00000001,
1674  PERFMON_STATE_FREEZE                     = 0x00000002,
1675  PERFMON_STATE_HW                         = 0x00000003,
1676  } PERFMON_STATE;
1677  
1678  /*******************************************************
1679   * HUBP Enums
1680   *******************************************************/
1681  
1682  /*
1683   * BIGK_FRAGMENT_SIZE enum
1684   */
1685  
1686  typedef enum BIGK_FRAGMENT_SIZE {
1687  VM_PG_SIZE_4KB                           = 0x00000000,
1688  VM_PG_SIZE_8KB                           = 0x00000001,
1689  VM_PG_SIZE_16KB                          = 0x00000002,
1690  VM_PG_SIZE_32KB                          = 0x00000003,
1691  VM_PG_SIZE_64KB                          = 0x00000004,
1692  VM_PG_SIZE_128KB                         = 0x00000005,
1693  VM_PG_SIZE_256KB                         = 0x00000006,
1694  VM_PG_SIZE_512KB                         = 0x00000007,
1695  VM_PG_SIZE_1024KB                        = 0x00000008,
1696  VM_PG_SIZE_2048KB                        = 0x00000009,
1697  } BIGK_FRAGMENT_SIZE;
1698  
1699  /*
1700   * CHUNK_SIZE enum
1701   */
1702  
1703  typedef enum CHUNK_SIZE {
1704  CHUNK_SIZE_1KB                           = 0x00000000,
1705  CHUNK_SIZE_2KB                           = 0x00000001,
1706  CHUNK_SIZE_4KB                           = 0x00000002,
1707  CHUNK_SIZE_8KB                           = 0x00000003,
1708  CHUNK_SIZE_16KB                          = 0x00000004,
1709  CHUNK_SIZE_32KB                          = 0x00000005,
1710  CHUNK_SIZE_64KB                          = 0x00000006,
1711  } CHUNK_SIZE;
1712  
1713  /*
1714   * COMPAT_LEVEL enum
1715   */
1716  
1717  typedef enum COMPAT_LEVEL {
1718  ADDR_GEN_ZERO                            = 0x00000000,
1719  ADDR_GEN_ONE                             = 0x00000001,
1720  ADDR_GEN_TWO                             = 0x00000002,
1721  ADDR_RESERVED                            = 0x00000003,
1722  } COMPAT_LEVEL;
1723  
1724  /*
1725   * DPTE_GROUP_SIZE enum
1726   */
1727  
1728  typedef enum DPTE_GROUP_SIZE {
1729  DPTE_GROUP_SIZE_64B                      = 0x00000000,
1730  DPTE_GROUP_SIZE_128B                     = 0x00000001,
1731  DPTE_GROUP_SIZE_256B                     = 0x00000002,
1732  DPTE_GROUP_SIZE_512B                     = 0x00000003,
1733  DPTE_GROUP_SIZE_1024B                    = 0x00000004,
1734  DPTE_GROUP_SIZE_2048B                    = 0x00000005,
1735  } DPTE_GROUP_SIZE;
1736  
1737  /*
1738   * FORCE_ONE_ROW_FOR_FRAME enum
1739   */
1740  
1741  typedef enum FORCE_ONE_ROW_FOR_FRAME {
1742  FORCE_ONE_ROW_FOR_FRAME_0                = 0x00000000,
1743  FORCE_ONE_ROW_FOR_FRAME_1                = 0x00000001,
1744  } FORCE_ONE_ROW_FOR_FRAME;
1745  
1746  /*
1747   * HUBP_BLANK_EN enum
1748   */
1749  
1750  typedef enum HUBP_BLANK_EN {
1751  HUBP_BLANK_SW_DEASSERT                   = 0x00000000,
1752  HUBP_BLANK_SW_ASSERT                     = 0x00000001,
1753  } HUBP_BLANK_EN;
1754  
1755  /*
1756   * HUBP_IN_BLANK enum
1757   */
1758  
1759  typedef enum HUBP_IN_BLANK {
1760  HUBP_IN_ACTIVE                           = 0x00000000,
1761  HUBP_IN_VBLANK                           = 0x00000001,
1762  } HUBP_IN_BLANK;
1763  
1764  /*
1765   * HUBP_MEASURE_WIN_MODE_DCFCLK enum
1766   */
1767  
1768  typedef enum HUBP_MEASURE_WIN_MODE_DCFCLK {
1769  HUBP_MEASURE_WIN_MODE_DCFCLK_0           = 0x00000000,
1770  HUBP_MEASURE_WIN_MODE_DCFCLK_1           = 0x00000001,
1771  HUBP_MEASURE_WIN_MODE_DCFCLK_2           = 0x00000002,
1772  HUBP_MEASURE_WIN_MODE_DCFCLK_3           = 0x00000003,
1773  } HUBP_MEASURE_WIN_MODE_DCFCLK;
1774  
1775  /*
1776   * HUBP_NO_OUTSTANDING_REQ enum
1777   */
1778  
1779  typedef enum HUBP_NO_OUTSTANDING_REQ {
1780  OUTSTANDING_REQ                          = 0x00000000,
1781  NO_OUTSTANDING_REQ                       = 0x00000001,
1782  } HUBP_NO_OUTSTANDING_REQ;
1783  
1784  /*
1785   * HUBP_SOFT_RESET enum
1786   */
1787  
1788  typedef enum HUBP_SOFT_RESET {
1789  HUBP_SOFT_RESET_ON                       = 0x00000000,
1790  HUBP_SOFT_RESET_OFF                      = 0x00000001,
1791  } HUBP_SOFT_RESET;
1792  
1793  /*
1794   * HUBP_TTU_DISABLE enum
1795   */
1796  
1797  typedef enum HUBP_TTU_DISABLE {
1798  HUBP_TTU_ENABLED                         = 0x00000000,
1799  HUBP_TTU_DISABLED                        = 0x00000001,
1800  } HUBP_TTU_DISABLE;
1801  
1802  /*
1803   * HUBP_VREADY_AT_OR_AFTER_VSYNC enum
1804   */
1805  
1806  typedef enum HUBP_VREADY_AT_OR_AFTER_VSYNC {
1807  VREADY_BEFORE_VSYNC                      = 0x00000000,
1808  VREADY_AT_OR_AFTER_VSYNC                 = 0x00000001,
1809  } HUBP_VREADY_AT_OR_AFTER_VSYNC;
1810  
1811  /*
1812   * HUBP_VTG_SEL enum
1813   */
1814  
1815  typedef enum HUBP_VTG_SEL {
1816  VTG_SEL_0                                = 0x00000000,
1817  VTG_SEL_1                                = 0x00000001,
1818  VTG_SEL_2                                = 0x00000002,
1819  VTG_SEL_3                                = 0x00000003,
1820  VTG_SEL_4                                = 0x00000004,
1821  VTG_SEL_5                                = 0x00000005,
1822  } HUBP_VTG_SEL;
1823  
1824  /*
1825   * H_MIRROR_EN enum
1826   */
1827  
1828  typedef enum H_MIRROR_EN {
1829  HW_MIRRORING_DISABLE                     = 0x00000000,
1830  HW_MIRRORING_ENABLE                      = 0x00000001,
1831  } H_MIRROR_EN;
1832  
1833  /*
1834   * LEGACY_PIPE_INTERLEAVE enum
1835   */
1836  
1837  typedef enum LEGACY_PIPE_INTERLEAVE {
1838  LEGACY_PIPE_INTERLEAVE_256B              = 0x00000000,
1839  LEGACY_PIPE_INTERLEAVE_512B              = 0x00000001,
1840  } LEGACY_PIPE_INTERLEAVE;
1841  
1842  /*
1843   * META_CHUNK_SIZE enum
1844   */
1845  
1846  typedef enum META_CHUNK_SIZE {
1847  META_CHUNK_SIZE_1KB                      = 0x00000000,
1848  META_CHUNK_SIZE_2KB                      = 0x00000001,
1849  META_CHUNK_SIZE_4KB                      = 0x00000002,
1850  META_CHUNK_SIZE_8KB                      = 0x00000003,
1851  } META_CHUNK_SIZE;
1852  
1853  /*
1854   * META_LINEAR enum
1855   */
1856  
1857  typedef enum META_LINEAR {
1858  META_SURF_TILED                          = 0x00000000,
1859  META_SURF_LINEAR                         = 0x00000001,
1860  } META_LINEAR;
1861  
1862  /*
1863   * MIN_CHUNK_SIZE enum
1864   */
1865  
1866  typedef enum MIN_CHUNK_SIZE {
1867  NO_MIN_CHUNK_SIZE                        = 0x00000000,
1868  MIN_CHUNK_SIZE_256B                      = 0x00000001,
1869  MIN_CHUNK_SIZE_512B                      = 0x00000002,
1870  MIN_CHUNK_SIZE_1024B                     = 0x00000003,
1871  } MIN_CHUNK_SIZE;
1872  
1873  /*
1874   * MIN_META_CHUNK_SIZE enum
1875   */
1876  
1877  typedef enum MIN_META_CHUNK_SIZE {
1878  NO_MIN_META_CHUNK_SIZE                   = 0x00000000,
1879  MIN_META_CHUNK_SIZE_64B                  = 0x00000001,
1880  MIN_META_CHUNK_SIZE_128B                 = 0x00000002,
1881  MIN_META_CHUNK_SIZE_256B                 = 0x00000003,
1882  } MIN_META_CHUNK_SIZE;
1883  
1884  /*
1885   * PIPE_ALIGNED enum
1886   */
1887  
1888  typedef enum PIPE_ALIGNED {
1889  PIPE_UNALIGNED_SURF                      = 0x00000000,
1890  PIPE_ALIGNED_SURF                        = 0x00000001,
1891  } PIPE_ALIGNED;
1892  
1893  /*
1894   * PTE_BUFFER_MODE enum
1895   */
1896  
1897  typedef enum PTE_BUFFER_MODE {
1898  PTE_BUFFER_MODE_0                        = 0x00000000,
1899  PTE_BUFFER_MODE_1                        = 0x00000001,
1900  } PTE_BUFFER_MODE;
1901  
1902  /*
1903   * PTE_ROW_HEIGHT_LINEAR enum
1904   */
1905  
1906  typedef enum PTE_ROW_HEIGHT_LINEAR {
1907  PTE_ROW_HEIGHT_LINEAR_8L                 = 0x00000000,
1908  PTE_ROW_HEIGHT_LINEAR_16L                = 0x00000001,
1909  PTE_ROW_HEIGHT_LINEAR_32L                = 0x00000002,
1910  PTE_ROW_HEIGHT_LINEAR_64L                = 0x00000003,
1911  PTE_ROW_HEIGHT_LINEAR_128L               = 0x00000004,
1912  PTE_ROW_HEIGHT_LINEAR_256L               = 0x00000005,
1913  PTE_ROW_HEIGHT_LINEAR_512L               = 0x00000006,
1914  PTE_ROW_HEIGHT_LINEAR_1024L              = 0x00000007,
1915  } PTE_ROW_HEIGHT_LINEAR;
1916  
1917  /*
1918   * ROTATION_ANGLE enum
1919   */
1920  
1921  typedef enum ROTATION_ANGLE {
1922  ROTATE_0_DEGREES                         = 0x00000000,
1923  ROTATE_90_DEGREES                        = 0x00000001,
1924  ROTATE_180_DEGREES                       = 0x00000002,
1925  ROTATE_270_DEGREES                       = 0x00000003,
1926  } ROTATION_ANGLE;
1927  
1928  /*
1929   * SWATH_HEIGHT enum
1930   */
1931  
1932  typedef enum SWATH_HEIGHT {
1933  SWATH_HEIGHT_1L                          = 0x00000000,
1934  SWATH_HEIGHT_2L                          = 0x00000001,
1935  SWATH_HEIGHT_4L                          = 0x00000002,
1936  SWATH_HEIGHT_8L                          = 0x00000003,
1937  SWATH_HEIGHT_16L                         = 0x00000004,
1938  } SWATH_HEIGHT;
1939  
1940  /*
1941   * USE_MALL_FOR_CURSOR enum
1942   */
1943  
1944  typedef enum USE_MALL_FOR_CURSOR {
1945  USE_MALL_FOR_CURSOR_0                    = 0x00000000,
1946  USE_MALL_FOR_CURSOR_1                    = 0x00000001,
1947  } USE_MALL_FOR_CURSOR;
1948  
1949  /*
1950   * USE_MALL_FOR_PSTATE_CHANGE enum
1951   */
1952  
1953  typedef enum USE_MALL_FOR_PSTATE_CHANGE {
1954  USE_MALL_FOR_PSTATE_CHANGE_0             = 0x00000000,
1955  USE_MALL_FOR_PSTATE_CHANGE_1             = 0x00000001,
1956  } USE_MALL_FOR_PSTATE_CHANGE;
1957  
1958  /*
1959   * USE_MALL_FOR_STATIC_SCREEN enum
1960   */
1961  
1962  typedef enum USE_MALL_FOR_STATIC_SCREEN {
1963  USE_MALL_FOR_STATIC_SCREEN_0             = 0x00000000,
1964  USE_MALL_FOR_STATIC_SCREEN_1             = 0x00000001,
1965  } USE_MALL_FOR_STATIC_SCREEN;
1966  
1967  /*
1968   * VMPG_SIZE enum
1969   */
1970  
1971  typedef enum VMPG_SIZE {
1972  VMPG_SIZE_4KB                            = 0x00000000,
1973  VMPG_SIZE_64KB                           = 0x00000001,
1974  } VMPG_SIZE;
1975  
1976  /*
1977   * VM_GROUP_SIZE enum
1978   */
1979  
1980  typedef enum VM_GROUP_SIZE {
1981  VM_GROUP_SIZE_64B                        = 0x00000000,
1982  VM_GROUP_SIZE_128B                       = 0x00000001,
1983  VM_GROUP_SIZE_256B                       = 0x00000002,
1984  VM_GROUP_SIZE_512B                       = 0x00000003,
1985  VM_GROUP_SIZE_1024B                      = 0x00000004,
1986  VM_GROUP_SIZE_2048B                      = 0x00000005,
1987  } VM_GROUP_SIZE;
1988  
1989  /*******************************************************
1990   * HUBPREQ Enums
1991   *******************************************************/
1992  
1993  /*
1994   * DFQ_MIN_FREE_ENTRIES enum
1995   */
1996  
1997  typedef enum DFQ_MIN_FREE_ENTRIES {
1998  DFQ_MIN_FREE_ENTRIES_0                   = 0x00000000,
1999  DFQ_MIN_FREE_ENTRIES_1                   = 0x00000001,
2000  DFQ_MIN_FREE_ENTRIES_2                   = 0x00000002,
2001  DFQ_MIN_FREE_ENTRIES_3                   = 0x00000003,
2002  DFQ_MIN_FREE_ENTRIES_4                   = 0x00000004,
2003  DFQ_MIN_FREE_ENTRIES_5                   = 0x00000005,
2004  DFQ_MIN_FREE_ENTRIES_6                   = 0x00000006,
2005  DFQ_MIN_FREE_ENTRIES_7                   = 0x00000007,
2006  } DFQ_MIN_FREE_ENTRIES;
2007  
2008  /*
2009   * DFQ_NUM_ENTRIES enum
2010   */
2011  
2012  typedef enum DFQ_NUM_ENTRIES {
2013  DFQ_NUM_ENTRIES_0                        = 0x00000000,
2014  DFQ_NUM_ENTRIES_1                        = 0x00000001,
2015  DFQ_NUM_ENTRIES_2                        = 0x00000002,
2016  DFQ_NUM_ENTRIES_3                        = 0x00000003,
2017  DFQ_NUM_ENTRIES_4                        = 0x00000004,
2018  DFQ_NUM_ENTRIES_5                        = 0x00000005,
2019  DFQ_NUM_ENTRIES_6                        = 0x00000006,
2020  DFQ_NUM_ENTRIES_7                        = 0x00000007,
2021  DFQ_NUM_ENTRIES_8                        = 0x00000008,
2022  } DFQ_NUM_ENTRIES;
2023  
2024  /*
2025   * DFQ_SIZE enum
2026   */
2027  
2028  typedef enum DFQ_SIZE {
2029  DFQ_SIZE_0                               = 0x00000000,
2030  DFQ_SIZE_1                               = 0x00000001,
2031  DFQ_SIZE_2                               = 0x00000002,
2032  DFQ_SIZE_3                               = 0x00000003,
2033  DFQ_SIZE_4                               = 0x00000004,
2034  DFQ_SIZE_5                               = 0x00000005,
2035  DFQ_SIZE_6                               = 0x00000006,
2036  DFQ_SIZE_7                               = 0x00000007,
2037  } DFQ_SIZE;
2038  
2039  /*
2040   * DMDATA_VM_DONE enum
2041   */
2042  
2043  typedef enum DMDATA_VM_DONE {
2044  DMDATA_VM_IS_NOT_DONE                    = 0x00000000,
2045  DMDATA_VM_IS_DONE                        = 0x00000001,
2046  } DMDATA_VM_DONE;
2047  
2048  /*
2049   * EXPANSION_MODE enum
2050   */
2051  
2052  typedef enum EXPANSION_MODE {
2053  EXPANSION_MODE_ZERO                      = 0x00000000,
2054  EXPANSION_MODE_CONSERVATIVE              = 0x00000001,
2055  EXPANSION_MODE_OPTIMAL                   = 0x00000002,
2056  } EXPANSION_MODE;
2057  
2058  /*
2059   * FLIP_RATE enum
2060   */
2061  
2062  typedef enum FLIP_RATE {
2063  FLIP_RATE_0                              = 0x00000000,
2064  FLIP_RATE_1                              = 0x00000001,
2065  FLIP_RATE_2                              = 0x00000002,
2066  FLIP_RATE_3                              = 0x00000003,
2067  FLIP_RATE_4                              = 0x00000004,
2068  FLIP_RATE_5                              = 0x00000005,
2069  FLIP_RATE_6                              = 0x00000006,
2070  FLIP_RATE_7                              = 0x00000007,
2071  } FLIP_RATE;
2072  
2073  /*
2074   * INT_MASK enum
2075   */
2076  
2077  typedef enum INT_MASK {
2078  INT_DISABLED                             = 0x00000000,
2079  INT_ENABLED                              = 0x00000001,
2080  } INT_MASK;
2081  
2082  /*
2083   * PIPE_IN_FLUSH_URGENT enum
2084   */
2085  
2086  typedef enum PIPE_IN_FLUSH_URGENT {
2087  PIPE_IN_FLUSH_URGENT_ENABLE              = 0x00000000,
2088  PIPE_IN_FLUSH_URGENT_DISABLE             = 0x00000001,
2089  } PIPE_IN_FLUSH_URGENT;
2090  
2091  /*
2092   * PRQ_MRQ_FLUSH_URGENT enum
2093   */
2094  
2095  typedef enum PRQ_MRQ_FLUSH_URGENT {
2096  PRQ_MRQ_FLUSH_URGENT_ENABLE              = 0x00000000,
2097  PRQ_MRQ_FLUSH_URGENT_DISABLE             = 0x00000001,
2098  } PRQ_MRQ_FLUSH_URGENT;
2099  
2100  /*
2101   * ROW_TTU_MODE enum
2102   */
2103  
2104  typedef enum ROW_TTU_MODE {
2105  END_OF_ROW_MODE                          = 0x00000000,
2106  WATERMARK_MODE                           = 0x00000001,
2107  } ROW_TTU_MODE;
2108  
2109  /*
2110   * SURFACE_DCC enum
2111   */
2112  
2113  typedef enum SURFACE_DCC {
2114  SURFACE_IS_NOT_DCC                       = 0x00000000,
2115  SURFACE_IS_DCC                           = 0x00000001,
2116  } SURFACE_DCC;
2117  
2118  /*
2119   * SURFACE_DCC_IND_128B enum
2120   */
2121  
2122  typedef enum SURFACE_DCC_IND_128B {
2123  SURFACE_DCC_IS_NOT_IND_128B              = 0x00000000,
2124  SURFACE_DCC_IS_IND_128B                  = 0x00000001,
2125  } SURFACE_DCC_IND_128B;
2126  
2127  /*
2128   * SURFACE_DCC_IND_64B enum
2129   */
2130  
2131  typedef enum SURFACE_DCC_IND_64B {
2132  SURFACE_DCC_IS_NOT_IND_64B               = 0x00000000,
2133  SURFACE_DCC_IS_IND_64B                   = 0x00000001,
2134  } SURFACE_DCC_IND_64B;
2135  
2136  /*
2137   * SURFACE_DCC_IND_BLK enum
2138   */
2139  
2140  typedef enum SURFACE_DCC_IND_BLK {
2141  SURFACE_DCC_BLOCK_IS_UNCONSTRAINED       = 0x00000000,
2142  SURFACE_DCC_BLOCK_IS_IND_64B             = 0x00000001,
2143  SURFACE_DCC_BLOCK_IS_IND_128B            = 0x00000002,
2144  SURFACE_DCC_BLOCK_IS_IND_64B_NO_128BCL   = 0x00000003,
2145  } SURFACE_DCC_IND_BLK;
2146  
2147  /*
2148   * SURFACE_FLIP_AWAY_INT_TYPE enum
2149   */
2150  
2151  typedef enum SURFACE_FLIP_AWAY_INT_TYPE {
2152  SURFACE_FLIP_AWAY_INT_LEVEL              = 0x00000000,
2153  SURFACE_FLIP_AWAY_INT_PULSE              = 0x00000001,
2154  } SURFACE_FLIP_AWAY_INT_TYPE;
2155  
2156  /*
2157   * SURFACE_FLIP_EXEC_DEBUG_MODE enum
2158   */
2159  
2160  typedef enum SURFACE_FLIP_EXEC_DEBUG_MODE {
2161  SURFACE_FLIP_EXEC_NORMAL_MODE            = 0x00000000,
2162  SURFACE_FLIP_EXEC_DEBUG_MODE_ENABLE      = 0x00000001,
2163  } SURFACE_FLIP_EXEC_DEBUG_MODE;
2164  
2165  /*
2166   * SURFACE_FLIP_INT_TYPE enum
2167   */
2168  
2169  typedef enum SURFACE_FLIP_INT_TYPE {
2170  SURFACE_FLIP_INT_LEVEL                   = 0x00000000,
2171  SURFACE_FLIP_INT_PULSE                   = 0x00000001,
2172  } SURFACE_FLIP_INT_TYPE;
2173  
2174  /*
2175   * SURFACE_FLIP_IN_STEREOSYNC enum
2176   */
2177  
2178  typedef enum SURFACE_FLIP_IN_STEREOSYNC {
2179  SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE      = 0x00000000,
2180  SURFACE_FLIP_IN_STEREOSYNC_MODE          = 0x00000001,
2181  } SURFACE_FLIP_IN_STEREOSYNC;
2182  
2183  /*
2184   * SURFACE_FLIP_MODE_FOR_STEREOSYNC enum
2185   */
2186  
2187  typedef enum SURFACE_FLIP_MODE_FOR_STEREOSYNC {
2188  FLIP_ANY_FRAME                           = 0x00000000,
2189  FLIP_LEFT_EYE                            = 0x00000001,
2190  FLIP_RIGHT_EYE                           = 0x00000002,
2191  SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED = 0x00000003,
2192  } SURFACE_FLIP_MODE_FOR_STEREOSYNC;
2193  
2194  /*
2195   * SURFACE_FLIP_STEREO_SELECT_DISABLE enum
2196   */
2197  
2198  typedef enum SURFACE_FLIP_STEREO_SELECT_DISABLE {
2199  SURFACE_FLIP_STEREO_SELECT_ENABLED       = 0x00000000,
2200  SURFACE_FLIP_STEREO_SELECT_DISABLED      = 0x00000001,
2201  } SURFACE_FLIP_STEREO_SELECT_DISABLE;
2202  
2203  /*
2204   * SURFACE_FLIP_STEREO_SELECT_POLARITY enum
2205   */
2206  
2207  typedef enum SURFACE_FLIP_STEREO_SELECT_POLARITY {
2208  SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT = 0x00000000,
2209  SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT = 0x00000001,
2210  } SURFACE_FLIP_STEREO_SELECT_POLARITY;
2211  
2212  /*
2213   * SURFACE_FLIP_TYPE enum
2214   */
2215  
2216  typedef enum SURFACE_FLIP_TYPE {
2217  SURFACE_V_FLIP                           = 0x00000000,
2218  SURFACE_I_FLIP                           = 0x00000001,
2219  } SURFACE_FLIP_TYPE;
2220  
2221  /*
2222   * SURFACE_FLIP_VUPDATE_SKIP_NUM enum
2223   */
2224  
2225  typedef enum SURFACE_FLIP_VUPDATE_SKIP_NUM {
2226  SURFACE_FLIP_VUPDATE_SKIP_NUM_0          = 0x00000000,
2227  SURFACE_FLIP_VUPDATE_SKIP_NUM_1          = 0x00000001,
2228  SURFACE_FLIP_VUPDATE_SKIP_NUM_2          = 0x00000002,
2229  SURFACE_FLIP_VUPDATE_SKIP_NUM_3          = 0x00000003,
2230  SURFACE_FLIP_VUPDATE_SKIP_NUM_4          = 0x00000004,
2231  SURFACE_FLIP_VUPDATE_SKIP_NUM_5          = 0x00000005,
2232  SURFACE_FLIP_VUPDATE_SKIP_NUM_6          = 0x00000006,
2233  SURFACE_FLIP_VUPDATE_SKIP_NUM_7          = 0x00000007,
2234  SURFACE_FLIP_VUPDATE_SKIP_NUM_8          = 0x00000008,
2235  SURFACE_FLIP_VUPDATE_SKIP_NUM_9          = 0x00000009,
2236  SURFACE_FLIP_VUPDATE_SKIP_NUM_10         = 0x0000000a,
2237  SURFACE_FLIP_VUPDATE_SKIP_NUM_11         = 0x0000000b,
2238  SURFACE_FLIP_VUPDATE_SKIP_NUM_12         = 0x0000000c,
2239  SURFACE_FLIP_VUPDATE_SKIP_NUM_13         = 0x0000000d,
2240  SURFACE_FLIP_VUPDATE_SKIP_NUM_14         = 0x0000000e,
2241  SURFACE_FLIP_VUPDATE_SKIP_NUM_15         = 0x0000000f,
2242  } SURFACE_FLIP_VUPDATE_SKIP_NUM;
2243  
2244  /*
2245   * SURFACE_INUSE_RAED_NO_LATCH enum
2246   */
2247  
2248  typedef enum SURFACE_INUSE_RAED_NO_LATCH {
2249  SURFACE_INUSE_IS_LATCHED                 = 0x00000000,
2250  SURFACE_INUSE_IS_NOT_LATCHED             = 0x00000001,
2251  } SURFACE_INUSE_RAED_NO_LATCH;
2252  
2253  /*
2254   * SURFACE_TMZ enum
2255   */
2256  
2257  typedef enum SURFACE_TMZ {
2258  SURFACE_IS_NOT_TMZ                       = 0x00000000,
2259  SURFACE_IS_TMZ                           = 0x00000001,
2260  } SURFACE_TMZ;
2261  
2262  /*
2263   * SURFACE_UPDATE_LOCK enum
2264   */
2265  
2266  typedef enum SURFACE_UPDATE_LOCK {
2267  SURFACE_UPDATE_IS_UNLOCKED               = 0x00000000,
2268  SURFACE_UPDATE_IS_LOCKED                 = 0x00000001,
2269  } SURFACE_UPDATE_LOCK;
2270  
2271  /*******************************************************
2272   * HUBPRET Enums
2273   *******************************************************/
2274  
2275  /*
2276   * CROSSBAR_FOR_ALPHA enum
2277   */
2278  
2279  typedef enum CROSSBAR_FOR_ALPHA {
2280  ALPHA_DATA_ONTO_ALPHA_PORT               = 0x00000000,
2281  Y_G_DATA_ONTO_ALPHA_PORT                 = 0x00000001,
2282  CB_B_DATA_ONTO_ALPHA_PORT                = 0x00000002,
2283  CR_R_DATA_ONTO_ALPHA_PORT                = 0x00000003,
2284  } CROSSBAR_FOR_ALPHA;
2285  
2286  /*
2287   * CROSSBAR_FOR_CB_B enum
2288   */
2289  
2290  typedef enum CROSSBAR_FOR_CB_B {
2291  ALPHA_DATA_ONTO_CB_B_PORT                = 0x00000000,
2292  Y_G_DATA_ONTO_CB_B_PORT                  = 0x00000001,
2293  CB_B_DATA_ONTO_CB_B_PORT                 = 0x00000002,
2294  CR_R_DATA_ONTO_CB_B_PORT                 = 0x00000003,
2295  } CROSSBAR_FOR_CB_B;
2296  
2297  /*
2298   * CROSSBAR_FOR_CR_R enum
2299   */
2300  
2301  typedef enum CROSSBAR_FOR_CR_R {
2302  ALPHA_DATA_ONTO_CR_R_PORT                = 0x00000000,
2303  Y_G_DATA_ONTO_CR_R_PORT                  = 0x00000001,
2304  CB_B_DATA_ONTO_CR_R_PORT                 = 0x00000002,
2305  CR_R_DATA_ONTO_CR_R_PORT                 = 0x00000003,
2306  } CROSSBAR_FOR_CR_R;
2307  
2308  /*
2309   * CROSSBAR_FOR_Y_G enum
2310   */
2311  
2312  typedef enum CROSSBAR_FOR_Y_G {
2313  ALPHA_DATA_ONTO_Y_G_PORT                 = 0x00000000,
2314  Y_G_DATA_ONTO_Y_G_PORT                   = 0x00000001,
2315  CB_B_DATA_ONTO_Y_G_PORT                  = 0x00000002,
2316  CR_R_DATA_ONTO_Y_G_PORT                  = 0x00000003,
2317  } CROSSBAR_FOR_Y_G;
2318  
2319  /*
2320   * DETILE_BUFFER_PACKER_ENABLE enum
2321   */
2322  
2323  typedef enum DETILE_BUFFER_PACKER_ENABLE {
2324  DETILE_BUFFER_PACKER_IS_DISABLE          = 0x00000000,
2325  DETILE_BUFFER_PACKER_IS_ENABLE           = 0x00000001,
2326  } DETILE_BUFFER_PACKER_ENABLE;
2327  
2328  /*
2329   * MEM_PWR_DIS_MODE enum
2330   */
2331  
2332  typedef enum MEM_PWR_DIS_MODE {
2333  MEM_POWER_DIS_MODE_ENABLE                = 0x00000000,
2334  MEM_POWER_DIS_MODE_DISABLE               = 0x00000001,
2335  } MEM_PWR_DIS_MODE;
2336  
2337  /*
2338   * MEM_PWR_FORCE_MODE enum
2339   */
2340  
2341  typedef enum MEM_PWR_FORCE_MODE {
2342  MEM_POWER_FORCE_MODE_OFF                 = 0x00000000,
2343  MEM_POWER_FORCE_MODE_LIGHT_SLEEP         = 0x00000001,
2344  MEM_POWER_FORCE_MODE_DEEP_SLEEP          = 0x00000002,
2345  MEM_POWER_FORCE_MODE_SHUT_DOWN           = 0x00000003,
2346  } MEM_PWR_FORCE_MODE;
2347  
2348  /*
2349   * MEM_PWR_STATUS enum
2350   */
2351  
2352  typedef enum MEM_PWR_STATUS {
2353  MEM_POWER_STATUS_ON                      = 0x00000000,
2354  MEM_POWER_STATUS_LIGHT_SLEEP             = 0x00000001,
2355  MEM_POWER_STATUS_DEEP_SLEEP              = 0x00000002,
2356  MEM_POWER_STATUS_SHUT_DOWN               = 0x00000003,
2357  } MEM_PWR_STATUS;
2358  
2359  /*
2360   * PIPE_INT_MASK_MODE enum
2361   */
2362  
2363  typedef enum PIPE_INT_MASK_MODE {
2364  PIPE_INT_MASK_MODE_DISABLE               = 0x00000000,
2365  PIPE_INT_MASK_MODE_ENABLE                = 0x00000001,
2366  } PIPE_INT_MASK_MODE;
2367  
2368  /*
2369   * PIPE_INT_TYPE_MODE enum
2370   */
2371  
2372  typedef enum PIPE_INT_TYPE_MODE {
2373  PIPE_INT_TYPE_MODE_DISABLE               = 0x00000000,
2374  PIPE_INT_TYPE_MODE_ENABLE                = 0x00000001,
2375  } PIPE_INT_TYPE_MODE;
2376  
2377  /*
2378   * PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE enum
2379   */
2380  
2381  typedef enum PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE {
2382  PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF    = 0x00000000,
2383  PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1      = 0x00000001,
2384  } PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE;
2385  
2386  /*******************************************************
2387   * CURSOR Enums
2388   *******************************************************/
2389  
2390  /*
2391   * CROB_MEM_PWR_LIGHT_SLEEP_MODE enum
2392   */
2393  
2394  typedef enum CROB_MEM_PWR_LIGHT_SLEEP_MODE {
2395  CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF      = 0x00000000,
2396  CROB_MEM_POWER_LIGHT_SLEEP_MODE_1        = 0x00000001,
2397  CROB_MEM_POWER_LIGHT_SLEEP_MODE_2        = 0x00000002,
2398  } CROB_MEM_PWR_LIGHT_SLEEP_MODE;
2399  
2400  /*
2401   * CURSOR_2X_MAGNIFY enum
2402   */
2403  
2404  typedef enum CURSOR_2X_MAGNIFY {
2405  CURSOR_2X_MAGNIFY_IS_DISABLE             = 0x00000000,
2406  CURSOR_2X_MAGNIFY_IS_ENABLE              = 0x00000001,
2407  } CURSOR_2X_MAGNIFY;
2408  
2409  /*
2410   * CURSOR_ENABLE enum
2411   */
2412  
2413  typedef enum CURSOR_ENABLE {
2414  CURSOR_IS_DISABLE                        = 0x00000000,
2415  CURSOR_IS_ENABLE                         = 0x00000001,
2416  } CURSOR_ENABLE;
2417  
2418  /*
2419   * CURSOR_LINES_PER_CHUNK enum
2420   */
2421  
2422  typedef enum CURSOR_LINES_PER_CHUNK {
2423  CURSOR_LINE_PER_CHUNK_1                  = 0x00000000,
2424  CURSOR_LINE_PER_CHUNK_2                  = 0x00000001,
2425  CURSOR_LINE_PER_CHUNK_4                  = 0x00000002,
2426  CURSOR_LINE_PER_CHUNK_8                  = 0x00000003,
2427  CURSOR_LINE_PER_CHUNK_16                 = 0x00000004,
2428  } CURSOR_LINES_PER_CHUNK;
2429  
2430  /*
2431   * CURSOR_MODE enum
2432   */
2433  
2434  typedef enum CURSOR_MODE {
2435  CURSOR_MONO_2BIT                         = 0x00000000,
2436  CURSOR_COLOR_24BIT_1BIT_AND              = 0x00000001,
2437  CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT    = 0x00000002,
2438  CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT  = 0x00000003,
2439  CURSOR_COLOR_64BIT_FP_PREMULT            = 0x00000004,
2440  CURSOR_COLOR_64BIT_FP_UNPREMULT          = 0x00000005,
2441  } CURSOR_MODE;
2442  
2443  /*
2444   * CURSOR_PERFMON_LATENCY_MEASURE_EN enum
2445   */
2446  
2447  typedef enum CURSOR_PERFMON_LATENCY_MEASURE_EN {
2448  CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED = 0x00000000,
2449  CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED = 0x00000001,
2450  } CURSOR_PERFMON_LATENCY_MEASURE_EN;
2451  
2452  /*
2453   * CURSOR_PERFMON_LATENCY_MEASURE_SEL enum
2454   */
2455  
2456  typedef enum CURSOR_PERFMON_LATENCY_MEASURE_SEL {
2457  CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY = 0x00000000,
2458  CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY = 0x00000001,
2459  } CURSOR_PERFMON_LATENCY_MEASURE_SEL;
2460  
2461  /*
2462   * CURSOR_PITCH enum
2463   */
2464  
2465  typedef enum CURSOR_PITCH {
2466  CURSOR_PITCH_64_PIXELS                   = 0x00000000,
2467  CURSOR_PITCH_128_PIXELS                  = 0x00000001,
2468  CURSOR_PITCH_256_PIXELS                  = 0x00000002,
2469  } CURSOR_PITCH;
2470  
2471  /*
2472   * CURSOR_REQ_MODE enum
2473   */
2474  
2475  typedef enum CURSOR_REQ_MODE {
2476  CURSOR_REQUEST_NORMALLY                  = 0x00000000,
2477  CURSOR_REQUEST_EARLY                     = 0x00000001,
2478  } CURSOR_REQ_MODE;
2479  
2480  /*
2481   * CURSOR_SNOOP enum
2482   */
2483  
2484  typedef enum CURSOR_SNOOP {
2485  CURSOR_IS_NOT_SNOOP                      = 0x00000000,
2486  CURSOR_IS_SNOOP                          = 0x00000001,
2487  } CURSOR_SNOOP;
2488  
2489  /*
2490   * CURSOR_STEREO_EN enum
2491   */
2492  
2493  typedef enum CURSOR_STEREO_EN {
2494  CURSOR_STEREO_IS_DISABLED                = 0x00000000,
2495  CURSOR_STEREO_IS_ENABLED                 = 0x00000001,
2496  } CURSOR_STEREO_EN;
2497  
2498  /*
2499   * CURSOR_SURFACE_TMZ enum
2500   */
2501  
2502  typedef enum CURSOR_SURFACE_TMZ {
2503  CURSOR_SURFACE_IS_NOT_TMZ                = 0x00000000,
2504  CURSOR_SURFACE_IS_TMZ                    = 0x00000001,
2505  } CURSOR_SURFACE_TMZ;
2506  
2507  /*
2508   * CURSOR_SYSTEM enum
2509   */
2510  
2511  typedef enum CURSOR_SYSTEM {
2512  CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS        = 0x00000000,
2513  CURSOR_IN_GUEST_PHYSICAL_ADDRESS         = 0x00000001,
2514  } CURSOR_SYSTEM;
2515  
2516  /*
2517   * CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS enum
2518   */
2519  
2520  typedef enum CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS {
2521  CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0 = 0x00000000,
2522  CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1 = 0x00000001,
2523  } CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS;
2524  
2525  /*
2526   * DMDATA_DONE enum
2527   */
2528  
2529  typedef enum DMDATA_DONE {
2530  DMDATA_NOT_SENT_TO_DIG                   = 0x00000000,
2531  DMDATA_SENT_TO_DIG                       = 0x00000001,
2532  } DMDATA_DONE;
2533  
2534  /*
2535   * DMDATA_MODE enum
2536   */
2537  
2538  typedef enum DMDATA_MODE {
2539  DMDATA_SOFTWARE_UPDATE_MODE              = 0x00000000,
2540  DMDATA_HARDWARE_UPDATE_MODE              = 0x00000001,
2541  } DMDATA_MODE;
2542  
2543  /*
2544   * DMDATA_QOS_MODE enum
2545   */
2546  
2547  typedef enum DMDATA_QOS_MODE {
2548  DMDATA_QOS_LEVEL_FROM_TTU                = 0x00000000,
2549  DMDATA_QOS_LEVEL_FROM_SOFTWARE           = 0x00000001,
2550  } DMDATA_QOS_MODE;
2551  
2552  /*
2553   * DMDATA_REPEAT enum
2554   */
2555  
2556  typedef enum DMDATA_REPEAT {
2557  DMDATA_USE_FOR_CURRENT_FRAME_ONLY        = 0x00000000,
2558  DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES = 0x00000001,
2559  } DMDATA_REPEAT;
2560  
2561  /*
2562   * DMDATA_UNDERFLOW enum
2563   */
2564  
2565  typedef enum DMDATA_UNDERFLOW {
2566  DMDATA_NOT_UNDERFLOW                     = 0x00000000,
2567  DMDATA_UNDERFLOWED                       = 0x00000001,
2568  } DMDATA_UNDERFLOW;
2569  
2570  /*
2571   * DMDATA_UNDERFLOW_CLEAR enum
2572   */
2573  
2574  typedef enum DMDATA_UNDERFLOW_CLEAR {
2575  DMDATA_DONT_CLEAR                        = 0x00000000,
2576  DMDATA_CLEAR_UNDERFLOW_STATUS            = 0x00000001,
2577  } DMDATA_UNDERFLOW_CLEAR;
2578  
2579  /*
2580   * DMDATA_UPDATED enum
2581   */
2582  
2583  typedef enum DMDATA_UPDATED {
2584  DMDATA_NOT_UPDATED                       = 0x00000000,
2585  DMDATA_WAS_UPDATED                       = 0x00000001,
2586  } DMDATA_UPDATED;
2587  
2588  /*******************************************************
2589   * HUBBUB_SDPIF Enums
2590   *******************************************************/
2591  
2592  /*
2593   * RESPONSE_STATUS enum
2594   */
2595  
2596  typedef enum RESPONSE_STATUS {
2597  OKAY                                     = 0x00000000,
2598  EXOKAY                                   = 0x00000001,
2599  SLVERR                                   = 0x00000002,
2600  DECERR                                   = 0x00000003,
2601  EARLY                                    = 0x00000004,
2602  OKAY_NODATA                              = 0x00000005,
2603  PROTVIOL                                 = 0x00000006,
2604  TRANSERR                                 = 0x00000007,
2605  CMPTO                                    = 0x00000008,
2606  CRS                                      = 0x0000000c,
2607  } RESPONSE_STATUS;
2608  
2609  /*******************************************************
2610   * HUBBUB_RET_PATH Enums
2611   *******************************************************/
2612  
2613  /*
2614   * DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE enum
2615   */
2616  
2617  typedef enum DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE {
2618  DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0x00000000,
2619  DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_1 = 0x00000001,
2620  DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_2 = 0x00000002,
2621  } DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE;
2622  
2623  /*
2624   * DCHUBBUB_MEM_PWR_DIS_MODE enum
2625   */
2626  
2627  typedef enum DCHUBBUB_MEM_PWR_DIS_MODE {
2628  DCHUBBUB_MEM_POWER_DIS_MODE_ENABLE       = 0x00000000,
2629  DCHUBBUB_MEM_POWER_DIS_MODE_DISABLE      = 0x00000001,
2630  } DCHUBBUB_MEM_PWR_DIS_MODE;
2631  
2632  /*
2633   * DCHUBBUB_MEM_PWR_MODE enum
2634   */
2635  
2636  typedef enum DCHUBBUB_MEM_PWR_MODE {
2637  DCHUBBUB_MEM_POWER_MODE_OFF              = 0x00000000,
2638  DCHUBBUB_MEM_POWER_MODE_LIGHT_SLEEP      = 0x00000001,
2639  DCHUBBUB_MEM_POWER_MODE_DEEP_SLEEP       = 0x00000002,
2640  DCHUBBUB_MEM_POWER_MODE_SHUT_DOWN        = 0x00000003,
2641  } DCHUBBUB_MEM_PWR_MODE;
2642  
2643  /*******************************************************
2644   * MPC_CFG Enums
2645   *******************************************************/
2646  
2647  /*
2648   * MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET enum
2649   */
2650  
2651  typedef enum MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET {
2652  MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0x00000000,
2653  MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 0x00000001,
2654  } MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET;
2655  
2656  /*
2657   * MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET enum
2658   */
2659  
2660  typedef enum MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET {
2661  MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE   = 0x00000000,
2662  MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE    = 0x00000001,
2663  } MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET;
2664  
2665  /*
2666   * MPC_CFG_ADR_VUPDATE_LOCK_SET enum
2667   */
2668  
2669  typedef enum MPC_CFG_ADR_VUPDATE_LOCK_SET {
2670  MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE       = 0x00000000,
2671  MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE        = 0x00000001,
2672  } MPC_CFG_ADR_VUPDATE_LOCK_SET;
2673  
2674  /*
2675   * MPC_CFG_CFG_VUPDATE_LOCK_SET enum
2676   */
2677  
2678  typedef enum MPC_CFG_CFG_VUPDATE_LOCK_SET {
2679  MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE       = 0x00000000,
2680  MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE        = 0x00000001,
2681  } MPC_CFG_CFG_VUPDATE_LOCK_SET;
2682  
2683  /*
2684   * MPC_CFG_CUR_VUPDATE_LOCK_SET enum
2685   */
2686  
2687  typedef enum MPC_CFG_CUR_VUPDATE_LOCK_SET {
2688  MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE       = 0x00000000,
2689  MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE        = 0x00000001,
2690  } MPC_CFG_CUR_VUPDATE_LOCK_SET;
2691  
2692  /*
2693   * MPC_CFG_MPC_TEST_CLK_SEL enum
2694   */
2695  
2696  typedef enum MPC_CFG_MPC_TEST_CLK_SEL {
2697  MPC_CFG_MPC_TEST_CLK_SEL_0               = 0x00000000,
2698  MPC_CFG_MPC_TEST_CLK_SEL_1               = 0x00000001,
2699  MPC_CFG_MPC_TEST_CLK_SEL_2               = 0x00000002,
2700  MPC_CFG_MPC_TEST_CLK_SEL_3               = 0x00000003,
2701  } MPC_CFG_MPC_TEST_CLK_SEL;
2702  
2703  /*
2704   * MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN enum
2705   */
2706  
2707  typedef enum MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN {
2708  MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000,
2709  MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001,
2710  } MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN;
2711  
2712  /*
2713   * MPC_CRC_CALC_INTERLACE_MODE enum
2714   */
2715  
2716  typedef enum MPC_CRC_CALC_INTERLACE_MODE {
2717  MPC_CRC_INTERLACE_MODE_TOP               = 0x00000000,
2718  MPC_CRC_INTERLACE_MODE_BOTTOM            = 0x00000001,
2719  MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM = 0x00000002,
2720  MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH   = 0x00000003,
2721  } MPC_CRC_CALC_INTERLACE_MODE;
2722  
2723  /*
2724   * MPC_CRC_CALC_MODE enum
2725   */
2726  
2727  typedef enum MPC_CRC_CALC_MODE {
2728  MPC_CRC_ONE_SHOT_MODE                    = 0x00000000,
2729  MPC_CRC_CONTINUOUS_MODE                  = 0x00000001,
2730  } MPC_CRC_CALC_MODE;
2731  
2732  /*
2733   * MPC_CRC_CALC_STEREO_MODE enum
2734   */
2735  
2736  typedef enum MPC_CRC_CALC_STEREO_MODE {
2737  MPC_CRC_STEREO_MODE_LEFT                 = 0x00000000,
2738  MPC_CRC_STEREO_MODE_RIGHT                = 0x00000001,
2739  MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT     = 0x00000002,
2740  MPC_CRC_STEREO_MODE_BOTH_RESET_EACH      = 0x00000003,
2741  } MPC_CRC_CALC_STEREO_MODE;
2742  
2743  /*
2744   * MPC_CRC_SOURCE_SELECT enum
2745   */
2746  
2747  typedef enum MPC_CRC_SOURCE_SELECT {
2748  MPC_CRC_SOURCE_SEL_DPP                   = 0x00000000,
2749  MPC_CRC_SOURCE_SEL_OPP                   = 0x00000001,
2750  MPC_CRC_SOURCE_SEL_DWB                   = 0x00000002,
2751  MPC_CRC_SOURCE_SEL_OTHER                 = 0x00000003,
2752  } MPC_CRC_SOURCE_SELECT;
2753  
2754  /*
2755   * MPC_DEBUG_BUS1_DATA_SELECT enum
2756   */
2757  
2758  typedef enum MPC_DEBUG_BUS1_DATA_SELECT {
2759  MPC_DEBUG_BUS1_DATA_SELECT_MPC_CFG       = 0x00000000,
2760  MPC_DEBUG_BUS1_DATA_SELECT_MPC_CONT      = 0x00000001,
2761  MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV1      = 0x00000002,
2762  MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV       = 0x00000003,
2763  } MPC_DEBUG_BUS1_DATA_SELECT;
2764  
2765  /*
2766   * MPC_DEBUG_BUS2_DATA_SELECT enum
2767   */
2768  
2769  typedef enum MPC_DEBUG_BUS2_DATA_SELECT {
2770  MPC_DEBUG_BUS2_DATA_SELECT_MPCC          = 0x00000000,
2771  MPC_DEBUG_BUS2_DATA_SELECT_MPCC_CONT     = 0x00000001,
2772  MPC_DEBUG_BUS2_DATA_SELECT_MPCC_MCM      = 0x00000002,
2773  MPC_DEBUG_BUS2_DATA_SELECT_RES           = 0x00000003,
2774  } MPC_DEBUG_BUS2_DATA_SELECT;
2775  
2776  /*
2777   * MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT enum
2778   */
2779  
2780  typedef enum MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT {
2781  MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_DEBUG_ID = 0x00000000,
2782  MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_DEBUG_ID = 0x00000001,
2783  MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_OGAM_DEBUG_ID = 0x00000002,
2784  MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_OCSC_DEBUG_ID = 0x00000003,
2785  MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFR_DEBUG_DATA = 0x00000004,
2786  MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFT_DEBUG_DATA = 0x00000005,
2787  MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_RSV1 = 0x00000006,
2788  MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_MCM_DEBUG_ID = 0x00000007,
2789  } MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT;
2790  
2791  /*
2792   * MPC_DEBUG_BUS_MPCC_BYTE_SELECT enum
2793   */
2794  
2795  typedef enum MPC_DEBUG_BUS_MPCC_BYTE_SELECT {
2796  MPC_DEBUG_BUS_MPCC_BYTE0                 = 0x00000000,
2797  MPC_DEBUG_BUS_MPCC_BYTE1                 = 0x00000001,
2798  MPC_DEBUG_BUS_MPCC_BYTE2                 = 0x00000002,
2799  MPC_DEBUG_BUS_MPCC_BYTE3                 = 0x00000003,
2800  } MPC_DEBUG_BUS_MPCC_BYTE_SELECT;
2801  
2802  /*******************************************************
2803   * MPC_OCSC Enums
2804   *******************************************************/
2805  
2806  /*
2807   * MPC_OCSC_COEF_FORMAT enum
2808   */
2809  
2810  typedef enum MPC_OCSC_COEF_FORMAT {
2811  MPC_OCSC_COEF_FORMAT_S2_13               = 0x00000000,
2812  MPC_OCSC_COEF_FORMAT_S3_12               = 0x00000001,
2813  } MPC_OCSC_COEF_FORMAT;
2814  
2815  /*
2816   * MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN enum
2817   */
2818  
2819  typedef enum MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN {
2820  MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000,
2821  MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001,
2822  } MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN;
2823  
2824  /*
2825   * MPC_OUT_CSC_MODE enum
2826   */
2827  
2828  typedef enum MPC_OUT_CSC_MODE {
2829  MPC_OUT_CSC_MODE_0                       = 0x00000000,
2830  MPC_OUT_CSC_MODE_1                       = 0x00000001,
2831  MPC_OUT_CSC_MODE_2                       = 0x00000002,
2832  MPC_OUT_CSC_MODE_RSV                     = 0x00000003,
2833  } MPC_OUT_CSC_MODE;
2834  
2835  /*
2836   * MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE enum
2837   */
2838  
2839  typedef enum MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE {
2840  MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS = 0x00000000,
2841  MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS = 0x00000001,
2842  MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS = 0x00000002,
2843  MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS = 0x00000003,
2844  MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS = 0x00000004,
2845  MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS = 0x00000005,
2846  MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS = 0x00000006,
2847  MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH = 0x00000007,
2848  } MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE;
2849  
2850  /*
2851   * MPC_OUT_RATE_CONTROL_DISABLE_SET enum
2852   */
2853  
2854  typedef enum MPC_OUT_RATE_CONTROL_DISABLE_SET {
2855  MPC_OUT_RATE_CONTROL_SET_ENABLE          = 0x00000000,
2856  MPC_OUT_RATE_CONTROL_SET_DISABLE         = 0x00000001,
2857  } MPC_OUT_RATE_CONTROL_DISABLE_SET;
2858  
2859  /*******************************************************
2860   * MPCC Enums
2861   *******************************************************/
2862  
2863  /*
2864   * MPCC_BG_COLOR_BPC enum
2865   */
2866  
2867  typedef enum MPCC_BG_COLOR_BPC {
2868  MPCC_BG_COLOR_BPC_8bit                   = 0x00000000,
2869  MPCC_BG_COLOR_BPC_9bit                   = 0x00000001,
2870  MPCC_BG_COLOR_BPC_10bit                  = 0x00000002,
2871  MPCC_BG_COLOR_BPC_11bit                  = 0x00000003,
2872  MPCC_BG_COLOR_BPC_12bit                  = 0x00000004,
2873  } MPCC_BG_COLOR_BPC;
2874  
2875  /*
2876   * MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY enum
2877   */
2878  
2879  typedef enum MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY {
2880  MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE = 0x00000000,
2881  MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE = 0x00000001,
2882  } MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY;
2883  
2884  /*
2885   * MPCC_CONTROL_MPCC_ALPHA_BLND_MODE enum
2886   */
2887  
2888  typedef enum MPCC_CONTROL_MPCC_ALPHA_BLND_MODE {
2889  MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA = 0x00000000,
2890  MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 0x00000001,
2891  MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA = 0x00000002,
2892  MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED = 0x00000003,
2893  } MPCC_CONTROL_MPCC_ALPHA_BLND_MODE;
2894  
2895  /*
2896   * MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE enum
2897   */
2898  
2899  typedef enum MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE {
2900  MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE = 0x00000000,
2901  MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE = 0x00000001,
2902  } MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE;
2903  
2904  /*
2905   * MPCC_CONTROL_MPCC_BOT_GAIN_MODE enum
2906   */
2907  
2908  typedef enum MPCC_CONTROL_MPCC_BOT_GAIN_MODE {
2909  MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0        = 0x00000000,
2910  MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1        = 0x00000001,
2911  } MPCC_CONTROL_MPCC_BOT_GAIN_MODE;
2912  
2913  /*
2914   * MPCC_CONTROL_MPCC_MODE enum
2915   */
2916  
2917  typedef enum MPCC_CONTROL_MPCC_MODE {
2918  MPCC_CONTROL_MPCC_MODE_BYPASS            = 0x00000000,
2919  MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH = 0x00000001,
2920  MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY    = 0x00000002,
2921  MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING  = 0x00000003,
2922  } MPCC_CONTROL_MPCC_MODE;
2923  
2924  /*
2925   * MPCC_SM_CONTROL_MPCC_SM_EN enum
2926   */
2927  
2928  typedef enum MPCC_SM_CONTROL_MPCC_SM_EN {
2929  MPCC_SM_CONTROL_MPCC_SM_EN_FALSE         = 0x00000000,
2930  MPCC_SM_CONTROL_MPCC_SM_EN_TRUE          = 0x00000001,
2931  } MPCC_SM_CONTROL_MPCC_SM_EN;
2932  
2933  /*
2934   * MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT enum
2935   */
2936  
2937  typedef enum MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT {
2938  MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE  = 0x00000000,
2939  MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE   = 0x00000001,
2940  } MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT;
2941  
2942  /*
2943   * MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL enum
2944   */
2945  
2946  typedef enum MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL {
2947  MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0x00000000,
2948  MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED = 0x00000001,
2949  MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 0x00000002,
2950  MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 0x00000003,
2951  } MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL;
2952  
2953  /*
2954   * MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL enum
2955   */
2956  
2957  typedef enum MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL {
2958  MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x00000000,
2959  MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x00000001,
2960  MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x00000002,
2961  MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 0x00000003,
2962  } MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL;
2963  
2964  /*
2965   * MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT enum
2966   */
2967  
2968  typedef enum MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT {
2969  MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE  = 0x00000000,
2970  MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE   = 0x00000001,
2971  } MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT;
2972  
2973  /*
2974   * MPCC_SM_CONTROL_MPCC_SM_MODE enum
2975   */
2976  
2977  typedef enum MPCC_SM_CONTROL_MPCC_SM_MODE {
2978  MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE = 0x00000000,
2979  MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING = 0x00000002,
2980  MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING = 0x00000004,
2981  MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING = 0x00000006,
2982  } MPCC_SM_CONTROL_MPCC_SM_MODE;
2983  
2984  /*
2985   * MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN enum
2986   */
2987  
2988  typedef enum MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN {
2989  MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000,
2990  MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001,
2991  } MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN;
2992  
2993  /*******************************************************
2994   * MPCC_OGAM Enums
2995   *******************************************************/
2996  
2997  /*
2998   * MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM enum
2999   */
3000  
3001  typedef enum MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM {
3002  MPCC_GAMUT_REMAP_COEF_FORMAT_S2_13       = 0x00000000,
3003  MPCC_GAMUT_REMAP_COEF_FORMAT_S3_12       = 0x00000001,
3004  } MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM;
3005  
3006  /*
3007   * MPCC_GAMUT_REMAP_MODE_ENUM enum
3008   */
3009  
3010  typedef enum MPCC_GAMUT_REMAP_MODE_ENUM {
3011  MPCC_GAMUT_REMAP_MODE_0                  = 0x00000000,
3012  MPCC_GAMUT_REMAP_MODE_1                  = 0x00000001,
3013  MPCC_GAMUT_REMAP_MODE_2                  = 0x00000002,
3014  MPCC_GAMUT_REMAP_MODE_RSV                = 0x00000003,
3015  } MPCC_GAMUT_REMAP_MODE_ENUM;
3016  
3017  /*
3018   * MPCC_OGAM_LUT_2_CONFIG_ENUM enum
3019   */
3020  
3021  typedef enum MPCC_OGAM_LUT_2_CONFIG_ENUM {
3022  MPCC_OGAM_LUT_2CFG_NO_MEMORY             = 0x00000000,
3023  MPCC_OGAM_LUT_2CFG_MEMORY_A              = 0x00000001,
3024  MPCC_OGAM_LUT_2CFG_MEMORY_B              = 0x00000002,
3025  } MPCC_OGAM_LUT_2_CONFIG_ENUM;
3026  
3027  /*
3028   * MPCC_OGAM_LUT_CONFIG_MODE enum
3029   */
3030  
3031  typedef enum MPCC_OGAM_LUT_CONFIG_MODE {
3032  MPCC_OGAM_DIFFERENT_RGB                  = 0x00000000,
3033  MPCC_OGAM_ALL_USE_R                      = 0x00000001,
3034  } MPCC_OGAM_LUT_CONFIG_MODE;
3035  
3036  /*
3037   * MPCC_OGAM_LUT_PWL_DISABLE_ENUM enum
3038   */
3039  
3040  typedef enum MPCC_OGAM_LUT_PWL_DISABLE_ENUM {
3041  MPCC_OGAM_ENABLE_PWL                     = 0x00000000,
3042  MPCC_OGAM_DISABLE_PWL                    = 0x00000001,
3043  } MPCC_OGAM_LUT_PWL_DISABLE_ENUM;
3044  
3045  /*
3046   * MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL enum
3047   */
3048  
3049  typedef enum MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL {
3050  MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA = 0x00000000,
3051  MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB = 0x00000001,
3052  } MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL;
3053  
3054  /*
3055   * MPCC_OGAM_LUT_RAM_SEL enum
3056   */
3057  
3058  typedef enum MPCC_OGAM_LUT_RAM_SEL {
3059  MPCC_OGAM_RAMA_ACCESS                    = 0x00000000,
3060  MPCC_OGAM_RAMB_ACCESS                    = 0x00000001,
3061  } MPCC_OGAM_LUT_RAM_SEL;
3062  
3063  /*
3064   * MPCC_OGAM_LUT_READ_COLOR_SEL enum
3065   */
3066  
3067  typedef enum MPCC_OGAM_LUT_READ_COLOR_SEL {
3068  MPCC_OGAM_BLUE_LUT                       = 0x00000000,
3069  MPCC_OGAM_GREEN_LUT                      = 0x00000001,
3070  MPCC_OGAM_RED_LUT                        = 0x00000002,
3071  } MPCC_OGAM_LUT_READ_COLOR_SEL;
3072  
3073  /*
3074   * MPCC_OGAM_LUT_READ_DBG enum
3075   */
3076  
3077  typedef enum MPCC_OGAM_LUT_READ_DBG {
3078  MPCC_OGAM_DISABLE_DEBUG                  = 0x00000000,
3079  MPCC_OGAM_ENABLE_DEBUG                   = 0x00000001,
3080  } MPCC_OGAM_LUT_READ_DBG;
3081  
3082  /*
3083   * MPCC_OGAM_LUT_SEL_ENUM enum
3084   */
3085  
3086  typedef enum MPCC_OGAM_LUT_SEL_ENUM {
3087  MPCC_OGAM_RAMA                           = 0x00000000,
3088  MPCC_OGAM_RAMB                           = 0x00000001,
3089  } MPCC_OGAM_LUT_SEL_ENUM;
3090  
3091  /*
3092   * MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM enum
3093   */
3094  
3095  typedef enum MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM {
3096  MPCC_OGAM_MODE_0                         = 0x00000000,
3097  MPCC_OGAM_MODE_RSV1                      = 0x00000001,
3098  MPCC_OGAM_MODE_2                         = 0x00000002,
3099  MPCC_OGAM_MODE_RSV                       = 0x00000003,
3100  } MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM;
3101  
3102  /*
3103   * MPCC_OGAM_NUM_SEG enum
3104   */
3105  
3106  typedef enum MPCC_OGAM_NUM_SEG {
3107  MPCC_OGAM_SEGMENTS_1                     = 0x00000000,
3108  MPCC_OGAM_SEGMENTS_2                     = 0x00000001,
3109  MPCC_OGAM_SEGMENTS_4                     = 0x00000002,
3110  MPCC_OGAM_SEGMENTS_8                     = 0x00000003,
3111  MPCC_OGAM_SEGMENTS_16                    = 0x00000004,
3112  MPCC_OGAM_SEGMENTS_32                    = 0x00000005,
3113  MPCC_OGAM_SEGMENTS_64                    = 0x00000006,
3114  MPCC_OGAM_SEGMENTS_128                   = 0x00000007,
3115  } MPCC_OGAM_NUM_SEG;
3116  
3117  /*
3118   * MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN enum
3119   */
3120  
3121  typedef enum MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN {
3122  MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000,
3123  MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001,
3124  } MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN;
3125  
3126  /*******************************************************
3127   * MPCC_MCM Enums
3128   *******************************************************/
3129  
3130  /*
3131   * MPCC_MCM_3DLUT_30BIT_ENUM enum
3132   */
3133  
3134  typedef enum MPCC_MCM_3DLUT_30BIT_ENUM {
3135  MPCC_MCM_3DLUT_36BIT                     = 0x00000000,
3136  MPCC_MCM_3DLUT_30BIT                     = 0x00000001,
3137  } MPCC_MCM_3DLUT_30BIT_ENUM;
3138  
3139  /*
3140   * MPCC_MCM_3DLUT_RAM_SEL enum
3141   */
3142  
3143  typedef enum MPCC_MCM_3DLUT_RAM_SEL {
3144  MPCC_MCM_RAM0_ACCESS                     = 0x00000000,
3145  MPCC_MCM_RAM1_ACCESS                     = 0x00000001,
3146  MPCC_MCM_RAM2_ACCESS                     = 0x00000002,
3147  MPCC_MCM_RAM3_ACCESS                     = 0x00000003,
3148  } MPCC_MCM_3DLUT_RAM_SEL;
3149  
3150  /*
3151   * MPCC_MCM_3DLUT_SIZE_ENUM enum
3152   */
3153  
3154  typedef enum MPCC_MCM_3DLUT_SIZE_ENUM {
3155  MPCC_MCM_3DLUT_17CUBE                    = 0x00000000,
3156  MPCC_MCM_3DLUT_9CUBE                     = 0x00000001,
3157  } MPCC_MCM_3DLUT_SIZE_ENUM;
3158  
3159  /*
3160   * MPCC_MCM_GAMMA_LUT_MODE_ENUM enum
3161   */
3162  
3163  typedef enum MPCC_MCM_GAMMA_LUT_MODE_ENUM {
3164  MPCC_MCM_GAMMA_LUT_BYPASS                = 0x00000000,
3165  MPCC_MCM_GAMMA_LUT_RESERVED_1            = 0x00000001,
3166  MPCC_MCM_GAMMA_LUT_RAM_LUT               = 0x00000002,
3167  MPCC_MCM_GAMMA_LUT_RESERVED_3            = 0x00000003,
3168  } MPCC_MCM_GAMMA_LUT_MODE_ENUM;
3169  
3170  /*
3171   * MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM enum
3172   */
3173  
3174  typedef enum MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM {
3175  MPCC_MCM_GAMMA_LUT_ENABLE_PWL            = 0x00000000,
3176  MPCC_MCM_GAMMA_LUT_DISABLE_PWL           = 0x00000001,
3177  } MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM;
3178  
3179  /*
3180   * MPCC_MCM_GAMMA_LUT_SEL_ENUM enum
3181   */
3182  
3183  typedef enum MPCC_MCM_GAMMA_LUT_SEL_ENUM {
3184  MPCC_MCM_GAMMA_LUT_RAMA                  = 0x00000000,
3185  MPCC_MCM_GAMMA_LUT_RAMB                  = 0x00000001,
3186  } MPCC_MCM_GAMMA_LUT_SEL_ENUM;
3187  
3188  /*
3189   * MPCC_MCM_LUT_2_MODE_ENUM enum
3190   */
3191  
3192  typedef enum MPCC_MCM_LUT_2_MODE_ENUM {
3193  MPCC_MCM_LUT_2_MODE_BYPASS               = 0x00000000,
3194  MPCC_MCM_LUT_2_MODE_RAMA_LUT             = 0x00000001,
3195  MPCC_MCM_LUT_2_MODE_RAMB_LUT             = 0x00000002,
3196  } MPCC_MCM_LUT_2_MODE_ENUM;
3197  
3198  /*
3199   * MPCC_MCM_LUT_CONFIG_MODE enum
3200   */
3201  
3202  typedef enum MPCC_MCM_LUT_CONFIG_MODE {
3203  MPCC_MCM_LUT_DIFFERENT_RGB               = 0x00000000,
3204  MPCC_MCM_LUT_ALL_USE_R                   = 0x00000001,
3205  } MPCC_MCM_LUT_CONFIG_MODE;
3206  
3207  /*
3208   * MPCC_MCM_LUT_NUM_SEG enum
3209   */
3210  
3211  typedef enum MPCC_MCM_LUT_NUM_SEG {
3212  MPCC_MCM_LUT_SEGMENTS_1                  = 0x00000000,
3213  MPCC_MCM_LUT_SEGMENTS_2                  = 0x00000001,
3214  MPCC_MCM_LUT_SEGMENTS_4                  = 0x00000002,
3215  MPCC_MCM_LUT_SEGMENTS_8                  = 0x00000003,
3216  MPCC_MCM_LUT_SEGMENTS_16                 = 0x00000004,
3217  MPCC_MCM_LUT_SEGMENTS_32                 = 0x00000005,
3218  MPCC_MCM_LUT_SEGMENTS_64                 = 0x00000006,
3219  MPCC_MCM_LUT_SEGMENTS_128                = 0x00000007,
3220  } MPCC_MCM_LUT_NUM_SEG;
3221  
3222  /*
3223   * MPCC_MCM_LUT_RAM_SEL enum
3224   */
3225  
3226  typedef enum MPCC_MCM_LUT_RAM_SEL {
3227  MPCC_MCM_LUT_RAMA_ACCESS                 = 0x00000000,
3228  MPCC_MCM_LUT_RAMB_ACCESS                 = 0x00000001,
3229  } MPCC_MCM_LUT_RAM_SEL;
3230  
3231  /*
3232   * MPCC_MCM_LUT_READ_COLOR_SEL enum
3233   */
3234  
3235  typedef enum MPCC_MCM_LUT_READ_COLOR_SEL {
3236  MPCC_MCM_LUT_BLUE_LUT                    = 0x00000000,
3237  MPCC_MCM_LUT_GREEN_LUT                   = 0x00000001,
3238  MPCC_MCM_LUT_RED_LUT                     = 0x00000002,
3239  } MPCC_MCM_LUT_READ_COLOR_SEL;
3240  
3241  /*
3242   * MPCC_MCM_LUT_READ_DBG enum
3243   */
3244  
3245  typedef enum MPCC_MCM_LUT_READ_DBG {
3246  MPCC_MCM_LUT_DISABLE_DEBUG               = 0x00000000,
3247  MPCC_MCM_LUT_ENABLE_DEBUG                = 0x00000001,
3248  } MPCC_MCM_LUT_READ_DBG;
3249  
3250  /*
3251   * MPCC_MCM_MEM_PWR_FORCE_ENUM enum
3252   */
3253  
3254  typedef enum MPCC_MCM_MEM_PWR_FORCE_ENUM {
3255  MPCC_MCM_MEM_PWR_FORCE_DIS               = 0x00000000,
3256  MPCC_MCM_MEM_PWR_FORCE_LS                = 0x00000001,
3257  MPCC_MCM_MEM_PWR_FORCE_DS                = 0x00000002,
3258  MPCC_MCM_MEM_PWR_FORCE_SD                = 0x00000003,
3259  } MPCC_MCM_MEM_PWR_FORCE_ENUM;
3260  
3261  /*
3262   * MPCC_MCM_MEM_PWR_STATE_ENUM enum
3263   */
3264  
3265  typedef enum MPCC_MCM_MEM_PWR_STATE_ENUM {
3266  MPCC_MCM_MEM_PWR_STATE_ON                = 0x00000000,
3267  MPCC_MCM_MEM_PWR_STATE_LS                = 0x00000001,
3268  MPCC_MCM_MEM_PWR_STATE_DS                = 0x00000002,
3269  MPCC_MCM_MEM_PWR_STATE_SD                = 0x00000003,
3270  } MPCC_MCM_MEM_PWR_STATE_ENUM;
3271  
3272  /*******************************************************
3273   * ABM Enums
3274   *******************************************************/
3275  
3276  /*******************************************************
3277   * DPG Enums
3278   *******************************************************/
3279  
3280  /*
3281   * ENUM_DPG_BIT_DEPTH enum
3282   */
3283  
3284  typedef enum ENUM_DPG_BIT_DEPTH {
3285  ENUM_DPG_BIT_DEPTH_6BPC                  = 0x00000000,
3286  ENUM_DPG_BIT_DEPTH_8BPC                  = 0x00000001,
3287  ENUM_DPG_BIT_DEPTH_10BPC                 = 0x00000002,
3288  ENUM_DPG_BIT_DEPTH_12BPC                 = 0x00000003,
3289  } ENUM_DPG_BIT_DEPTH;
3290  
3291  /*
3292   * ENUM_DPG_DYNAMIC_RANGE enum
3293   */
3294  
3295  typedef enum ENUM_DPG_DYNAMIC_RANGE {
3296  ENUM_DPG_DYNAMIC_RANGE_VESA              = 0x00000000,
3297  ENUM_DPG_DYNAMIC_RANGE_CEA               = 0x00000001,
3298  } ENUM_DPG_DYNAMIC_RANGE;
3299  
3300  /*
3301   * ENUM_DPG_EN enum
3302   */
3303  
3304  typedef enum ENUM_DPG_EN {
3305  ENUM_DPG_DISABLE                         = 0x00000000,
3306  ENUM_DPG_ENABLE                          = 0x00000001,
3307  } ENUM_DPG_EN;
3308  
3309  /*
3310   * ENUM_DPG_FIELD_POLARITY enum
3311   */
3312  
3313  typedef enum ENUM_DPG_FIELD_POLARITY {
3314  ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD = 0x00000000,
3315  ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN = 0x00000001,
3316  } ENUM_DPG_FIELD_POLARITY;
3317  
3318  /*
3319   * ENUM_DPG_MODE enum
3320   */
3321  
3322  typedef enum ENUM_DPG_MODE {
3323  ENUM_DPG_MODE_RGB_COLOUR_BLOCK           = 0x00000000,
3324  ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK     = 0x00000001,
3325  ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK     = 0x00000002,
3326  ENUM_DPG_MODE_VERTICAL_BAR               = 0x00000003,
3327  ENUM_DPG_MODE_HORIZONTAL_BAR             = 0x00000004,
3328  ENUM_DPG_MODE_RGB_SINGLE_RAMP            = 0x00000005,
3329  ENUM_DPG_MODE_RGB_DUAL_RAMP              = 0x00000006,
3330  ENUM_DPG_MODE_RGB_XR_BIAS                = 0x00000007,
3331  } ENUM_DPG_MODE;
3332  
3333  /*******************************************************
3334   * FMT Enums
3335   *******************************************************/
3336  
3337  /*
3338   * FMTMEM_PWR_DIS_CTRL enum
3339   */
3340  
3341  typedef enum FMTMEM_PWR_DIS_CTRL {
3342  FMTMEM_ENABLE_MEM_PWR_CTRL               = 0x00000000,
3343  FMTMEM_DISABLE_MEM_PWR_CTRL              = 0x00000001,
3344  } FMTMEM_PWR_DIS_CTRL;
3345  
3346  /*
3347   * FMTMEM_PWR_FORCE_CTRL enum
3348   */
3349  
3350  typedef enum FMTMEM_PWR_FORCE_CTRL {
3351  FMTMEM_NO_FORCE_REQUEST                  = 0x00000000,
3352  FMTMEM_FORCE_LIGHT_SLEEP_REQUEST         = 0x00000001,
3353  FMTMEM_FORCE_DEEP_SLEEP_REQUEST          = 0x00000002,
3354  FMTMEM_FORCE_SHUT_DOWN_REQUEST           = 0x00000003,
3355  } FMTMEM_PWR_FORCE_CTRL;
3356  
3357  /*
3358   * FMT_BIT_DEPTH_CONTROL_25FRC_SEL enum
3359   */
3360  
3361  typedef enum FMT_BIT_DEPTH_CONTROL_25FRC_SEL {
3362  FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei       = 0x00000000,
3363  FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi       = 0x00000001,
3364  FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi       = 0x00000002,
3365  FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 0x00000003,
3366  } FMT_BIT_DEPTH_CONTROL_25FRC_SEL;
3367  
3368  /*
3369   * FMT_BIT_DEPTH_CONTROL_50FRC_SEL enum
3370   */
3371  
3372  typedef enum FMT_BIT_DEPTH_CONTROL_50FRC_SEL {
3373  FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A        = 0x00000000,
3374  FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B        = 0x00000001,
3375  FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C        = 0x00000002,
3376  FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D        = 0x00000003,
3377  } FMT_BIT_DEPTH_CONTROL_50FRC_SEL;
3378  
3379  /*
3380   * FMT_BIT_DEPTH_CONTROL_75FRC_SEL enum
3381   */
3382  
3383  typedef enum FMT_BIT_DEPTH_CONTROL_75FRC_SEL {
3384  FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E        = 0x00000000,
3385  FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F        = 0x00000001,
3386  FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G        = 0x00000002,
3387  FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 0x00000003,
3388  } FMT_BIT_DEPTH_CONTROL_75FRC_SEL;
3389  
3390  /*
3391   * FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH enum
3392   */
3393  
3394  typedef enum FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH {
3395  FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0x00000000,
3396  FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 0x00000001,
3397  FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 0x00000002,
3398  } FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH;
3399  
3400  /*
3401   * FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH enum
3402   */
3403  
3404  typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH {
3405  FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP = 0x00000000,
3406  FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP = 0x00000001,
3407  FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP = 0x00000002,
3408  } FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH;
3409  
3410  /*
3411   * FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL enum
3412   */
3413  
3414  typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL {
3415  FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0x00000000,
3416  FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 0x00000001,
3417  } FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL;
3418  
3419  /*
3420   * FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH enum
3421   */
3422  
3423  typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH {
3424  FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0x00000000,
3425  FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 0x00000001,
3426  FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 0x00000002,
3427  } FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH;
3428  
3429  /*
3430   * FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE enum
3431   */
3432  
3433  typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE {
3434  FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0x00000000,
3435  FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 0x00000001,
3436  } FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE;
3437  
3438  /*
3439   * FMT_CLAMP_CNTL_COLOR_FORMAT enum
3440   */
3441  
3442  typedef enum FMT_CLAMP_CNTL_COLOR_FORMAT {
3443  FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC         = 0x00000000,
3444  FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC         = 0x00000001,
3445  FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC        = 0x00000002,
3446  FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC        = 0x00000003,
3447  FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1    = 0x00000004,
3448  FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2    = 0x00000005,
3449  FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3    = 0x00000006,
3450  FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 0x00000007,
3451  } FMT_CLAMP_CNTL_COLOR_FORMAT;
3452  
3453  /*
3454   * FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS enum
3455   */
3456  
3457  typedef enum FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS {
3458  FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE = 0x00000000,
3459  FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE = 0x00000001,
3460  } FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS;
3461  
3462  /*
3463   * FMT_CONTROL_PIXEL_ENCODING enum
3464   */
3465  
3466  typedef enum FMT_CONTROL_PIXEL_ENCODING {
3467  FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0x00000000,
3468  FMT_CONTROL_PIXEL_ENCODING_YCBCR422      = 0x00000001,
3469  FMT_CONTROL_PIXEL_ENCODING_YCBCR420      = 0x00000002,
3470  FMT_CONTROL_PIXEL_ENCODING_RESERVED      = 0x00000003,
3471  } FMT_CONTROL_PIXEL_ENCODING;
3472  
3473  /*
3474   * FMT_CONTROL_SUBSAMPLING_MODE enum
3475   */
3476  
3477  typedef enum FMT_CONTROL_SUBSAMPLING_MODE {
3478  FMT_CONTROL_SUBSAMPLING_MODE_DROP        = 0x00000000,
3479  FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE     = 0x00000001,
3480  FMT_CONTROL_SUBSAMPLING_MOME_3_TAP       = 0x00000002,
3481  FMT_CONTROL_SUBSAMPLING_MOME_RESERVED    = 0x00000003,
3482  } FMT_CONTROL_SUBSAMPLING_MODE;
3483  
3484  /*
3485   * FMT_CONTROL_SUBSAMPLING_ORDER enum
3486   */
3487  
3488  typedef enum FMT_CONTROL_SUBSAMPLING_ORDER {
3489  FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0x00000000,
3490  FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 0x00000001,
3491  } FMT_CONTROL_SUBSAMPLING_ORDER;
3492  
3493  /*
3494   * FMT_DEBUG_CNTL_COLOR_SELECT enum
3495   */
3496  
3497  typedef enum FMT_DEBUG_CNTL_COLOR_SELECT {
3498  FMT_DEBUG_CNTL_COLOR_SELECT_BLUE         = 0x00000000,
3499  FMT_DEBUG_CNTL_COLOR_SELECT_GREEN        = 0x00000001,
3500  FMT_DEBUG_CNTL_COLOR_SELECT_RED1         = 0x00000002,
3501  FMT_DEBUG_CNTL_COLOR_SELECT_RED2         = 0x00000003,
3502  } FMT_DEBUG_CNTL_COLOR_SELECT;
3503  
3504  /*
3505   * FMT_DYNAMIC_EXP_MODE enum
3506   */
3507  
3508  typedef enum FMT_DYNAMIC_EXP_MODE {
3509  FMT_DYNAMIC_EXP_MODE_10to12              = 0x00000000,
3510  FMT_DYNAMIC_EXP_MODE_8to12               = 0x00000001,
3511  } FMT_DYNAMIC_EXP_MODE;
3512  
3513  /*
3514   * FMT_FRAME_RANDOM_ENABLE_CONTROL enum
3515   */
3516  
3517  typedef enum FMT_FRAME_RANDOM_ENABLE_CONTROL {
3518  FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME = 0x00000000,
3519  FMT_FRAME_RANDOM_ENABLE_RESET_ONCE       = 0x00000001,
3520  } FMT_FRAME_RANDOM_ENABLE_CONTROL;
3521  
3522  /*
3523   * FMT_POWER_STATE_ENUM enum
3524   */
3525  
3526  typedef enum FMT_POWER_STATE_ENUM {
3527  FMT_POWER_STATE_ENUM_ON                  = 0x00000000,
3528  FMT_POWER_STATE_ENUM_LS                  = 0x00000001,
3529  FMT_POWER_STATE_ENUM_DS                  = 0x00000002,
3530  FMT_POWER_STATE_ENUM_SD                  = 0x00000003,
3531  } FMT_POWER_STATE_ENUM;
3532  
3533  /*
3534   * FMT_RGB_RANDOM_ENABLE_CONTROL enum
3535   */
3536  
3537  typedef enum FMT_RGB_RANDOM_ENABLE_CONTROL {
3538  FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE    = 0x00000000,
3539  FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE     = 0x00000001,
3540  } FMT_RGB_RANDOM_ENABLE_CONTROL;
3541  
3542  /*
3543   * FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL enum
3544   */
3545  
3546  typedef enum FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL {
3547  FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP = 0x00000000,
3548  FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1 = 0x00000001,
3549  FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2 = 0x00000002,
3550  FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED = 0x00000003,
3551  } FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL;
3552  
3553  /*
3554   * FMT_SPATIAL_DITHER_MODE enum
3555   */
3556  
3557  typedef enum FMT_SPATIAL_DITHER_MODE {
3558  FMT_SPATIAL_DITHER_MODE_0                = 0x00000000,
3559  FMT_SPATIAL_DITHER_MODE_1                = 0x00000001,
3560  FMT_SPATIAL_DITHER_MODE_2                = 0x00000002,
3561  FMT_SPATIAL_DITHER_MODE_3                = 0x00000003,
3562  } FMT_SPATIAL_DITHER_MODE;
3563  
3564  /*
3565   * FMT_STEREOSYNC_OVERRIDE_CONTROL enum
3566   */
3567  
3568  typedef enum FMT_STEREOSYNC_OVERRIDE_CONTROL {
3569  FMT_STEREOSYNC_OVERRIDE_CONTROL_0        = 0x00000000,
3570  FMT_STEREOSYNC_OVERRIDE_CONTROL_1        = 0x00000001,
3571  } FMT_STEREOSYNC_OVERRIDE_CONTROL;
3572  
3573  /*
3574   * FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 enum
3575   */
3576  
3577  typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 {
3578  FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR = 0x00000000,
3579  FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB = 0x00000001,
3580  } FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0;
3581  
3582  /*******************************************************
3583   * OPPBUF Enums
3584   *******************************************************/
3585  
3586  /*
3587   * OPPBUF_DISPLAY_SEGMENTATION enum
3588   */
3589  
3590  typedef enum OPPBUF_DISPLAY_SEGMENTATION {
3591  OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT    = 0x00000000,
3592  OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT    = 0x00000001,
3593  OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT    = 0x00000002,
3594  OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT = 0x00000003,
3595  OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT = 0x00000004,
3596  } OPPBUF_DISPLAY_SEGMENTATION;
3597  
3598  /*******************************************************
3599   * OPP_PIPE Enums
3600   *******************************************************/
3601  
3602  /*
3603   * OPP_PIPE_CLOCK_ENABLE_CONTROL enum
3604   */
3605  
3606  typedef enum OPP_PIPE_CLOCK_ENABLE_CONTROL {
3607  OPP_PIPE_CLOCK_DISABLE                   = 0x00000000,
3608  OPP_PIPE_CLOCK_ENABLE                    = 0x00000001,
3609  } OPP_PIPE_CLOCK_ENABLE_CONTROL;
3610  
3611  /*
3612   * OPP_PIPE_DIGTIAL_BYPASS_CONTROL enum
3613   */
3614  
3615  typedef enum OPP_PIPE_DIGTIAL_BYPASS_CONTROL {
3616  OPP_PIPE_DIGTIAL_BYPASS_DISABLE          = 0x00000000,
3617  OPP_PIPE_DIGTIAL_BYPASS_ENABLE           = 0x00000001,
3618  } OPP_PIPE_DIGTIAL_BYPASS_CONTROL;
3619  
3620  /*******************************************************
3621   * OPP_PIPE_CRC Enums
3622   *******************************************************/
3623  
3624  /*
3625   * OPP_PIPE_CRC_CONT_EN enum
3626   */
3627  
3628  typedef enum OPP_PIPE_CRC_CONT_EN {
3629  OPP_PIPE_CRC_MODE_ONE_SHOT               = 0x00000000,
3630  OPP_PIPE_CRC_MODE_CONTINUOUS             = 0x00000001,
3631  } OPP_PIPE_CRC_CONT_EN;
3632  
3633  /*
3634   * OPP_PIPE_CRC_EN enum
3635   */
3636  
3637  typedef enum OPP_PIPE_CRC_EN {
3638  OPP_PIPE_CRC_DISABLE                     = 0x00000000,
3639  OPP_PIPE_CRC_ENABLE                      = 0x00000001,
3640  } OPP_PIPE_CRC_EN;
3641  
3642  /*
3643   * OPP_PIPE_CRC_INTERLACE_EN enum
3644   */
3645  
3646  typedef enum OPP_PIPE_CRC_INTERLACE_EN {
3647  OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE = 0x00000000,
3648  OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED = 0x00000001,
3649  } OPP_PIPE_CRC_INTERLACE_EN;
3650  
3651  /*
3652   * OPP_PIPE_CRC_INTERLACE_MODE enum
3653   */
3654  
3655  typedef enum OPP_PIPE_CRC_INTERLACE_MODE {
3656  OPP_PIPE_CRC_INTERLACE_MODE_TOP          = 0x00000000,
3657  OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM       = 0x00000001,
3658  OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD = 0x00000002,
3659  OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD = 0x00000003,
3660  } OPP_PIPE_CRC_INTERLACE_MODE;
3661  
3662  /*
3663   * OPP_PIPE_CRC_ONE_SHOT_PENDING enum
3664   */
3665  
3666  typedef enum OPP_PIPE_CRC_ONE_SHOT_PENDING {
3667  OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING = 0x00000000,
3668  OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING    = 0x00000001,
3669  } OPP_PIPE_CRC_ONE_SHOT_PENDING;
3670  
3671  /*
3672   * OPP_PIPE_CRC_PIXEL_SELECT enum
3673   */
3674  
3675  typedef enum OPP_PIPE_CRC_PIXEL_SELECT {
3676  OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS     = 0x00000000,
3677  OPP_PIPE_CRC_PIXEL_SELECT_RESERVED       = 0x00000001,
3678  OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS    = 0x00000002,
3679  OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS     = 0x00000003,
3680  } OPP_PIPE_CRC_PIXEL_SELECT;
3681  
3682  /*
3683   * OPP_PIPE_CRC_SOURCE_SELECT enum
3684   */
3685  
3686  typedef enum OPP_PIPE_CRC_SOURCE_SELECT {
3687  OPP_PIPE_CRC_SOURCE_SELECT_FMT           = 0x00000000,
3688  OPP_PIPE_CRC_SOURCE_SELECT_SFT           = 0x00000001,
3689  } OPP_PIPE_CRC_SOURCE_SELECT;
3690  
3691  /*
3692   * OPP_PIPE_CRC_STEREO_EN enum
3693   */
3694  
3695  typedef enum OPP_PIPE_CRC_STEREO_EN {
3696  OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO = 0x00000000,
3697  OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO = 0x00000001,
3698  } OPP_PIPE_CRC_STEREO_EN;
3699  
3700  /*
3701   * OPP_PIPE_CRC_STEREO_MODE enum
3702   */
3703  
3704  typedef enum OPP_PIPE_CRC_STEREO_MODE {
3705  OPP_PIPE_CRC_STEREO_MODE_LEFT            = 0x00000000,
3706  OPP_PIPE_CRC_STEREO_MODE_RIGHT           = 0x00000001,
3707  OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE = 0x00000002,
3708  OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE = 0x00000003,
3709  } OPP_PIPE_CRC_STEREO_MODE;
3710  
3711  /*******************************************************
3712   * OPP_TOP Enums
3713   *******************************************************/
3714  
3715  /*
3716   * OPP_ABM_DEBUG_BUS_SELECT_CONTROL enum
3717   */
3718  
3719  typedef enum OPP_ABM_DEBUG_BUS_SELECT_CONTROL {
3720  DEBUG_BUS_SELECT_ABM0                    = 0x00000000,
3721  DEBUG_BUS_SELECT_ABM1                    = 0x00000001,
3722  DEBUG_BUS_SELECT_ABM2                    = 0x00000002,
3723  DEBUG_BUS_SELECT_ABM3                    = 0x00000003,
3724  DEBUG_BUS_SELECT_ABM_RESERVED0           = 0x00000004,
3725  DEBUG_BUS_SELECT_ABM_RESERVED1           = 0x00000005,
3726  } OPP_ABM_DEBUG_BUS_SELECT_CONTROL;
3727  
3728  /*
3729   * OPP_DPG_DEBUG_BUS_SELECT_CONTROL enum
3730   */
3731  
3732  typedef enum OPP_DPG_DEBUG_BUS_SELECT_CONTROL {
3733  DEBUG_BUS_SELECT_DPG0                    = 0x00000000,
3734  DEBUG_BUS_SELECT_DPG1                    = 0x00000001,
3735  DEBUG_BUS_SELECT_DPG2                    = 0x00000002,
3736  DEBUG_BUS_SELECT_DPG3                    = 0x00000003,
3737  DEBUG_BUS_SELECT_DPG_RESERVED0           = 0x00000004,
3738  DEBUG_BUS_SELECT_DPG_RESERVED1           = 0x00000005,
3739  } OPP_DPG_DEBUG_BUS_SELECT_CONTROL;
3740  
3741  /*
3742   * OPP_FMT_DEBUG_BUS_SELECT_CONTROL enum
3743   */
3744  
3745  typedef enum OPP_FMT_DEBUG_BUS_SELECT_CONTROL {
3746  DEBUG_BUS_SELECT_FMT0                    = 0x00000000,
3747  DEBUG_BUS_SELECT_FMT1                    = 0x00000001,
3748  DEBUG_BUS_SELECT_FMT2                    = 0x00000002,
3749  DEBUG_BUS_SELECT_FMT3                    = 0x00000003,
3750  DEBUG_BUS_SELECT_FMT_RESERVED0           = 0x00000004,
3751  DEBUG_BUS_SELECT_FMT_RESERVED1           = 0x00000005,
3752  } OPP_FMT_DEBUG_BUS_SELECT_CONTROL;
3753  
3754  /*
3755   * OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL enum
3756   */
3757  
3758  typedef enum OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL {
3759  DEBUG_BUS_SELECT_OPPBUF0                 = 0x00000000,
3760  DEBUG_BUS_SELECT_OPPBUF1                 = 0x00000001,
3761  DEBUG_BUS_SELECT_OPPBUF2                 = 0x00000002,
3762  DEBUG_BUS_SELECT_OPPBUF3                 = 0x00000003,
3763  DEBUG_BUS_SELECT_OPPBUF_RESERVED0        = 0x00000004,
3764  DEBUG_BUS_SELECT_OPPBUF_RESERVED1        = 0x00000005,
3765  } OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL;
3766  
3767  /*
3768   * OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL enum
3769   */
3770  
3771  typedef enum OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL {
3772  DEBUG_BUS_SELECT_OPP_PIPE0               = 0x00000000,
3773  DEBUG_BUS_SELECT_OPP_PIPE1               = 0x00000001,
3774  DEBUG_BUS_SELECT_OPP_PIPE2               = 0x00000002,
3775  DEBUG_BUS_SELECT_OPP_PIPE3               = 0x00000003,
3776  DEBUG_BUS_SELECT_OPP_PIPE_RESERVED0      = 0x00000004,
3777  DEBUG_BUS_SELECT_OPP_PIPE_RESERVED1      = 0x00000005,
3778  } OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL;
3779  
3780  /*
3781   * OPP_TEST_CLK_SEL_CONTROL enum
3782   */
3783  
3784  typedef enum OPP_TEST_CLK_SEL_CONTROL {
3785  OPP_TEST_CLK_SEL_DISPCLK_P               = 0x00000000,
3786  OPP_TEST_CLK_SEL_DISPCLK_R               = 0x00000001,
3787  OPP_TEST_CLK_SEL_DISPCLK_ABM0            = 0x00000002,
3788  OPP_TEST_CLK_SEL_DISPCLK_ABM1            = 0x00000003,
3789  OPP_TEST_CLK_SEL_DISPCLK_ABM2            = 0x00000004,
3790  OPP_TEST_CLK_SEL_DISPCLK_ABM3            = 0x00000005,
3791  OPP_TEST_CLK_SEL_RESERVED0               = 0x00000006,
3792  OPP_TEST_CLK_SEL_RESERVED1               = 0x00000007,
3793  OPP_TEST_CLK_SEL_DISPCLK_OPP0            = 0x00000008,
3794  OPP_TEST_CLK_SEL_DISPCLK_OPP1            = 0x00000009,
3795  OPP_TEST_CLK_SEL_DISPCLK_OPP2            = 0x0000000a,
3796  OPP_TEST_CLK_SEL_DISPCLK_OPP3            = 0x0000000b,
3797  OPP_TEST_CLK_SEL_RESERVED2               = 0x0000000c,
3798  OPP_TEST_CLK_SEL_RESERVED3               = 0x0000000d,
3799  } OPP_TEST_CLK_SEL_CONTROL;
3800  
3801  /*
3802   * OPP_TOP_CLOCK_ENABLE_STATUS enum
3803   */
3804  
3805  typedef enum OPP_TOP_CLOCK_ENABLE_STATUS {
3806  OPP_TOP_CLOCK_DISABLED_STATUS            = 0x00000000,
3807  OPP_TOP_CLOCK_ENABLED_STATUS             = 0x00000001,
3808  } OPP_TOP_CLOCK_ENABLE_STATUS;
3809  
3810  /*
3811   * OPP_TOP_CLOCK_GATING_CONTROL enum
3812   */
3813  
3814  typedef enum OPP_TOP_CLOCK_GATING_CONTROL {
3815  OPP_TOP_CLOCK_GATING_ENABLED             = 0x00000000,
3816  OPP_TOP_CLOCK_GATING_DISABLED            = 0x00000001,
3817  } OPP_TOP_CLOCK_GATING_CONTROL;
3818  
3819  /*******************************************************
3820   * DSCRM Enums
3821   *******************************************************/
3822  
3823  /*
3824   * ENUM_DSCRM_EN enum
3825   */
3826  
3827  typedef enum ENUM_DSCRM_EN {
3828  ENUM_DSCRM_DISABLE                       = 0x00000000,
3829  ENUM_DSCRM_ENABLE                        = 0x00000001,
3830  } ENUM_DSCRM_EN;
3831  
3832  /*******************************************************
3833   * OTG Enums
3834   *******************************************************/
3835  
3836  /*
3837   * MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK enum
3838   */
3839  
3840  typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK {
3841  MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0x00000000,
3842  MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 0x00000001,
3843  } MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK;
3844  
3845  /*
3846   * MASTER_UPDATE_LOCK_SEL enum
3847   */
3848  
3849  typedef enum MASTER_UPDATE_LOCK_SEL {
3850  MASTER_UPDATE_LOCK_SEL_0                 = 0x00000000,
3851  MASTER_UPDATE_LOCK_SEL_1                 = 0x00000001,
3852  MASTER_UPDATE_LOCK_SEL_2                 = 0x00000002,
3853  MASTER_UPDATE_LOCK_SEL_3                 = 0x00000003,
3854  MASTER_UPDATE_LOCK_SEL_RESERVED4         = 0x00000004,
3855  MASTER_UPDATE_LOCK_SEL_RESERVED5         = 0x00000005,
3856  } MASTER_UPDATE_LOCK_SEL;
3857  
3858  /*
3859   * MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE enum
3860   */
3861  
3862  typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE {
3863  MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH = 0x00000000,
3864  MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP = 0x00000001,
3865  MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM = 0x00000002,
3866  MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED = 0x00000003,
3867  } MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE;
3868  
3869  /*
3870   * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN enum
3871   */
3872  
3873  typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN {
3874  OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE = 0x00000000,
3875  OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE = 0x00000001,
3876  } OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN;
3877  
3878  /*
3879   * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB enum
3880   */
3881  
3882  typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB {
3883  OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE = 0x00000000,
3884  OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE = 0x00000001,
3885  } OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB;
3886  
3887  /*
3888   * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR enum
3889   */
3890  
3891  typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR {
3892  OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE = 0x00000000,
3893  OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE = 0x00000001,
3894  } OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR;
3895  
3896  /*
3897   * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE enum
3898   */
3899  
3900  typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE {
3901  OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH = 0x00000000,
3902  OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE = 0x00000001,
3903  OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE = 0x00000002,
3904  OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED = 0x00000003,
3905  } OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE;
3906  
3907  /*
3908   * OTG_CONTROL_OTG_DISABLE_POINT_CNTL enum
3909   */
3910  
3911  typedef enum OTG_CONTROL_OTG_DISABLE_POINT_CNTL {
3912  OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE = 0x00000000,
3913  OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT = 0x00000001,
3914  OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_VUPDATE = 0x00000002,
3915  OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST = 0x00000003,
3916  } OTG_CONTROL_OTG_DISABLE_POINT_CNTL;
3917  
3918  /*
3919   * OTG_CONTROL_OTG_FIELD_NUMBER_CNTL enum
3920   */
3921  
3922  typedef enum OTG_CONTROL_OTG_FIELD_NUMBER_CNTL {
3923  OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL = 0x00000000,
3924  OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP     = 0x00000001,
3925  } OTG_CONTROL_OTG_FIELD_NUMBER_CNTL;
3926  
3927  /*
3928   * OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY enum
3929   */
3930  
3931  typedef enum OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY {
3932  OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE = 0x00000000,
3933  OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE = 0x00000001,
3934  } OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY;
3935  
3936  /*
3937   * OTG_CONTROL_OTG_MASTER_EN enum
3938   */
3939  
3940  typedef enum OTG_CONTROL_OTG_MASTER_EN {
3941  OTG_CONTROL_OTG_MASTER_EN_FALSE          = 0x00000000,
3942  OTG_CONTROL_OTG_MASTER_EN_TRUE           = 0x00000001,
3943  } OTG_CONTROL_OTG_MASTER_EN;
3944  
3945  /*
3946   * OTG_CONTROL_OTG_OUT_MUX enum
3947   */
3948  
3949  typedef enum OTG_CONTROL_OTG_OUT_MUX {
3950  OTG_CONTROL_OTG_OUT_MUX_0                = 0x00000000,
3951  OTG_CONTROL_OTG_OUT_MUX_1                = 0x00000001,
3952  OTG_CONTROL_OTG_OUT_MUX_2                = 0x00000002,
3953  } OTG_CONTROL_OTG_OUT_MUX;
3954  
3955  /*
3956   * OTG_CONTROL_OTG_START_POINT_CNTL enum
3957   */
3958  
3959  typedef enum OTG_CONTROL_OTG_START_POINT_CNTL {
3960  OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL  = 0x00000000,
3961  OTG_CONTROL_OTG_START_POINT_CNTL_DP      = 0x00000001,
3962  } OTG_CONTROL_OTG_START_POINT_CNTL;
3963  
3964  /*
3965   * OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN enum
3966   */
3967  
3968  typedef enum OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN {
3969  OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE = 0x00000000,
3970  OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE = 0x00000001,
3971  } OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN;
3972  
3973  /*
3974   * OTG_CRC_CNTL_OTG_CRC1_EN enum
3975   */
3976  
3977  typedef enum OTG_CRC_CNTL_OTG_CRC1_EN {
3978  OTG_CRC_CNTL_OTG_CRC1_EN_FALSE           = 0x00000000,
3979  OTG_CRC_CNTL_OTG_CRC1_EN_TRUE            = 0x00000001,
3980  } OTG_CRC_CNTL_OTG_CRC1_EN;
3981  
3982  /*
3983   * OTG_CRC_CNTL_OTG_CRC_CONT_EN enum
3984   */
3985  
3986  typedef enum OTG_CRC_CNTL_OTG_CRC_CONT_EN {
3987  OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE       = 0x00000000,
3988  OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE        = 0x00000001,
3989  } OTG_CRC_CNTL_OTG_CRC_CONT_EN;
3990  
3991  /*
3992   * OTG_CRC_CNTL_OTG_CRC_CONT_MODE enum
3993   */
3994  
3995  typedef enum OTG_CRC_CNTL_OTG_CRC_CONT_MODE {
3996  OTG_CRC_CNTL_OTG_CRC_CONT_MODE_RESET     = 0x00000000,
3997  OTG_CRC_CNTL_OTG_CRC_CONT_MODE_NORESET   = 0x00000001,
3998  } OTG_CRC_CNTL_OTG_CRC_CONT_MODE;
3999  
4000  /*
4001   * OTG_CRC_CNTL_OTG_CRC_EN enum
4002   */
4003  
4004  typedef enum OTG_CRC_CNTL_OTG_CRC_EN {
4005  OTG_CRC_CNTL_OTG_CRC_EN_FALSE            = 0x00000000,
4006  OTG_CRC_CNTL_OTG_CRC_EN_TRUE             = 0x00000001,
4007  } OTG_CRC_CNTL_OTG_CRC_EN;
4008  
4009  /*
4010   * OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE enum
4011   */
4012  
4013  typedef enum OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE {
4014  OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP  = 0x00000000,
4015  OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM = 0x00000001,
4016  OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM = 0x00000002,
4017  OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD = 0x00000003,
4018  } OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE;
4019  
4020  /*
4021   * OTG_CRC_CNTL_OTG_CRC_STEREO_MODE enum
4022   */
4023  
4024  typedef enum OTG_CRC_CNTL_OTG_CRC_STEREO_MODE {
4025  OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT    = 0x00000000,
4026  OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT   = 0x00000001,
4027  OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES = 0x00000002,
4028  OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS = 0x00000003,
4029  } OTG_CRC_CNTL_OTG_CRC_STEREO_MODE;
4030  
4031  /*
4032   * OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS enum
4033   */
4034  
4035  typedef enum OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS {
4036  OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE = 0x00000000,
4037  OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE = 0x00000001,
4038  } OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS;
4039  
4040  /*
4041   * OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT enum
4042   */
4043  
4044  typedef enum OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT {
4045  OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB     = 0x00000000,
4046  OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B    = 0x00000001,
4047  OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB    = 0x00000002,
4048  OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B   = 0x00000003,
4049  OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB     = 0x00000004,
4050  OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B    = 0x00000005,
4051  OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB    = 0x00000006,
4052  OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B   = 0x00000007,
4053  } OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT;
4054  
4055  /*
4056   * OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT enum
4057   */
4058  
4059  typedef enum OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT {
4060  OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB     = 0x00000000,
4061  OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B    = 0x00000001,
4062  OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB    = 0x00000002,
4063  OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B   = 0x00000003,
4064  OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB     = 0x00000004,
4065  OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B    = 0x00000005,
4066  OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB    = 0x00000006,
4067  OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B   = 0x00000007,
4068  } OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT;
4069  
4070  /*
4071   * OTG_DIG_UPDATE_VCOUNT_MODE enum
4072   */
4073  
4074  typedef enum OTG_DIG_UPDATE_VCOUNT_MODE {
4075  OTG_DIG_UPDATE_VCOUNT_0                  = 0x00000000,
4076  OTG_DIG_UPDATE_VCOUNT_1                  = 0x00000001,
4077  } OTG_DIG_UPDATE_VCOUNT_MODE;
4078  
4079  /*
4080   * OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE enum
4081   */
4082  
4083  typedef enum OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE {
4084  OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_0 = 0x00000000,
4085  OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_1 = 0x00000001,
4086  OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_2 = 0x00000002,
4087  OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_3 = 0x00000003,
4088  } OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE;
4089  
4090  /*
4091   * OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY enum
4092   */
4093  
4094  typedef enum OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY {
4095  OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE = 0x00000000,
4096  OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE = 0x00000001,
4097  } OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY;
4098  
4099  /*
4100   * OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME enum
4101   */
4102  
4103  typedef enum OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME {
4104  OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME = 0x00000000,
4105  OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME = 0x00000001,
4106  OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME = 0x00000002,
4107  OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME = 0x00000003,
4108  } OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME;
4109  
4110  /*
4111   * OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN enum
4112   */
4113  
4114  typedef enum OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN {
4115  OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE = 0x00000000,
4116  OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE = 0x00000001,
4117  } OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN;
4118  
4119  /*
4120   * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY enum
4121   */
4122  
4123  typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY {
4124  OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE = 0x00000000,
4125  OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE = 0x00000001,
4126  } OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY;
4127  
4128  /*
4129   * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY enum
4130   */
4131  
4132  typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY {
4133  OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE = 0x00000000,
4134  OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE = 0x00000001,
4135  } OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY;
4136  
4137  /*
4138   * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT enum
4139   */
4140  
4141  typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT {
4142  OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0 = 0x00000000,
4143  OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1 = 0x00000001,
4144  OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA = 0x00000002,
4145  OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB = 0x00000003,
4146  OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC = 0x00000004,
4147  OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD = 0x00000005,
4148  OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE = 0x00000006,
4149  OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF = 0x00000007,
4150  OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1 = 0x00000008,
4151  OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2 = 0x00000009,
4152  OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA = 0x0000000a,
4153  OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK = 0x0000000b,
4154  OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA = 0x0000000c,
4155  OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK = 0x0000000d,
4156  OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 0x0000000e,
4157  OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_RESERVED = 0x0000000f,
4158  OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK = 0x00000010,
4159  OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC = 0x00000011,
4160  OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA = 0x00000012,
4161  OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB = 0x00000013,
4162  } OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT;
4163  
4164  /*
4165   * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK enum
4166   */
4167  
4168  typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK {
4169  OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE = 0x00000000,
4170  OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE = 0x00000001,
4171  } OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK;
4172  
4173  /*
4174   * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR enum
4175   */
4176  
4177  typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR {
4178  OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE = 0x00000000,
4179  OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE = 0x00000001,
4180  } OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR;
4181  
4182  /*
4183   * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE enum
4184   */
4185  
4186  typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE {
4187  OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE = 0x00000000,
4188  OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT = 0x00000001,
4189  OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT = 0x00000002,
4190  OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED = 0x00000003,
4191  } OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE;
4192  
4193  /*
4194   * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL enum
4195   */
4196  
4197  typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL {
4198  OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE = 0x00000000,
4199  OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE = 0x00000001,
4200  } OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL;
4201  
4202  /*
4203   * OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL enum
4204   */
4205  
4206  typedef enum OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL {
4207  OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0 = 0x00000000,
4208  OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1 = 0x00000001,
4209  OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2 = 0x00000002,
4210  OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3 = 0x00000003,
4211  OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED4 = 0x00000004,
4212  OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED5 = 0x00000005,
4213  } OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL;
4214  
4215  /*
4216   * OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL enum
4217   */
4218  
4219  typedef enum OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL {
4220  DIG_UPDATE_EYE_SEL_BOTH                  = 0x00000000,
4221  DIG_UPDATE_EYE_SEL_LEFT                  = 0x00000001,
4222  DIG_UPDATE_EYE_SEL_RIGHT                 = 0x00000002,
4223  } OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL;
4224  
4225  /*
4226   * OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL enum
4227   */
4228  
4229  typedef enum OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL {
4230  DIG_UPDATE_FIELD_SEL_BOTH                = 0x00000000,
4231  DIG_UPDATE_FIELD_SEL_TOP                 = 0x00000001,
4232  DIG_UPDATE_FIELD_SEL_BOTTOM              = 0x00000002,
4233  DIG_UPDATE_FIELD_SEL_RESERVED            = 0x00000003,
4234  } OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL;
4235  
4236  /*
4237   * OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD enum
4238   */
4239  
4240  typedef enum OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD {
4241  MASTER_UPDATE_LOCK_DB_FIELD_BOTH         = 0x00000000,
4242  MASTER_UPDATE_LOCK_DB_FIELD_TOP          = 0x00000001,
4243  MASTER_UPDATE_LOCK_DB_FIELD_BOTTOM       = 0x00000002,
4244  MASTER_UPDATE_LOCK_DB_FIELD_RESERVED     = 0x00000003,
4245  } OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD;
4246  
4247  /*
4248   * OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL enum
4249   */
4250  
4251  typedef enum OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL {
4252  MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH    = 0x00000000,
4253  MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT    = 0x00000001,
4254  MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT   = 0x00000002,
4255  MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED = 0x00000003,
4256  } OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL;
4257  
4258  /*
4259   * OTG_GLOBAL_UPDATE_LOCK_EN enum
4260   */
4261  
4262  typedef enum OTG_GLOBAL_UPDATE_LOCK_EN {
4263  OTG_GLOBAL_UPDATE_LOCK_DISABLE           = 0x00000000,
4264  OTG_GLOBAL_UPDATE_LOCK_ENABLE            = 0x00000001,
4265  } OTG_GLOBAL_UPDATE_LOCK_EN;
4266  
4267  /*
4268   * OTG_GSL_MASTER_MODE enum
4269   */
4270  
4271  typedef enum OTG_GSL_MASTER_MODE {
4272  OTG_GSL_MASTER_MODE_0                    = 0x00000000,
4273  OTG_GSL_MASTER_MODE_1                    = 0x00000001,
4274  OTG_GSL_MASTER_MODE_2                    = 0x00000002,
4275  OTG_GSL_MASTER_MODE_3                    = 0x00000003,
4276  } OTG_GSL_MASTER_MODE;
4277  
4278  /*
4279   * OTG_HORZ_REPETITION_COUNT enum
4280   */
4281  
4282  typedef enum OTG_HORZ_REPETITION_COUNT {
4283  OTG_HORZ_REPETITION_COUNT_0              = 0x00000000,
4284  OTG_HORZ_REPETITION_COUNT_1              = 0x00000001,
4285  OTG_HORZ_REPETITION_COUNT_2              = 0x00000002,
4286  OTG_HORZ_REPETITION_COUNT_3              = 0x00000003,
4287  OTG_HORZ_REPETITION_COUNT_4              = 0x00000004,
4288  OTG_HORZ_REPETITION_COUNT_5              = 0x00000005,
4289  OTG_HORZ_REPETITION_COUNT_6              = 0x00000006,
4290  OTG_HORZ_REPETITION_COUNT_7              = 0x00000007,
4291  OTG_HORZ_REPETITION_COUNT_8              = 0x00000008,
4292  OTG_HORZ_REPETITION_COUNT_9              = 0x00000009,
4293  OTG_HORZ_REPETITION_COUNT_10             = 0x0000000a,
4294  OTG_HORZ_REPETITION_COUNT_11             = 0x0000000b,
4295  OTG_HORZ_REPETITION_COUNT_12             = 0x0000000c,
4296  OTG_HORZ_REPETITION_COUNT_13             = 0x0000000d,
4297  OTG_HORZ_REPETITION_COUNT_14             = 0x0000000e,
4298  OTG_HORZ_REPETITION_COUNT_15             = 0x0000000f,
4299  } OTG_HORZ_REPETITION_COUNT;
4300  
4301  /*
4302   * OTG_H_SYNC_A_POL enum
4303   */
4304  
4305  typedef enum OTG_H_SYNC_A_POL {
4306  OTG_H_SYNC_A_POL_HIGH                    = 0x00000000,
4307  OTG_H_SYNC_A_POL_LOW                     = 0x00000001,
4308  } OTG_H_SYNC_A_POL;
4309  
4310  /*
4311   * OTG_H_TIMING_DIV_MODE enum
4312   */
4313  
4314  typedef enum OTG_H_TIMING_DIV_MODE {
4315  OTG_H_TIMING_DIV_MODE_NO_DIV             = 0x00000000,
4316  OTG_H_TIMING_DIV_MODE_DIV_BY2            = 0x00000001,
4317  OTG_H_TIMING_DIV_MODE_RESERVED           = 0x00000002,
4318  OTG_H_TIMING_DIV_MODE_DIV_BY4            = 0x00000003,
4319  } OTG_H_TIMING_DIV_MODE;
4320  
4321  /*
4322   * OTG_H_TIMING_DIV_MODE_MANUAL enum
4323   */
4324  
4325  typedef enum OTG_H_TIMING_DIV_MODE_MANUAL {
4326  OTG_H_TIMING_DIV_MODE_AUTO               = 0x00000000,
4327  OTG_H_TIMING_DIV_MODE_NOAUTO             = 0x00000001,
4328  } OTG_H_TIMING_DIV_MODE_MANUAL;
4329  
4330  /*
4331   * OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE enum
4332   */
4333  
4334  typedef enum OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE {
4335  OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE = 0x00000000,
4336  OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE = 0x00000001,
4337  } OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE;
4338  
4339  /*
4340   * OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD enum
4341   */
4342  
4343  typedef enum OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD {
4344  OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT = 0x00000000,
4345  OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM = 0x00000001,
4346  OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP = 0x00000002,
4347  OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2 = 0x00000003,
4348  } OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD;
4349  
4350  /*
4351   * OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK enum
4352   */
4353  
4354  typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK {
4355  OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE = 0x00000000,
4356  OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE = 0x00000001,
4357  } OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK;
4358  
4359  /*
4360   * OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE enum
4361   */
4362  
4363  typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE {
4364  OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE = 0x00000000,
4365  OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE = 0x00000001,
4366  } OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE;
4367  
4368  /*
4369   * OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK enum
4370   */
4371  
4372  typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK {
4373  OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE = 0x00000000,
4374  OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE = 0x00000001,
4375  } OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK;
4376  
4377  /*
4378   * OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE enum
4379   */
4380  
4381  typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE {
4382  OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE = 0x00000000,
4383  OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE = 0x00000001,
4384  } OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE;
4385  
4386  /*
4387   * OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK enum
4388   */
4389  
4390  typedef enum OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK {
4391  OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE = 0x00000000,
4392  OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE = 0x00000001,
4393  } OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK;
4394  
4395  /*
4396   * OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE enum
4397   */
4398  
4399  typedef enum OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE {
4400  OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE = 0x00000000,
4401  OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE = 0x00000001,
4402  } OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE;
4403  
4404  /*
4405   * OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK enum
4406   */
4407  
4408  typedef enum OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK {
4409  OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE = 0x00000000,
4410  OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE = 0x00000001,
4411  } OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK;
4412  
4413  /*
4414   * OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE enum
4415   */
4416  
4417  typedef enum OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE {
4418  OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE = 0x00000000,
4419  OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE = 0x00000001,
4420  } OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE;
4421  
4422  /*
4423   * OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK enum
4424   */
4425  
4426  typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK {
4427  OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE = 0x00000000,
4428  OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE = 0x00000001,
4429  } OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK;
4430  
4431  /*
4432   * OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE enum
4433   */
4434  
4435  typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE {
4436  OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE = 0x00000000,
4437  OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE = 0x00000001,
4438  } OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE;
4439  
4440  /*
4441   * OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK enum
4442   */
4443  
4444  typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK {
4445  OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE = 0x00000000,
4446  OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE = 0x00000001,
4447  } OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK;
4448  
4449  /*
4450   * OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE enum
4451   */
4452  
4453  typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE {
4454  OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE = 0x00000000,
4455  OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE = 0x00000001,
4456  } OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE;
4457  
4458  /*
4459   * OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK enum
4460   */
4461  
4462  typedef enum OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK {
4463  OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE = 0x00000000,
4464  OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE = 0x00000001,
4465  } OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK;
4466  
4467  /*
4468   * OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE enum
4469   */
4470  
4471  typedef enum OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE {
4472  OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE = 0x00000000,
4473  OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE = 0x00000001,
4474  } OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE;
4475  
4476  /*
4477   * OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE enum
4478   */
4479  
4480  typedef enum OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE {
4481  OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE = 0x00000000,
4482  OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE = 0x00000001,
4483  } OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE;
4484  
4485  /*
4486   * OTG_MASTER_UPDATE_LOCK_DB_EN enum
4487   */
4488  
4489  typedef enum OTG_MASTER_UPDATE_LOCK_DB_EN {
4490  OTG_MASTER_UPDATE_LOCK_DISABLE           = 0x00000000,
4491  OTG_MASTER_UPDATE_LOCK_ENABLE            = 0x00000001,
4492  } OTG_MASTER_UPDATE_LOCK_DB_EN;
4493  
4494  /*
4495   * OTG_MASTER_UPDATE_LOCK_GSL_EN enum
4496   */
4497  
4498  typedef enum OTG_MASTER_UPDATE_LOCK_GSL_EN {
4499  OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE      = 0x00000000,
4500  OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE       = 0x00000001,
4501  } OTG_MASTER_UPDATE_LOCK_GSL_EN;
4502  
4503  /*
4504   * OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE enum
4505   */
4506  
4507  typedef enum OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE {
4508  OTG_MASTER_UPDATE_LOCK_VCOUNT_0          = 0x00000000,
4509  OTG_MASTER_UPDATE_LOCK_VCOUNT_1          = 0x00000001,
4510  } OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE;
4511  
4512  /*
4513   * OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL enum
4514   */
4515  
4516  typedef enum OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL {
4517  OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE = 0x00000000,
4518  OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA = 0x00000001,
4519  OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB = 0x00000002,
4520  OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED = 0x00000003,
4521  } OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL;
4522  
4523  /*
4524   * OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR enum
4525   */
4526  
4527  typedef enum OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR {
4528  OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE = 0x00000000,
4529  OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE = 0x00000001,
4530  } OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR;
4531  
4532  /*
4533   * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR enum
4534   */
4535  
4536  typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR {
4537  OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE = 0x00000000,
4538  OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE = 0x00000001,
4539  } OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR;
4540  
4541  /*
4542   * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE enum
4543   */
4544  
4545  typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE {
4546  OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE = 0x00000000,
4547  OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE = 0x00000001,
4548  } OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE;
4549  
4550  /*
4551   * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE enum
4552   */
4553  
4554  typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE {
4555  OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE = 0x00000000,
4556  OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE = 0x00000001,
4557  } OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE;
4558  
4559  /*
4560   * OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE enum
4561   */
4562  
4563  typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE {
4564  OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE = 0x00000000,
4565  OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE = 0x00000001,
4566  } OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE;
4567  
4568  /*
4569   * OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE enum
4570   */
4571  
4572  typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE {
4573  OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF = 0x00000000,
4574  OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON = 0x00000001,
4575  } OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE;
4576  
4577  /*
4578   * OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL enum
4579   */
4580  
4581  typedef enum OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL {
4582  OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_FALSE = 0x00000000,
4583  OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_TRUE = 0x00000001,
4584  } OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL;
4585  
4586  /*
4587   * OTG_STEREO_CONTROL_OTG_STEREO_EN enum
4588   */
4589  
4590  typedef enum OTG_STEREO_CONTROL_OTG_STEREO_EN {
4591  OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE   = 0x00000000,
4592  OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE    = 0x00000001,
4593  } OTG_STEREO_CONTROL_OTG_STEREO_EN;
4594  
4595  /*
4596   * OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY enum
4597   */
4598  
4599  typedef enum OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY {
4600  OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE = 0x00000000,
4601  OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE = 0x00000001,
4602  } OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY;
4603  
4604  /*
4605   * OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY enum
4606   */
4607  
4608  typedef enum OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY {
4609  OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE = 0x00000000,
4610  OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE = 0x00000001,
4611  } OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY;
4612  
4613  /*
4614   * OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE enum
4615   */
4616  
4617  typedef enum OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE {
4618  OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO = 0x00000000,
4619  OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT = 0x00000001,
4620  OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT = 0x00000002,
4621  OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED = 0x00000003,
4622  } OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE;
4623  
4624  /*
4625   * OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR enum
4626   */
4627  
4628  typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR {
4629  OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE     = 0x00000000,
4630  OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE      = 0x00000001,
4631  } OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR;
4632  
4633  /*
4634   * OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT enum
4635   */
4636  
4637  typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT {
4638  OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0 = 0x00000000,
4639  OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE = 0x00000001,
4640  OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA = 0x00000002,
4641  OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB = 0x00000003,
4642  OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA = 0x00000004,
4643  OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1 = 0x00000005,
4644  OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC = 0x00000006,
4645  OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD = 0x00000007,
4646  } OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT;
4647  
4648  /*
4649   * OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN enum
4650   */
4651  
4652  typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN {
4653  OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE = 0x00000000,
4654  OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE = 0x00000001,
4655  } OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN;
4656  
4657  /*
4658   * OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT enum
4659   */
4660  
4661  typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT {
4662  OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0 = 0x00000000,
4663  OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1 = 0x00000001,
4664  OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2 = 0x00000002,
4665  OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3 = 0x00000003,
4666  OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED4 = 0x00000004,
4667  OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED5 = 0x00000005,
4668  } OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT;
4669  
4670  /*
4671   * OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT enum
4672   */
4673  
4674  typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT {
4675  OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0 = 0x00000000,
4676  OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN = 0x00000001,
4677  OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN = 0x00000002,
4678  OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN = 0x00000003,
4679  OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN = 0x00000004,
4680  OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN = 0x00000005,
4681  OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN = 0x00000006,
4682  OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN = 0x00000007,
4683  OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN = 0x00000008,
4684  OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN = 0x00000009,
4685  OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN = 0x0000000a,
4686  OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1 = 0x0000000b,
4687  OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2 = 0x0000000c,
4688  OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN = 0x0000000d,
4689  OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_RESERVED14 = 0x0000000e,
4690  OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK = 0x0000000f,
4691  OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP = 0x00000010,
4692  OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING = 0x00000011,
4693  OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF = 0x00000012,
4694  OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC = 0x00000013,
4695  OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC = 0x00000014,
4696  OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 0x00000015,
4697  OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 0x00000016,
4698  OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1 = 0x00000017,
4699  OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING = 0x00000018,
4700  } OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT;
4701  
4702  /*
4703   * OTG_TRIGA_FALLING_EDGE_DETECT_CNTL enum
4704   */
4705  
4706  typedef enum OTG_TRIGA_FALLING_EDGE_DETECT_CNTL {
4707  OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0     = 0x00000000,
4708  OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1     = 0x00000001,
4709  OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2     = 0x00000002,
4710  OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3     = 0x00000003,
4711  } OTG_TRIGA_FALLING_EDGE_DETECT_CNTL;
4712  
4713  /*
4714   * OTG_TRIGA_FREQUENCY_SELECT enum
4715   */
4716  
4717  typedef enum OTG_TRIGA_FREQUENCY_SELECT {
4718  OTG_TRIGA_FREQUENCY_SELECT_0             = 0x00000000,
4719  OTG_TRIGA_FREQUENCY_SELECT_1             = 0x00000001,
4720  OTG_TRIGA_FREQUENCY_SELECT_2             = 0x00000002,
4721  OTG_TRIGA_FREQUENCY_SELECT_3             = 0x00000003,
4722  } OTG_TRIGA_FREQUENCY_SELECT;
4723  
4724  /*
4725   * OTG_TRIGA_RISING_EDGE_DETECT_CNTL enum
4726   */
4727  
4728  typedef enum OTG_TRIGA_RISING_EDGE_DETECT_CNTL {
4729  OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0      = 0x00000000,
4730  OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1      = 0x00000001,
4731  OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2      = 0x00000002,
4732  OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3      = 0x00000003,
4733  } OTG_TRIGA_RISING_EDGE_DETECT_CNTL;
4734  
4735  /*
4736   * OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR enum
4737   */
4738  
4739  typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR {
4740  OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE     = 0x00000000,
4741  OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE      = 0x00000001,
4742  } OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR;
4743  
4744  /*
4745   * OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT enum
4746   */
4747  
4748  typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT {
4749  OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0 = 0x00000000,
4750  OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE = 0x00000001,
4751  OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA = 0x00000002,
4752  OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB = 0x00000003,
4753  OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA = 0x00000004,
4754  OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1 = 0x00000005,
4755  OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC = 0x00000006,
4756  OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD = 0x00000007,
4757  } OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT;
4758  
4759  /*
4760   * OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN enum
4761   */
4762  
4763  typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN {
4764  OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE = 0x00000000,
4765  OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE = 0x00000001,
4766  } OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN;
4767  
4768  /*
4769   * OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT enum
4770   */
4771  
4772  typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT {
4773  OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0 = 0x00000000,
4774  OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1 = 0x00000001,
4775  OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2 = 0x00000002,
4776  OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3 = 0x00000003,
4777  OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED4 = 0x00000004,
4778  OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED5 = 0x00000005,
4779  } OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT;
4780  
4781  /*
4782   * OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT enum
4783   */
4784  
4785  typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT {
4786  OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0 = 0x00000000,
4787  OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN = 0x00000001,
4788  OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN = 0x00000002,
4789  OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN = 0x00000003,
4790  OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN = 0x00000004,
4791  OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN = 0x00000005,
4792  OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN = 0x00000006,
4793  OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN = 0x00000007,
4794  OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN = 0x00000008,
4795  OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN = 0x00000009,
4796  OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN = 0x0000000a,
4797  OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1 = 0x0000000b,
4798  OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2 = 0x0000000c,
4799  OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN = 0x0000000d,
4800  OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_RESERVED14 = 0x0000000e,
4801  OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK = 0x0000000f,
4802  OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP = 0x00000010,
4803  OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING = 0x00000011,
4804  OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF = 0x00000012,
4805  OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC = 0x00000013,
4806  OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC = 0x00000014,
4807  OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 0x00000015,
4808  OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 0x00000016,
4809  OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1 = 0x00000017,
4810  OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING = 0x00000018,
4811  } OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT;
4812  
4813  /*
4814   * OTG_TRIGB_FALLING_EDGE_DETECT_CNTL enum
4815   */
4816  
4817  typedef enum OTG_TRIGB_FALLING_EDGE_DETECT_CNTL {
4818  OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0     = 0x00000000,
4819  OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1     = 0x00000001,
4820  OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2     = 0x00000002,
4821  OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3     = 0x00000003,
4822  } OTG_TRIGB_FALLING_EDGE_DETECT_CNTL;
4823  
4824  /*
4825   * OTG_TRIGB_FREQUENCY_SELECT enum
4826   */
4827  
4828  typedef enum OTG_TRIGB_FREQUENCY_SELECT {
4829  OTG_TRIGB_FREQUENCY_SELECT_0             = 0x00000000,
4830  OTG_TRIGB_FREQUENCY_SELECT_1             = 0x00000001,
4831  OTG_TRIGB_FREQUENCY_SELECT_2             = 0x00000002,
4832  OTG_TRIGB_FREQUENCY_SELECT_3             = 0x00000003,
4833  } OTG_TRIGB_FREQUENCY_SELECT;
4834  
4835  /*
4836   * OTG_TRIGB_RISING_EDGE_DETECT_CNTL enum
4837   */
4838  
4839  typedef enum OTG_TRIGB_RISING_EDGE_DETECT_CNTL {
4840  OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0      = 0x00000000,
4841  OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1      = 0x00000001,
4842  OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2      = 0x00000002,
4843  OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3      = 0x00000003,
4844  } OTG_TRIGB_RISING_EDGE_DETECT_CNTL;
4845  
4846  /*
4847   * OTG_UPDATE_LOCK_OTG_UPDATE_LOCK enum
4848   */
4849  
4850  typedef enum OTG_UPDATE_LOCK_OTG_UPDATE_LOCK {
4851  OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE    = 0x00000000,
4852  OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE     = 0x00000001,
4853  } OTG_UPDATE_LOCK_OTG_UPDATE_LOCK;
4854  
4855  /*
4856   * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR enum
4857   */
4858  
4859  typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR {
4860  OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE = 0x00000000,
4861  OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE = 0x00000001,
4862  } OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR;
4863  
4864  /*
4865   * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE enum
4866   */
4867  
4868  typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE {
4869  OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE = 0x00000000,
4870  OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE = 0x00000001,
4871  } OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE;
4872  
4873  /*
4874   * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE enum
4875   */
4876  
4877  typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE {
4878  OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE = 0x00000000,
4879  OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE = 0x00000001,
4880  } OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE;
4881  
4882  /*
4883   * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY enum
4884   */
4885  
4886  typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY {
4887  OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE = 0x00000000,
4888  OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE = 0x00000001,
4889  } OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY;
4890  
4891  /*
4892   * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR enum
4893   */
4894  
4895  typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR {
4896  OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE = 0x00000000,
4897  OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE = 0x00000001,
4898  } OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR;
4899  
4900  /*
4901   * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE enum
4902   */
4903  
4904  typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE {
4905  OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE = 0x00000000,
4906  OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE = 0x00000001,
4907  } OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE;
4908  
4909  /*
4910   * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE enum
4911   */
4912  
4913  typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE {
4914  OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE = 0x00000000,
4915  OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE = 0x00000001,
4916  } OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE;
4917  
4918  /*
4919   * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR enum
4920   */
4921  
4922  typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR {
4923  OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE = 0x00000000,
4924  OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE = 0x00000001,
4925  } OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR;
4926  
4927  /*
4928   * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE enum
4929   */
4930  
4931  typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE {
4932  OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE = 0x00000000,
4933  OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE = 0x00000001,
4934  } OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE;
4935  
4936  /*
4937   * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE enum
4938   */
4939  
4940  typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE {
4941  OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE = 0x00000000,
4942  OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE = 0x00000001,
4943  } OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE;
4944  
4945  /*
4946   * OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE enum
4947   */
4948  
4949  typedef enum OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE {
4950  OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE = 0x00000000,
4951  OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA = 0x00000001,
4952  OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB = 0x00000002,
4953  OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED = 0x00000003,
4954  } OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE;
4955  
4956  /*
4957   * OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR enum
4958   */
4959  
4960  typedef enum OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR {
4961  OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE = 0x00000000,
4962  OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE = 0x00000001,
4963  } OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR;
4964  
4965  /*
4966   * OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR enum
4967   */
4968  
4969  typedef enum OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR {
4970  OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE = 0x00000000,
4971  OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE = 0x00000001,
4972  } OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR;
4973  
4974  /*
4975   * OTG_VUPDATE_BLOCK_DISABLE enum
4976   */
4977  
4978  typedef enum OTG_VUPDATE_BLOCK_DISABLE {
4979  OTG_VUPDATE_BLOCK_DISABLE_OFF            = 0x00000000,
4980  OTG_VUPDATE_BLOCK_DISABLE_ON             = 0x00000001,
4981  } OTG_VUPDATE_BLOCK_DISABLE;
4982  
4983  /*
4984   * OTG_V_SYNC_A_POL enum
4985   */
4986  
4987  typedef enum OTG_V_SYNC_A_POL {
4988  OTG_V_SYNC_A_POL_HIGH                    = 0x00000000,
4989  OTG_V_SYNC_A_POL_LOW                     = 0x00000001,
4990  } OTG_V_SYNC_A_POL;
4991  
4992  /*
4993   * OTG_V_SYNC_MODE enum
4994   */
4995  
4996  typedef enum OTG_V_SYNC_MODE {
4997  OTG_V_SYNC_MODE_HSYNC                    = 0x00000000,
4998  OTG_V_SYNC_MODE_HBLANK                   = 0x00000001,
4999  } OTG_V_SYNC_MODE;
5000  
5001  /*
5002   * OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD enum
5003   */
5004  
5005  typedef enum OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD {
5006  OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0 = 0x00000000,
5007  OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1 = 0x00000001,
5008  } OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD;
5009  
5010  /*
5011   * OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT enum
5012   */
5013  
5014  typedef enum OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT {
5015  OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE = 0x00000000,
5016  OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE = 0x00000001,
5017  } OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT;
5018  
5019  /*
5020   * OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC enum
5021   */
5022  
5023  typedef enum OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC {
5024  OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE = 0x00000000,
5025  OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE = 0x00000001,
5026  } OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC;
5027  
5028  /*
5029   * OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL enum
5030   */
5031  
5032  typedef enum OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL {
5033  OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE = 0x00000000,
5034  OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE = 0x00000001,
5035  } OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL;
5036  
5037  /*
5038   * OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL enum
5039   */
5040  
5041  typedef enum OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL {
5042  OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE = 0x00000000,
5043  OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE = 0x00000001,
5044  } OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL;
5045  
5046  /*
5047   * OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK enum
5048   */
5049  
5050  typedef enum OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK {
5051  OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_FALSE = 0x00000000,
5052  OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_TRUE = 0x00000001,
5053  } OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK;
5054  
5055  /*******************************************************
5056   * OPTC_MISC Enums
5057   *******************************************************/
5058  
5059  /*
5060   * OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL enum
5061   */
5062  
5063  typedef enum OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL {
5064  OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG0 = 0x00000000,
5065  OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG1 = 0x00000001,
5066  OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG2 = 0x00000002,
5067  OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG3 = 0x00000003,
5068  OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED4 = 0x00000004,
5069  OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED5 = 0x00000005,
5070  } OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL;
5071  
5072  /*******************************************************
5073   * DMCUB Enums
5074   *******************************************************/
5075  
5076  /*
5077   * DC_DMCUB_INT_TYPE enum
5078   */
5079  
5080  typedef enum DC_DMCUB_INT_TYPE {
5081  INT_LEVEL                                = 0x00000000,
5082  INT_PULSE                                = 0x00000001,
5083  } DC_DMCUB_INT_TYPE;
5084  
5085  /*
5086   * DC_DMCUB_TIMER_WINDOW enum
5087   */
5088  
5089  typedef enum DC_DMCUB_TIMER_WINDOW {
5090  BITS_31_0                                = 0x00000000,
5091  BITS_32_1                                = 0x00000001,
5092  BITS_33_2                                = 0x00000002,
5093  BITS_34_3                                = 0x00000003,
5094  BITS_35_4                                = 0x00000004,
5095  BITS_36_5                                = 0x00000005,
5096  BITS_37_6                                = 0x00000006,
5097  BITS_38_7                                = 0x00000007,
5098  } DC_DMCUB_TIMER_WINDOW;
5099  
5100  /*******************************************************
5101   * RBBMIF Enums
5102   *******************************************************/
5103  
5104  /*
5105   * INVALID_REG_ACCESS_TYPE enum
5106   */
5107  
5108  typedef enum INVALID_REG_ACCESS_TYPE {
5109  REG_UNALLOCATED_ADDR_WRITE               = 0x00000000,
5110  REG_UNALLOCATED_ADDR_READ                = 0x00000001,
5111  REG_VIRTUAL_WRITE                        = 0x00000002,
5112  REG_VIRTUAL_READ                         = 0x00000003,
5113  REG_SECURE_VIOLATE_WRITE                 = 0x00000004,
5114  REG_SECURE_VIOLATE_READ                  = 0x00000005,
5115  } INVALID_REG_ACCESS_TYPE;
5116  
5117  /*******************************************************
5118   * IHC Enums
5119   *******************************************************/
5120  
5121  /*
5122   * DMU_DC_GPU_TIMER_READ_SELECT enum
5123   */
5124  
5125  typedef enum DMU_DC_GPU_TIMER_READ_SELECT {
5126  DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0 = 0x00000000,
5127  DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1 = 0x00000001,
5128  DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2 = 0x00000002,
5129  DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3 = 0x00000003,
5130  DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4 = 0x00000004,
5131  DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5 = 0x00000005,
5132  DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6 = 0x00000006,
5133  DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7 = 0x00000007,
5134  RESERVED_8                               = 0x00000008,
5135  RESERVED_9                               = 0x00000009,
5136  RESERVED_10                              = 0x0000000a,
5137  RESERVED_11                              = 0x0000000b,
5138  DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12 = 0x0000000c,
5139  DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13 = 0x0000000d,
5140  DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14 = 0x0000000e,
5141  DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15 = 0x0000000f,
5142  DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16 = 0x00000010,
5143  DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17 = 0x00000011,
5144  DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18 = 0x00000012,
5145  DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19 = 0x00000013,
5146  RESERVED_20                              = 0x00000014,
5147  RESERVED_21                              = 0x00000015,
5148  RESERVED_22                              = 0x00000016,
5149  RESERVED_23                              = 0x00000017,
5150  DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24 = 0x00000018,
5151  DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25 = 0x00000019,
5152  DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26 = 0x0000001a,
5153  DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27 = 0x0000001b,
5154  DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28 = 0x0000001c,
5155  DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29 = 0x0000001d,
5156  DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30 = 0x0000001e,
5157  DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31 = 0x0000001f,
5158  RESERVED_32                              = 0x00000020,
5159  RESERVED_33                              = 0x00000021,
5160  RESERVED_34                              = 0x00000022,
5161  RESERVED_35                              = 0x00000023,
5162  DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36 = 0x00000024,
5163  DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37 = 0x00000025,
5164  DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38 = 0x00000026,
5165  DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39 = 0x00000027,
5166  DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40 = 0x00000028,
5167  DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41 = 0x00000029,
5168  DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42 = 0x0000002a,
5169  DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43 = 0x0000002b,
5170  RESERVED_44                              = 0x0000002c,
5171  RESERVED_45                              = 0x0000002d,
5172  RESERVED_46                              = 0x0000002e,
5173  RESERVED_47                              = 0x0000002f,
5174  DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48 = 0x00000030,
5175  DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49 = 0x00000031,
5176  DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50 = 0x00000032,
5177  DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51 = 0x00000033,
5178  DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52 = 0x00000034,
5179  DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53 = 0x00000035,
5180  DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54 = 0x00000036,
5181  DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55 = 0x00000037,
5182  RESERVED_56                              = 0x00000038,
5183  RESERVED_57                              = 0x00000039,
5184  RESERVED_58                              = 0x0000003a,
5185  RESERVED_59                              = 0x0000003b,
5186  RESERVED_60                              = 0x0000003c,
5187  RESERVED_61                              = 0x0000003d,
5188  RESERVED_62                              = 0x0000003e,
5189  RESERVED_63                              = 0x0000003f,
5190  DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64 = 0x00000040,
5191  DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65 = 0x00000041,
5192  DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66 = 0x00000042,
5193  DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67 = 0x00000043,
5194  DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68 = 0x00000044,
5195  DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69 = 0x00000045,
5196  DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70 = 0x00000046,
5197  DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71 = 0x00000047,
5198  RESERVED_72                              = 0x00000048,
5199  RESERVED_73                              = 0x00000049,
5200  RESERVED_74                              = 0x0000004a,
5201  RESERVED_75                              = 0x0000004b,
5202  DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76 = 0x0000004c,
5203  DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77 = 0x0000004d,
5204  DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78 = 0x0000004e,
5205  DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79 = 0x0000004f,
5206  DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80 = 0x00000050,
5207  DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81 = 0x00000051,
5208  DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82 = 0x00000052,
5209  DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83 = 0x00000053,
5210  RESERVED_84                              = 0x00000054,
5211  RESERVED_85                              = 0x00000055,
5212  RESERVED_86                              = 0x00000056,
5213  RESERVED_87                              = 0x00000057,
5214  RESERVED_88                              = 0x00000058,
5215  RESERVED_89                              = 0x00000059,
5216  RESERVED_90                              = 0x0000005a,
5217  RESERVED_91                              = 0x0000005b,
5218  } DMU_DC_GPU_TIMER_READ_SELECT;
5219  
5220  /*
5221   * DMU_DC_GPU_TIMER_START_POSITION enum
5222   */
5223  
5224  typedef enum DMU_DC_GPU_TIMER_START_POSITION {
5225  DMU_GPU_TIMER_START_0_END_27             = 0x00000000,
5226  DMU_GPU_TIMER_START_1_END_28             = 0x00000001,
5227  DMU_GPU_TIMER_START_2_END_29             = 0x00000002,
5228  DMU_GPU_TIMER_START_3_END_30             = 0x00000003,
5229  DMU_GPU_TIMER_START_4_END_31             = 0x00000004,
5230  DMU_GPU_TIMER_START_6_END_33             = 0x00000005,
5231  DMU_GPU_TIMER_START_8_END_35             = 0x00000006,
5232  DMU_GPU_TIMER_START_10_END_37            = 0x00000007,
5233  } DMU_DC_GPU_TIMER_START_POSITION;
5234  
5235  /*
5236   * IHC_INTERRUPT_DEST enum
5237   */
5238  
5239  typedef enum IHC_INTERRUPT_DEST {
5240  INTERRUPT_SENT_TO_IH                     = 0x00000000,
5241  INTERRUPT_SENT_TO_DMCUB                  = 0x00000001,
5242  } IHC_INTERRUPT_DEST;
5243  
5244  /*
5245   * IHC_INTERRUPT_LINE_STATUS enum
5246   */
5247  
5248  typedef enum IHC_INTERRUPT_LINE_STATUS {
5249  INTERRUPT_LINE_NOT_ASSERTED              = 0x00000000,
5250  INTERRUPT_LINE_ASSERTED                  = 0x00000001,
5251  } IHC_INTERRUPT_LINE_STATUS;
5252  
5253  /*******************************************************
5254   * DMU_MISC Enums
5255   *******************************************************/
5256  
5257  /*
5258   * DC_SMU_INTERRUPT_ENABLE enum
5259   */
5260  
5261  typedef enum DC_SMU_INTERRUPT_ENABLE {
5262  DISABLE_THE_INTERRUPT                    = 0x00000000,
5263  ENABLE_THE_INTERRUPT                     = 0x00000001,
5264  } DC_SMU_INTERRUPT_ENABLE;
5265  
5266  /*
5267   * DMU_CLOCK_ON enum
5268   */
5269  
5270  typedef enum DMU_CLOCK_ON {
5271  DMU_CLOCK_STATUS_ON                      = 0x00000000,
5272  DMU_CLOCK_STATUS_OFF                     = 0x00000001,
5273  } DMU_CLOCK_ON;
5274  
5275  /*
5276   * SMU_INTR enum
5277   */
5278  
5279  typedef enum SMU_INTR {
5280  SMU_MSG_INTR_NOOP                        = 0x00000000,
5281  SET_SMU_MSG_INTR                         = 0x00000001,
5282  } SMU_INTR;
5283  
5284  /*******************************************************
5285   * DCCG Enums
5286   *******************************************************/
5287  
5288  /*
5289   * ALLOW_SR_ON_TRANS_REQ enum
5290   */
5291  
5292  typedef enum ALLOW_SR_ON_TRANS_REQ {
5293  ALLOW_SR_ON_TRANS_REQ_ENABLE             = 0x00000000,
5294  ALLOW_SR_ON_TRANS_REQ_DISABLE            = 0x00000001,
5295  } ALLOW_SR_ON_TRANS_REQ;
5296  
5297  /*
5298   * AMCLOCK_ENABLE enum
5299   */
5300  
5301  typedef enum AMCLOCK_ENABLE {
5302  ENABLE_AMCLK0                            = 0x00000000,
5303  ENABLE_AMCLK1                            = 0x00000001,
5304  } AMCLOCK_ENABLE;
5305  
5306  /*
5307   * CLEAR_SMU_INTR enum
5308   */
5309  
5310  typedef enum CLEAR_SMU_INTR {
5311  SMU_INTR_STATUS_NOOP                     = 0x00000000,
5312  SMU_INTR_STATUS_CLEAR                    = 0x00000001,
5313  } CLEAR_SMU_INTR;
5314  
5315  /*
5316   * CLOCK_BRANCH_SOFT_RESET enum
5317   */
5318  
5319  typedef enum CLOCK_BRANCH_SOFT_RESET {
5320  CLOCK_BRANCH_SOFT_RESET_NOOP             = 0x00000000,
5321  CLOCK_BRANCH_SOFT_RESET_FORCE            = 0x00000001,
5322  } CLOCK_BRANCH_SOFT_RESET;
5323  
5324  /*
5325   * DCCG_AUDIO_DTO0_SOURCE_SEL enum
5326   */
5327  
5328  typedef enum DCCG_AUDIO_DTO0_SOURCE_SEL {
5329  DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0          = 0x00000000,
5330  DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1          = 0x00000001,
5331  DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2          = 0x00000002,
5332  DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3          = 0x00000003,
5333  DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED      = 0x00000004,
5334  } DCCG_AUDIO_DTO0_SOURCE_SEL;
5335  
5336  /*
5337   * DCCG_AUDIO_DTO2_SOURCE_SEL enum
5338   */
5339  
5340  typedef enum DCCG_AUDIO_DTO2_SOURCE_SEL {
5341  DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0        = 0x00000000,
5342  DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0_DIV2   = 0x00000001,
5343  } DCCG_AUDIO_DTO2_SOURCE_SEL;
5344  
5345  /*
5346   * DCCG_AUDIO_DTO_SEL enum
5347   */
5348  
5349  typedef enum DCCG_AUDIO_DTO_SEL {
5350  DCCG_AUDIO_DTO_SEL_AUDIO_DTO0            = 0x00000000,
5351  DCCG_AUDIO_DTO_SEL_AUDIO_DTO1            = 0x00000001,
5352  DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO          = 0x00000002,
5353  DCCG_AUDIO_DTO_SEL_AUDIO_DTO_DTBCLK      = 0x00000003,
5354  } DCCG_AUDIO_DTO_SEL;
5355  
5356  /*
5357   * DCCG_AUDIO_DTO_USE_512FBR_DTO enum
5358   */
5359  
5360  typedef enum DCCG_AUDIO_DTO_USE_512FBR_DTO {
5361  DCCG_AUDIO_DTO_USE_128FBR_FOR_DP         = 0x00000000,
5362  DCCG_AUDIO_DTO_USE_512FBR_FOR_DP         = 0x00000001,
5363  } DCCG_AUDIO_DTO_USE_512FBR_DTO;
5364  
5365  /*
5366   * DCCG_DBG_BLOCK_SEL enum
5367   */
5368  
5369  typedef enum DCCG_DBG_BLOCK_SEL {
5370  DCCG_DBG_BLOCK_SEL_DCCG                  = 0x00000000,
5371  DCCG_DBG_BLOCK_SEL_PMON                  = 0x00000001,
5372  DCCG_DBG_BLOCK_SEL_PMON2                 = 0x00000002,
5373  } DCCG_DBG_BLOCK_SEL;
5374  
5375  /*
5376   * DCCG_DBG_EN enum
5377   */
5378  
5379  typedef enum DCCG_DBG_EN {
5380  DCCG_DBG_EN_DISABLE                      = 0x00000000,
5381  DCCG_DBG_EN_ENABLE                       = 0x00000001,
5382  } DCCG_DBG_EN;
5383  
5384  /*
5385   * DCCG_DEEP_COLOR_CNTL enum
5386   */
5387  
5388  typedef enum DCCG_DEEP_COLOR_CNTL {
5389  DCCG_DEEP_COLOR_DTO_DISABLE              = 0x00000000,
5390  DCCG_DEEP_COLOR_DTO_5_4_RATIO            = 0x00000001,
5391  DCCG_DEEP_COLOR_DTO_3_2_RATIO            = 0x00000002,
5392  DCCG_DEEP_COLOR_DTO_2_1_RATIO            = 0x00000003,
5393  } DCCG_DEEP_COLOR_CNTL;
5394  
5395  /*
5396   * DCCG_FIFO_ERRDET_OVR_EN enum
5397   */
5398  
5399  typedef enum DCCG_FIFO_ERRDET_OVR_EN {
5400  DCCG_FIFO_ERRDET_OVR_DISABLE             = 0x00000000,
5401  DCCG_FIFO_ERRDET_OVR_ENABLE              = 0x00000001,
5402  } DCCG_FIFO_ERRDET_OVR_EN;
5403  
5404  /*
5405   * DCCG_FIFO_ERRDET_RESET enum
5406   */
5407  
5408  typedef enum DCCG_FIFO_ERRDET_RESET {
5409  DCCG_FIFO_ERRDET_RESET_NOOP              = 0x00000000,
5410  DCCG_FIFO_ERRDET_RESET_FORCE             = 0x00000001,
5411  } DCCG_FIFO_ERRDET_RESET;
5412  
5413  /*
5414   * DCCG_FIFO_ERRDET_STATE enum
5415   */
5416  
5417  typedef enum DCCG_FIFO_ERRDET_STATE {
5418  DCCG_FIFO_ERRDET_STATE_CALIBRATION       = 0x00000000,
5419  DCCG_FIFO_ERRDET_STATE_DETECTION         = 0x00000001,
5420  } DCCG_FIFO_ERRDET_STATE;
5421  
5422  /*
5423   * DCCG_PERF_MODE_HSYNC enum
5424   */
5425  
5426  typedef enum DCCG_PERF_MODE_HSYNC {
5427  DCCG_PERF_MODE_HSYNC_NOOP                = 0x00000000,
5428  DCCG_PERF_MODE_HSYNC_START               = 0x00000001,
5429  } DCCG_PERF_MODE_HSYNC;
5430  
5431  /*
5432   * DCCG_PERF_MODE_VSYNC enum
5433   */
5434  
5435  typedef enum DCCG_PERF_MODE_VSYNC {
5436  DCCG_PERF_MODE_VSYNC_NOOP                = 0x00000000,
5437  DCCG_PERF_MODE_VSYNC_START               = 0x00000001,
5438  } DCCG_PERF_MODE_VSYNC;
5439  
5440  /*
5441   * DCCG_PERF_OTG_SELECT enum
5442   */
5443  
5444  typedef enum DCCG_PERF_OTG_SELECT {
5445  DCCG_PERF_SEL_OTG0                       = 0x00000000,
5446  DCCG_PERF_SEL_OTG1                       = 0x00000001,
5447  DCCG_PERF_SEL_OTG2                       = 0x00000002,
5448  DCCG_PERF_SEL_OTG3                       = 0x00000003,
5449  DCCG_PERF_SEL_RESERVED                   = 0x00000004,
5450  } DCCG_PERF_OTG_SELECT;
5451  
5452  /*
5453   * DCCG_PERF_RUN enum
5454   */
5455  
5456  typedef enum DCCG_PERF_RUN {
5457  DCCG_PERF_RUN_NOOP                       = 0x00000000,
5458  DCCG_PERF_RUN_START                      = 0x00000001,
5459  } DCCG_PERF_RUN;
5460  
5461  /*
5462   * DC_MEM_GLOBAL_PWR_REQ_DIS enum
5463   */
5464  
5465  typedef enum DC_MEM_GLOBAL_PWR_REQ_DIS {
5466  DC_MEM_GLOBAL_PWR_REQ_ENABLE             = 0x00000000,
5467  DC_MEM_GLOBAL_PWR_REQ_DISABLE            = 0x00000001,
5468  } DC_MEM_GLOBAL_PWR_REQ_DIS;
5469  
5470  /*
5471   * DIO_FIFO_ERROR enum
5472   */
5473  
5474  typedef enum DIO_FIFO_ERROR {
5475  DIO_FIFO_ERROR_00                        = 0x00000000,
5476  DIO_FIFO_ERROR_01                        = 0x00000001,
5477  DIO_FIFO_ERROR_10                        = 0x00000002,
5478  DIO_FIFO_ERROR_11                        = 0x00000003,
5479  } DIO_FIFO_ERROR;
5480  
5481  /*
5482   * DISABLE_CLOCK_GATING enum
5483   */
5484  
5485  typedef enum DISABLE_CLOCK_GATING {
5486  CLOCK_GATING_ENABLED                     = 0x00000000,
5487  CLOCK_GATING_DISABLED                    = 0x00000001,
5488  } DISABLE_CLOCK_GATING;
5489  
5490  /*
5491   * DISABLE_CLOCK_GATING_IN_DCO enum
5492   */
5493  
5494  typedef enum DISABLE_CLOCK_GATING_IN_DCO {
5495  CLOCK_GATING_ENABLED_IN_DCO              = 0x00000000,
5496  CLOCK_GATING_DISABLED_IN_DCO             = 0x00000001,
5497  } DISABLE_CLOCK_GATING_IN_DCO;
5498  
5499  /*
5500   * DISPCLK_CHG_FWD_CORR_DISABLE enum
5501   */
5502  
5503  typedef enum DISPCLK_CHG_FWD_CORR_DISABLE {
5504  DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING = 0x00000000,
5505  DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING = 0x00000001,
5506  } DISPCLK_CHG_FWD_CORR_DISABLE;
5507  
5508  /*
5509   * DISPCLK_FREQ_RAMP_DONE enum
5510   */
5511  
5512  typedef enum DISPCLK_FREQ_RAMP_DONE {
5513  DISPCLK_FREQ_RAMP_IN_PROGRESS            = 0x00000000,
5514  DISPCLK_FREQ_RAMP_COMPLETED              = 0x00000001,
5515  } DISPCLK_FREQ_RAMP_DONE;
5516  
5517  /*
5518   * DPREFCLK_SRC_SEL enum
5519   */
5520  
5521  typedef enum DPREFCLK_SRC_SEL {
5522  DPREFCLK_SRC_SEL_CK                      = 0x00000000,
5523  DPREFCLK_SRC_SEL_P0PLL                   = 0x00000001,
5524  DPREFCLK_SRC_SEL_P1PLL                   = 0x00000002,
5525  DPREFCLK_SRC_SEL_P2PLL                   = 0x00000003,
5526  } DPREFCLK_SRC_SEL;
5527  
5528  /*
5529   * DP_DTO_DS_DISABLE enum
5530   */
5531  
5532  typedef enum DP_DTO_DS_DISABLE {
5533  DP_DTO_DESPREAD_DISABLE                  = 0x00000000,
5534  DP_DTO_DESPREAD_ENABLE                   = 0x00000001,
5535  } DP_DTO_DS_DISABLE;
5536  
5537  /*
5538   * DS_HW_CAL_ENABLE enum
5539   */
5540  
5541  typedef enum DS_HW_CAL_ENABLE {
5542  DS_HW_CAL_DIS                            = 0x00000000,
5543  DS_HW_CAL_EN                             = 0x00000001,
5544  } DS_HW_CAL_ENABLE;
5545  
5546  /*
5547   * DS_JITTER_COUNT_SRC_SEL enum
5548   */
5549  
5550  typedef enum DS_JITTER_COUNT_SRC_SEL {
5551  DS_JITTER_COUNT_SRC_SEL0                 = 0x00000000,
5552  DS_JITTER_COUNT_SRC_SEL1                 = 0x00000001,
5553  } DS_JITTER_COUNT_SRC_SEL;
5554  
5555  /*
5556   * DS_REF_SRC enum
5557   */
5558  
5559  typedef enum DS_REF_SRC {
5560  DS_REF_IS_XTALIN                         = 0x00000000,
5561  DS_REF_IS_EXT_GENLOCK                    = 0x00000001,
5562  DS_REF_IS_PCIE                           = 0x00000002,
5563  } DS_REF_SRC;
5564  
5565  /*
5566   * DVOACLKC_IN_PHASE enum
5567   */
5568  
5569  typedef enum DVOACLKC_IN_PHASE {
5570  DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x00000000,
5571  DVOACLKC_IN_PHASE_WITH_PCLK_DVO          = 0x00000001,
5572  } DVOACLKC_IN_PHASE;
5573  
5574  /*
5575   * DVOACLKC_MVP_IN_PHASE enum
5576   */
5577  
5578  typedef enum DVOACLKC_MVP_IN_PHASE {
5579  DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x00000000,
5580  DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO      = 0x00000001,
5581  } DVOACLKC_MVP_IN_PHASE;
5582  
5583  /*
5584   * DVOACLKC_MVP_SKEW_PHASE_OVERRIDE enum
5585   */
5586  
5587  typedef enum DVOACLKC_MVP_SKEW_PHASE_OVERRIDE {
5588  DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE = 0x00000000,
5589  DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE  = 0x00000001,
5590  } DVOACLKC_MVP_SKEW_PHASE_OVERRIDE;
5591  
5592  /*
5593   * DVOACLKD_IN_PHASE enum
5594   */
5595  
5596  typedef enum DVOACLKD_IN_PHASE {
5597  DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x00000000,
5598  DVOACLKD_IN_PHASE_WITH_PCLK_DVO          = 0x00000001,
5599  } DVOACLKD_IN_PHASE;
5600  
5601  /*
5602   * DVOACLK_COARSE_SKEW_CNTL enum
5603   */
5604  
5605  typedef enum DVOACLK_COARSE_SKEW_CNTL {
5606  DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT   = 0x00000000,
5607  DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP    = 0x00000001,
5608  DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS   = 0x00000002,
5609  DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS   = 0x00000003,
5610  DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS   = 0x00000004,
5611  DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS   = 0x00000005,
5612  DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS   = 0x00000006,
5613  DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS   = 0x00000007,
5614  DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS   = 0x00000008,
5615  DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS   = 0x00000009,
5616  DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS  = 0x0000000a,
5617  DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS  = 0x0000000b,
5618  DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS  = 0x0000000c,
5619  DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS  = 0x0000000d,
5620  DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS  = 0x0000000e,
5621  DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS  = 0x0000000f,
5622  DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP    = 0x00000010,
5623  DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS   = 0x00000011,
5624  DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS   = 0x00000012,
5625  DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS   = 0x00000013,
5626  DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS   = 0x00000014,
5627  DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS   = 0x00000015,
5628  DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS   = 0x00000016,
5629  DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS   = 0x00000017,
5630  DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS   = 0x00000018,
5631  DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS  = 0x00000019,
5632  DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS  = 0x0000001a,
5633  DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS  = 0x0000001b,
5634  DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS  = 0x0000001c,
5635  DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS  = 0x0000001d,
5636  DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS  = 0x0000001e,
5637  } DVOACLK_COARSE_SKEW_CNTL;
5638  
5639  /*
5640   * DVOACLK_FINE_SKEW_CNTL enum
5641   */
5642  
5643  typedef enum DVOACLK_FINE_SKEW_CNTL {
5644  DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT     = 0x00000000,
5645  DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP      = 0x00000001,
5646  DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS     = 0x00000002,
5647  DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS     = 0x00000003,
5648  DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP      = 0x00000004,
5649  DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS     = 0x00000005,
5650  DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS     = 0x00000006,
5651  DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS     = 0x00000007,
5652  } DVOACLK_FINE_SKEW_CNTL;
5653  
5654  /*
5655   * DVO_ENABLE_RST enum
5656   */
5657  
5658  typedef enum DVO_ENABLE_RST {
5659  DVO_ENABLE_RST_DISABLE                   = 0x00000000,
5660  DVO_ENABLE_RST_ENABLE                    = 0x00000001,
5661  } DVO_ENABLE_RST;
5662  
5663  /*
5664   * ENABLE enum
5665   */
5666  
5667  typedef enum ENABLE {
5668  DISABLE_THE_FEATURE                      = 0x00000000,
5669  ENABLE_THE_FEATURE                       = 0x00000001,
5670  } ENABLE;
5671  
5672  /*
5673   * ENABLE_CLOCK enum
5674   */
5675  
5676  typedef enum ENABLE_CLOCK {
5677  ENABLE_THE_REFCLK                        = 0x00000000,
5678  ENABLE_THE_FUNC_CLOCK                    = 0x00000001,
5679  } ENABLE_CLOCK;
5680  
5681  /*
5682   * FORCE_DISABLE_CLOCK enum
5683   */
5684  
5685  typedef enum FORCE_DISABLE_CLOCK {
5686  NOT_FORCE_THE_CLOCK_DISABLED             = 0x00000000,
5687  FORCE_THE_CLOCK_DISABLED                 = 0x00000001,
5688  } FORCE_DISABLE_CLOCK;
5689  
5690  /*
5691   * HDMICHARCLK_SRC_SEL enum
5692   */
5693  
5694  typedef enum HDMICHARCLK_SRC_SEL {
5695  HDMICHARCLK_SRC_SEL_UNIPHYA              = 0x00000000,
5696  HDMICHARCLK_SRC_SEL_UNIPHYB              = 0x00000001,
5697  HDMICHARCLK_SRC_SEL_UNIPHYC              = 0x00000002,
5698  HDMICHARCLK_SRC_SEL_UNIPHYD              = 0x00000003,
5699  HDMICHARCLK_SRC_SEL_UNIPHYE              = 0x00000004,
5700  HDMICHARCLK_SRC_SEL_SRC_RESERVED         = 0x00000005,
5701  } HDMICHARCLK_SRC_SEL;
5702  
5703  /*
5704   * HDMISTREAMCLK_DTO_FORCE_DIS enum
5705   */
5706  
5707  typedef enum HDMISTREAMCLK_DTO_FORCE_DIS {
5708  DTO_FORCE_NO_BYPASS                      = 0x00000000,
5709  DTO_FORCE_BYPASS                         = 0x00000001,
5710  } HDMISTREAMCLK_DTO_FORCE_DIS;
5711  
5712  /*
5713   * HDMISTREAMCLK_SRC_SEL enum
5714   */
5715  
5716  typedef enum HDMISTREAMCLK_SRC_SEL {
5717  SEL_REFCLK0                              = 0x00000000,
5718  SEL_DTBCLK0                              = 0x00000001,
5719  SEL_DTBCLK1                              = 0x00000002,
5720  } HDMISTREAMCLK_SRC_SEL;
5721  
5722  /*
5723   * JITTER_REMOVE_DISABLE enum
5724   */
5725  
5726  typedef enum JITTER_REMOVE_DISABLE {
5727  ENABLE_JITTER_REMOVAL                    = 0x00000000,
5728  DISABLE_JITTER_REMOVAL                   = 0x00000001,
5729  } JITTER_REMOVE_DISABLE;
5730  
5731  /*
5732   * MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL enum
5733   */
5734  
5735  typedef enum MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL {
5736  MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN    = 0x00000000,
5737  MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 0x00000001,
5738  } MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL;
5739  
5740  /*
5741   * MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL enum
5742   */
5743  
5744  typedef enum MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL {
5745  MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN    = 0x00000000,
5746  MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 0x00000001,
5747  } MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL;
5748  
5749  /*
5750   * OTG_ADD_PIXEL enum
5751   */
5752  
5753  typedef enum OTG_ADD_PIXEL {
5754  OTG_ADD_PIXEL_NOOP                       = 0x00000000,
5755  OTG_ADD_PIXEL_FORCE                      = 0x00000001,
5756  } OTG_ADD_PIXEL;
5757  
5758  /*
5759   * OTG_DROP_PIXEL enum
5760   */
5761  
5762  typedef enum OTG_DROP_PIXEL {
5763  OTG_DROP_PIXEL_NOOP                      = 0x00000000,
5764  OTG_DROP_PIXEL_FORCE                     = 0x00000001,
5765  } OTG_DROP_PIXEL;
5766  
5767  /*
5768   * PHYSYMCLK_FORCE_EN enum
5769   */
5770  
5771  typedef enum PHYSYMCLK_FORCE_EN {
5772  PHYSYMCLK_FORCE_EN_DISABLE               = 0x00000000,
5773  PHYSYMCLK_FORCE_EN_ENABLE                = 0x00000001,
5774  } PHYSYMCLK_FORCE_EN;
5775  
5776  /*
5777   * PHYSYMCLK_FORCE_SRC_SEL enum
5778   */
5779  
5780  typedef enum PHYSYMCLK_FORCE_SRC_SEL {
5781  PHYSYMCLK_FORCE_SRC_SYMCLK               = 0x00000000,
5782  PHYSYMCLK_FORCE_SRC_PHYD18CLK            = 0x00000001,
5783  PHYSYMCLK_FORCE_SRC_PHYD32CLK            = 0x00000002,
5784  } PHYSYMCLK_FORCE_SRC_SEL;
5785  
5786  /*
5787   * PIPE_PHYPLL_PIXEL_RATE_SOURCE enum
5788   */
5789  
5790  typedef enum PIPE_PHYPLL_PIXEL_RATE_SOURCE {
5791  PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA    = 0x00000000,
5792  PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB    = 0x00000001,
5793  PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC    = 0x00000002,
5794  PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD    = 0x00000003,
5795  PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED   = 0x00000004,
5796  } PIPE_PHYPLL_PIXEL_RATE_SOURCE;
5797  
5798  /*
5799   * PIPE_PIXEL_RATE_PLL_SOURCE enum
5800   */
5801  
5802  typedef enum PIPE_PIXEL_RATE_PLL_SOURCE {
5803  PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL        = 0x00000000,
5804  PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL       = 0x00000001,
5805  } PIPE_PIXEL_RATE_PLL_SOURCE;
5806  
5807  /*
5808   * PIPE_PIXEL_RATE_SOURCE enum
5809   */
5810  
5811  typedef enum PIPE_PIXEL_RATE_SOURCE {
5812  PIPE_PIXEL_RATE_SOURCE_P0PLL             = 0x00000000,
5813  PIPE_PIXEL_RATE_SOURCE_P1PLL             = 0x00000001,
5814  PIPE_PIXEL_RATE_SOURCE_P2PLL             = 0x00000002,
5815  } PIPE_PIXEL_RATE_SOURCE;
5816  
5817  /*
5818   * PLL_CFG_IF_SOFT_RESET enum
5819   */
5820  
5821  typedef enum PLL_CFG_IF_SOFT_RESET {
5822  PLL_CFG_IF_SOFT_RESET_NOOP               = 0x00000000,
5823  PLL_CFG_IF_SOFT_RESET_FORCE              = 0x00000001,
5824  } PLL_CFG_IF_SOFT_RESET;
5825  
5826  /*
5827   * SYMCLK_FE_FORCE_EN enum
5828   */
5829  
5830  typedef enum SYMCLK_FE_FORCE_EN {
5831  SYMCLK_FE_FORCE_EN_DISABLE               = 0x00000000,
5832  SYMCLK_FE_FORCE_EN_ENABLE                = 0x00000001,
5833  } SYMCLK_FE_FORCE_EN;
5834  
5835  /*
5836   * SYMCLK_FE_FORCE_SRC enum
5837   */
5838  
5839  typedef enum SYMCLK_FE_FORCE_SRC {
5840  SYMCLK_FE_FORCE_SRC_UNIPHYA              = 0x00000000,
5841  SYMCLK_FE_FORCE_SRC_UNIPHYB              = 0x00000001,
5842  SYMCLK_FE_FORCE_SRC_UNIPHYC              = 0x00000002,
5843  SYMCLK_FE_FORCE_SRC_UNIPHYD              = 0x00000003,
5844  SYMCLK_FE_FORCE_SRC_RESERVED             = 0x00000004,
5845  } SYMCLK_FE_FORCE_SRC;
5846  
5847  /*
5848   * TEST_CLK_DIV_SEL enum
5849   */
5850  
5851  typedef enum TEST_CLK_DIV_SEL {
5852  NO_DIV                                   = 0x00000000,
5853  DIV_2                                    = 0x00000001,
5854  DIV_4                                    = 0x00000002,
5855  DIV_8                                    = 0x00000003,
5856  } TEST_CLK_DIV_SEL;
5857  
5858  /*
5859   * VSYNC_CNT_LATCH_MASK enum
5860   */
5861  
5862  typedef enum VSYNC_CNT_LATCH_MASK {
5863  VSYNC_CNT_LATCH_MASK_0                   = 0x00000000,
5864  VSYNC_CNT_LATCH_MASK_1                   = 0x00000001,
5865  } VSYNC_CNT_LATCH_MASK;
5866  
5867  /*
5868   * VSYNC_CNT_RESET_SEL enum
5869   */
5870  
5871  typedef enum VSYNC_CNT_RESET_SEL {
5872  VSYNC_CNT_RESET_SEL_0                    = 0x00000000,
5873  VSYNC_CNT_RESET_SEL_1                    = 0x00000001,
5874  } VSYNC_CNT_RESET_SEL;
5875  
5876  /*
5877   * XTAL_REF_CLOCK_SOURCE_SEL enum
5878   */
5879  
5880  typedef enum XTAL_REF_CLOCK_SOURCE_SEL {
5881  XTAL_REF_CLOCK_SOURCE_SEL_XTALIN         = 0x00000000,
5882  XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK     = 0x00000001,
5883  } XTAL_REF_CLOCK_SOURCE_SEL;
5884  
5885  /*
5886   * XTAL_REF_SEL enum
5887   */
5888  
5889  typedef enum XTAL_REF_SEL {
5890  XTAL_REF_SEL_1X                          = 0x00000000,
5891  XTAL_REF_SEL_2X                          = 0x00000001,
5892  } XTAL_REF_SEL;
5893  
5894  /*******************************************************
5895   * HPD Enums
5896   *******************************************************/
5897  
5898  /*
5899   * HPD_INT_CONTROL_ACK enum
5900   */
5901  
5902  typedef enum HPD_INT_CONTROL_ACK {
5903  HPD_INT_CONTROL_ACK_0                    = 0x00000000,
5904  HPD_INT_CONTROL_ACK_1                    = 0x00000001,
5905  } HPD_INT_CONTROL_ACK;
5906  
5907  /*
5908   * HPD_INT_CONTROL_POLARITY enum
5909   */
5910  
5911  typedef enum HPD_INT_CONTROL_POLARITY {
5912  HPD_INT_CONTROL_GEN_INT_ON_DISCON        = 0x00000000,
5913  HPD_INT_CONTROL_GEN_INT_ON_CON           = 0x00000001,
5914  } HPD_INT_CONTROL_POLARITY;
5915  
5916  /*
5917   * HPD_INT_CONTROL_RX_INT_ACK enum
5918   */
5919  
5920  typedef enum HPD_INT_CONTROL_RX_INT_ACK {
5921  HPD_INT_CONTROL_RX_INT_ACK_0             = 0x00000000,
5922  HPD_INT_CONTROL_RX_INT_ACK_1             = 0x00000001,
5923  } HPD_INT_CONTROL_RX_INT_ACK;
5924  
5925  /*******************************************************
5926   * DP Enums
5927   *******************************************************/
5928  
5929  /*
5930   * DPHY_8B10B_CUR_DISP enum
5931   */
5932  
5933  typedef enum DPHY_8B10B_CUR_DISP {
5934  DPHY_8B10B_CUR_DISP_ZERO                 = 0x00000000,
5935  DPHY_8B10B_CUR_DISP_ONE                  = 0x00000001,
5936  } DPHY_8B10B_CUR_DISP;
5937  
5938  /*
5939   * DPHY_8B10B_RESET enum
5940   */
5941  
5942  typedef enum DPHY_8B10B_RESET {
5943  DPHY_8B10B_NOT_RESET                     = 0x00000000,
5944  DPHY_8B10B_RESETET                       = 0x00000001,
5945  } DPHY_8B10B_RESET;
5946  
5947  /*
5948   * DPHY_ALT_SCRAMBLER_RESET_EN enum
5949   */
5950  
5951  typedef enum DPHY_ALT_SCRAMBLER_RESET_EN {
5952  DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE   = 0x00000000,
5953  DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION = 0x00000001,
5954  } DPHY_ALT_SCRAMBLER_RESET_EN;
5955  
5956  /*
5957   * DPHY_ALT_SCRAMBLER_RESET_SEL enum
5958   */
5959  
5960  typedef enum DPHY_ALT_SCRAMBLER_RESET_SEL {
5961  DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE = 0x00000000,
5962  DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE = 0x00000001,
5963  } DPHY_ALT_SCRAMBLER_RESET_SEL;
5964  
5965  /*
5966   * DPHY_ATEST_SEL_LANE0 enum
5967   */
5968  
5969  typedef enum DPHY_ATEST_SEL_LANE0 {
5970  DPHY_ATEST_LANE0_PRBS_PATTERN            = 0x00000000,
5971  DPHY_ATEST_LANE0_REG_PATTERN             = 0x00000001,
5972  } DPHY_ATEST_SEL_LANE0;
5973  
5974  /*
5975   * DPHY_ATEST_SEL_LANE1 enum
5976   */
5977  
5978  typedef enum DPHY_ATEST_SEL_LANE1 {
5979  DPHY_ATEST_LANE1_PRBS_PATTERN            = 0x00000000,
5980  DPHY_ATEST_LANE1_REG_PATTERN             = 0x00000001,
5981  } DPHY_ATEST_SEL_LANE1;
5982  
5983  /*
5984   * DPHY_ATEST_SEL_LANE2 enum
5985   */
5986  
5987  typedef enum DPHY_ATEST_SEL_LANE2 {
5988  DPHY_ATEST_LANE2_PRBS_PATTERN            = 0x00000000,
5989  DPHY_ATEST_LANE2_REG_PATTERN             = 0x00000001,
5990  } DPHY_ATEST_SEL_LANE2;
5991  
5992  /*
5993   * DPHY_ATEST_SEL_LANE3 enum
5994   */
5995  
5996  typedef enum DPHY_ATEST_SEL_LANE3 {
5997  DPHY_ATEST_LANE3_PRBS_PATTERN            = 0x00000000,
5998  DPHY_ATEST_LANE3_REG_PATTERN             = 0x00000001,
5999  } DPHY_ATEST_SEL_LANE3;
6000  
6001  /*
6002   * DPHY_BYPASS enum
6003   */
6004  
6005  typedef enum DPHY_BYPASS {
6006  DPHY_8B10B_OUTPUT                        = 0x00000000,
6007  DPHY_DBG_OUTPUT                          = 0x00000001,
6008  } DPHY_BYPASS;
6009  
6010  /*
6011   * DPHY_CRC_CONT_EN enum
6012   */
6013  
6014  typedef enum DPHY_CRC_CONT_EN {
6015  DPHY_CRC_ONE_SHOT                        = 0x00000000,
6016  DPHY_CRC_CONTINUOUS                      = 0x00000001,
6017  } DPHY_CRC_CONT_EN;
6018  
6019  /*
6020   * DPHY_CRC_EN enum
6021   */
6022  
6023  typedef enum DPHY_CRC_EN {
6024  DPHY_CRC_DISABLED                        = 0x00000000,
6025  DPHY_CRC_ENABLED                         = 0x00000001,
6026  } DPHY_CRC_EN;
6027  
6028  /*
6029   * DPHY_CRC_FIELD enum
6030   */
6031  
6032  typedef enum DPHY_CRC_FIELD {
6033  DPHY_CRC_START_FROM_TOP_FIELD            = 0x00000000,
6034  DPHY_CRC_START_FROM_BOTTOM_FIELD         = 0x00000001,
6035  } DPHY_CRC_FIELD;
6036  
6037  /*
6038   * DPHY_CRC_MST_PHASE_ERROR_ACK enum
6039   */
6040  
6041  typedef enum DPHY_CRC_MST_PHASE_ERROR_ACK {
6042  DPHY_CRC_MST_PHASE_ERROR_NO_ACK          = 0x00000000,
6043  DPHY_CRC_MST_PHASE_ERROR_ACKED           = 0x00000001,
6044  } DPHY_CRC_MST_PHASE_ERROR_ACK;
6045  
6046  /*
6047   * DPHY_CRC_SEL enum
6048   */
6049  
6050  typedef enum DPHY_CRC_SEL {
6051  DPHY_CRC_LANE0_SELECTED                  = 0x00000000,
6052  DPHY_CRC_LANE1_SELECTED                  = 0x00000001,
6053  DPHY_CRC_LANE2_SELECTED                  = 0x00000002,
6054  DPHY_CRC_LANE3_SELECTED                  = 0x00000003,
6055  } DPHY_CRC_SEL;
6056  
6057  /*
6058   * DPHY_FEC_ENABLE enum
6059   */
6060  
6061  typedef enum DPHY_FEC_ENABLE {
6062  DPHY_FEC_DISABLED                        = 0x00000000,
6063  DPHY_FEC_ENABLED                         = 0x00000001,
6064  } DPHY_FEC_ENABLE;
6065  
6066  /*
6067   * DPHY_FEC_READY enum
6068   */
6069  
6070  typedef enum DPHY_FEC_READY {
6071  DPHY_FEC_READY_EN                        = 0x00000000,
6072  DPHY_FEC_READY_DIS                       = 0x00000001,
6073  } DPHY_FEC_READY;
6074  
6075  /*
6076   * DPHY_LOAD_BS_COUNT_START enum
6077   */
6078  
6079  typedef enum DPHY_LOAD_BS_COUNT_START {
6080  DPHY_LOAD_BS_COUNT_STARTED               = 0x00000000,
6081  DPHY_LOAD_BS_COUNT_NOT_STARTED           = 0x00000001,
6082  } DPHY_LOAD_BS_COUNT_START;
6083  
6084  /*
6085   * DPHY_PRBS_EN enum
6086   */
6087  
6088  typedef enum DPHY_PRBS_EN {
6089  DPHY_PRBS_DISABLE                        = 0x00000000,
6090  DPHY_PRBS_ENABLE                         = 0x00000001,
6091  } DPHY_PRBS_EN;
6092  
6093  /*
6094   * DPHY_PRBS_SEL enum
6095   */
6096  
6097  typedef enum DPHY_PRBS_SEL {
6098  DPHY_PRBS7_SELECTED                      = 0x00000000,
6099  DPHY_PRBS23_SELECTED                     = 0x00000001,
6100  DPHY_PRBS11_SELECTED                     = 0x00000002,
6101  } DPHY_PRBS_SEL;
6102  
6103  /*
6104   * DPHY_RX_FAST_TRAINING_CAPABLE enum
6105   */
6106  
6107  typedef enum DPHY_RX_FAST_TRAINING_CAPABLE {
6108  DPHY_FAST_TRAINING_NOT_CAPABLE_0         = 0x00000000,
6109  DPHY_FAST_TRAINING_CAPABLE               = 0x00000001,
6110  } DPHY_RX_FAST_TRAINING_CAPABLE;
6111  
6112  /*
6113   * DPHY_SCRAMBLER_ADVANCE enum
6114   */
6115  
6116  typedef enum DPHY_SCRAMBLER_ADVANCE {
6117  DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY = 0x00000000,
6118  DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL = 0x00000001,
6119  } DPHY_SCRAMBLER_ADVANCE;
6120  
6121  /*
6122   * DPHY_SCRAMBLER_DIS enum
6123   */
6124  
6125  typedef enum DPHY_SCRAMBLER_DIS {
6126  DPHY_SCR_ENABLED                         = 0x00000000,
6127  DPHY_SCR_DISABLED                        = 0x00000001,
6128  } DPHY_SCRAMBLER_DIS;
6129  
6130  /*
6131   * DPHY_SCRAMBLER_KCODE enum
6132   */
6133  
6134  typedef enum DPHY_SCRAMBLER_KCODE {
6135  DPHY_SCRAMBLER_KCODE_DISABLED            = 0x00000000,
6136  DPHY_SCRAMBLER_KCODE_ENABLED             = 0x00000001,
6137  } DPHY_SCRAMBLER_KCODE;
6138  
6139  /*
6140   * DPHY_SCRAMBLER_SEL enum
6141   */
6142  
6143  typedef enum DPHY_SCRAMBLER_SEL {
6144  DPHY_SCRAMBLER_SEL_LANE_DATA             = 0x00000000,
6145  DPHY_SCRAMBLER_SEL_DBG_DATA              = 0x00000001,
6146  } DPHY_SCRAMBLER_SEL;
6147  
6148  /*
6149   * DPHY_SKEW_BYPASS enum
6150   */
6151  
6152  typedef enum DPHY_SKEW_BYPASS {
6153  DPHY_WITH_SKEW                           = 0x00000000,
6154  DPHY_NO_SKEW                             = 0x00000001,
6155  } DPHY_SKEW_BYPASS;
6156  
6157  /*
6158   * DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM enum
6159   */
6160  
6161  typedef enum DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM {
6162  DPHY_STREAM_RESET_DURING_FAST_TRAINING_RESET = 0x00000000,
6163  DPHY_STREAM_RESET_DURING_FAST_TRAINING_NOT_RESET = 0x00000001,
6164  } DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM;
6165  
6166  /*
6167   * DPHY_SW_FAST_TRAINING_START enum
6168   */
6169  
6170  typedef enum DPHY_SW_FAST_TRAINING_START {
6171  DPHY_SW_FAST_TRAINING_NOT_STARTED        = 0x00000000,
6172  DPHY_SW_FAST_TRAINING_STARTED            = 0x00000001,
6173  } DPHY_SW_FAST_TRAINING_START;
6174  
6175  /*
6176   * DPHY_TRAINING_PATTERN_SEL enum
6177   */
6178  
6179  typedef enum DPHY_TRAINING_PATTERN_SEL {
6180  DPHY_TRAINING_PATTERN_1                  = 0x00000000,
6181  DPHY_TRAINING_PATTERN_2                  = 0x00000001,
6182  DPHY_TRAINING_PATTERN_3                  = 0x00000002,
6183  DPHY_TRAINING_PATTERN_4                  = 0x00000003,
6184  } DPHY_TRAINING_PATTERN_SEL;
6185  
6186  /*
6187   * DP_COMPONENT_DEPTH enum
6188   */
6189  
6190  typedef enum DP_COMPONENT_DEPTH {
6191  DP_COMPONENT_DEPTH_6BPC                  = 0x00000000,
6192  DP_COMPONENT_DEPTH_8BPC                  = 0x00000001,
6193  DP_COMPONENT_DEPTH_10BPC                 = 0x00000002,
6194  DP_COMPONENT_DEPTH_12BPC                 = 0x00000003,
6195  DP_COMPONENT_DEPTH_16BPC                 = 0x00000004,
6196  } DP_COMPONENT_DEPTH;
6197  
6198  /*
6199   * DP_CP_ENCRYPTION_TYPE enum
6200   */
6201  
6202  typedef enum DP_CP_ENCRYPTION_TYPE {
6203  DP_CP_ENCRYPTION_TYPE_0                  = 0x00000000,
6204  DP_CP_ENCRYPTION_TYPE_1                  = 0x00000001,
6205  } DP_CP_ENCRYPTION_TYPE;
6206  
6207  /*
6208   * DP_DPHY_8B10B_EXT_DISP enum
6209   */
6210  
6211  typedef enum DP_DPHY_8B10B_EXT_DISP {
6212  DP_DPHY_8B10B_EXT_DISP_ZERO              = 0x00000000,
6213  DP_DPHY_8B10B_EXT_DISP_ONE               = 0x00000001,
6214  } DP_DPHY_8B10B_EXT_DISP;
6215  
6216  /*
6217   * DP_DPHY_FAST_TRAINING_COMPLETE_ACK enum
6218   */
6219  
6220  typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_ACK {
6221  DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED = 0x00000000,
6222  DP_DPHY_FAST_TRAINING_COMPLETE_ACKED     = 0x00000001,
6223  } DP_DPHY_FAST_TRAINING_COMPLETE_ACK;
6224  
6225  /*
6226   * DP_DPHY_FAST_TRAINING_COMPLETE_MASK enum
6227   */
6228  
6229  typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_MASK {
6230  DP_DPHY_FAST_TRAINING_COMPLETE_MASKED    = 0x00000000,
6231  DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED = 0x00000001,
6232  } DP_DPHY_FAST_TRAINING_COMPLETE_MASK;
6233  
6234  /*
6235   * DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN enum
6236   */
6237  
6238  typedef enum DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN {
6239  DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED = 0x00000000,
6240  DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 0x00000001,
6241  } DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN;
6242  
6243  /*
6244   * DP_DPHY_HBR2_PATTERN_CONTROL_MODE enum
6245   */
6246  
6247  typedef enum DP_DPHY_HBR2_PATTERN_CONTROL_MODE {
6248  DP_DPHY_HBR2_PASS_THROUGH                = 0x00000000,
6249  DP_DPHY_HBR2_PATTERN_1                   = 0x00000001,
6250  DP_DPHY_HBR2_PATTERN_2_NEG               = 0x00000002,
6251  DP_DPHY_HBR2_PATTERN_3                   = 0x00000003,
6252  DP_DPHY_HBR2_PATTERN_2_POS               = 0x00000006,
6253  } DP_DPHY_HBR2_PATTERN_CONTROL_MODE;
6254  
6255  /*
6256   * DP_DSC_MODE enum
6257   */
6258  
6259  typedef enum DP_DSC_MODE {
6260  DP_DSC_DISABLE                           = 0x00000000,
6261  DP_DSC_444_SIMPLE_422                    = 0x00000001,
6262  DP_DSC_NATIVE_422_420                    = 0x00000002,
6263  } DP_DSC_MODE;
6264  
6265  /*
6266   * DP_EMBEDDED_PANEL_MODE enum
6267   */
6268  
6269  typedef enum DP_EMBEDDED_PANEL_MODE {
6270  DP_EXTERNAL_PANEL                        = 0x00000000,
6271  DP_EMBEDDED_PANEL                        = 0x00000001,
6272  } DP_EMBEDDED_PANEL_MODE;
6273  
6274  /*
6275   * DP_LINK_TRAINING_COMPLETE enum
6276   */
6277  
6278  typedef enum DP_LINK_TRAINING_COMPLETE {
6279  DP_LINK_TRAINING_NOT_COMPLETE            = 0x00000000,
6280  DP_LINK_TRAINING_ALREADY_COMPLETE        = 0x00000001,
6281  } DP_LINK_TRAINING_COMPLETE;
6282  
6283  /*
6284   * DP_LINK_TRAINING_SWITCH_MODE enum
6285   */
6286  
6287  typedef enum DP_LINK_TRAINING_SWITCH_MODE {
6288  DP_LINK_TRAINING_SWITCH_TO_IDLE          = 0x00000000,
6289  DP_LINK_TRAINING_SWITCH_TO_VIDEO         = 0x00000001,
6290  } DP_LINK_TRAINING_SWITCH_MODE;
6291  
6292  /*
6293   * DP_ML_PHY_SEQ_MODE enum
6294   */
6295  
6296  typedef enum DP_ML_PHY_SEQ_MODE {
6297  DP_ML_PHY_SEQ_LINE_NUM                   = 0x00000000,
6298  DP_ML_PHY_SEQ_IMMEDIATE                  = 0x00000001,
6299  } DP_ML_PHY_SEQ_MODE;
6300  
6301  /*
6302   * DP_MSA_V_TIMING_OVERRIDE_EN enum
6303   */
6304  
6305  typedef enum DP_MSA_V_TIMING_OVERRIDE_EN {
6306  MSA_V_TIMING_OVERRIDE_DISABLED           = 0x00000000,
6307  MSA_V_TIMING_OVERRIDE_ENABLED            = 0x00000001,
6308  } DP_MSA_V_TIMING_OVERRIDE_EN;
6309  
6310  /*
6311   * DP_MSE_BLANK_CODE enum
6312   */
6313  
6314  typedef enum DP_MSE_BLANK_CODE {
6315  DP_MSE_BLANK_CODE_SF_FILLED              = 0x00000000,
6316  DP_MSE_BLANK_CODE_ZERO_FILLED            = 0x00000001,
6317  } DP_MSE_BLANK_CODE;
6318  
6319  /*
6320   * DP_MSE_LINK_LINE enum
6321   */
6322  
6323  typedef enum DP_MSE_LINK_LINE {
6324  DP_MSE_LINK_LINE_32_MTP_LONG             = 0x00000000,
6325  DP_MSE_LINK_LINE_64_MTP_LONG             = 0x00000001,
6326  DP_MSE_LINK_LINE_128_MTP_LONG            = 0x00000002,
6327  DP_MSE_LINK_LINE_256_MTP_LONG            = 0x00000003,
6328  } DP_MSE_LINK_LINE;
6329  
6330  /*
6331   * DP_MSE_SAT_ENCRYPT0 enum
6332   */
6333  
6334  typedef enum DP_MSE_SAT_ENCRYPT0 {
6335  DP_MSE_SAT_ENCRYPT0_DISABLED             = 0x00000000,
6336  DP_MSE_SAT_ENCRYPT0_ENABLED              = 0x00000001,
6337  } DP_MSE_SAT_ENCRYPT0;
6338  
6339  /*
6340   * DP_MSE_SAT_ENCRYPT1 enum
6341   */
6342  
6343  typedef enum DP_MSE_SAT_ENCRYPT1 {
6344  DP_MSE_SAT_ENCRYPT1_DISABLED             = 0x00000000,
6345  DP_MSE_SAT_ENCRYPT1_ENABLED              = 0x00000001,
6346  } DP_MSE_SAT_ENCRYPT1;
6347  
6348  /*
6349   * DP_MSE_SAT_ENCRYPT2 enum
6350   */
6351  
6352  typedef enum DP_MSE_SAT_ENCRYPT2 {
6353  DP_MSE_SAT_ENCRYPT2_DISABLED             = 0x00000000,
6354  DP_MSE_SAT_ENCRYPT2_ENABLED              = 0x00000001,
6355  } DP_MSE_SAT_ENCRYPT2;
6356  
6357  /*
6358   * DP_MSE_SAT_ENCRYPT3 enum
6359   */
6360  
6361  typedef enum DP_MSE_SAT_ENCRYPT3 {
6362  DP_MSE_SAT_ENCRYPT3_DISABLED             = 0x00000000,
6363  DP_MSE_SAT_ENCRYPT3_ENABLED              = 0x00000001,
6364  } DP_MSE_SAT_ENCRYPT3;
6365  
6366  /*
6367   * DP_MSE_SAT_ENCRYPT4 enum
6368   */
6369  
6370  typedef enum DP_MSE_SAT_ENCRYPT4 {
6371  DP_MSE_SAT_ENCRYPT4_DISABLED             = 0x00000000,
6372  DP_MSE_SAT_ENCRYPT4_ENABLED              = 0x00000001,
6373  } DP_MSE_SAT_ENCRYPT4;
6374  
6375  /*
6376   * DP_MSE_SAT_ENCRYPT5 enum
6377   */
6378  
6379  typedef enum DP_MSE_SAT_ENCRYPT5 {
6380  DP_MSE_SAT_ENCRYPT5_DISABLED             = 0x00000000,
6381  DP_MSE_SAT_ENCRYPT5_ENABLED              = 0x00000001,
6382  } DP_MSE_SAT_ENCRYPT5;
6383  
6384  /*
6385   * DP_MSE_SAT_UPDATE_ACT enum
6386   */
6387  
6388  typedef enum DP_MSE_SAT_UPDATE_ACT {
6389  DP_MSE_SAT_UPDATE_NO_ACTION              = 0x00000000,
6390  DP_MSE_SAT_UPDATE_WITH_TRIGGER           = 0x00000001,
6391  DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER        = 0x00000002,
6392  } DP_MSE_SAT_UPDATE_ACT;
6393  
6394  /*
6395   * DP_MSE_TIMESTAMP_MODE enum
6396   */
6397  
6398  typedef enum DP_MSE_TIMESTAMP_MODE {
6399  DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE = 0x00000000,
6400  DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE   = 0x00000001,
6401  } DP_MSE_TIMESTAMP_MODE;
6402  
6403  /*
6404   * DP_MSE_ZERO_ENCODER enum
6405   */
6406  
6407  typedef enum DP_MSE_ZERO_ENCODER {
6408  DP_MSE_NOT_ZERO_FE_ENCODER               = 0x00000000,
6409  DP_MSE_ZERO_FE_ENCODER                   = 0x00000001,
6410  } DP_MSE_ZERO_ENCODER;
6411  
6412  /*
6413   * DP_MSO_NUM_OF_SST_LINKS enum
6414   */
6415  
6416  typedef enum DP_MSO_NUM_OF_SST_LINKS {
6417  DP_MSO_ONE_SSTLINK                       = 0x00000000,
6418  DP_MSO_TWO_SSTLINK                       = 0x00000001,
6419  DP_MSO_FOUR_SSTLINK                      = 0x00000002,
6420  } DP_MSO_NUM_OF_SST_LINKS;
6421  
6422  /*
6423   * DP_PIXEL_ENCODING enum
6424   */
6425  
6426  typedef enum DP_PIXEL_ENCODING {
6427  DP_PIXEL_ENCODING_RGB444                 = 0x00000000,
6428  DP_PIXEL_ENCODING_YCBCR422               = 0x00000001,
6429  DP_PIXEL_ENCODING_YCBCR444               = 0x00000002,
6430  DP_PIXEL_ENCODING_RGB_WIDE_GAMUT         = 0x00000003,
6431  DP_PIXEL_ENCODING_Y_ONLY                 = 0x00000004,
6432  DP_PIXEL_ENCODING_YCBCR420               = 0x00000005,
6433  } DP_PIXEL_ENCODING;
6434  
6435  /*
6436   * DP_PIXEL_PER_CYCLE_PROCESSING_NUM enum
6437   */
6438  
6439  typedef enum DP_PIXEL_PER_CYCLE_PROCESSING_NUM {
6440  DP_ONE_PIXEL_PER_CYCLE                   = 0x00000000,
6441  DP_TWO_PIXEL_PER_CYCLE                   = 0x00000001,
6442  } DP_PIXEL_PER_CYCLE_PROCESSING_NUM;
6443  
6444  /*
6445   * DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE enum
6446   */
6447  
6448  typedef enum DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE {
6449  DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ         = 0x00000000,
6450  DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 0x00000001,
6451  } DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE;
6452  
6453  /*
6454   * DP_SEC_ASP_PRIORITY enum
6455   */
6456  
6457  typedef enum DP_SEC_ASP_PRIORITY {
6458  DP_SEC_ASP_LOW_PRIORITY                  = 0x00000000,
6459  DP_SEC_ASP_HIGH_PRIORITY                 = 0x00000001,
6460  } DP_SEC_ASP_PRIORITY;
6461  
6462  /*
6463   * DP_SEC_AUDIO_MUTE enum
6464   */
6465  
6466  typedef enum DP_SEC_AUDIO_MUTE {
6467  DP_SEC_AUDIO_MUTE_HW_CTRL                = 0x00000000,
6468  DP_SEC_AUDIO_MUTE_SW_CTRL                = 0x00000001,
6469  } DP_SEC_AUDIO_MUTE;
6470  
6471  /*
6472   * DP_SEC_COLLISION_ACK enum
6473   */
6474  
6475  typedef enum DP_SEC_COLLISION_ACK {
6476  DP_SEC_COLLISION_ACK_NO_EFFECT           = 0x00000000,
6477  DP_SEC_COLLISION_ACK_CLR_FLAG            = 0x00000001,
6478  } DP_SEC_COLLISION_ACK;
6479  
6480  /*
6481   * DP_SEC_GSP0_PRIORITY enum
6482   */
6483  
6484  typedef enum DP_SEC_GSP0_PRIORITY {
6485  SEC_GSP0_PRIORITY_LOW                    = 0x00000000,
6486  SEC_GSP0_PRIORITY_HIGH                   = 0x00000001,
6487  } DP_SEC_GSP0_PRIORITY;
6488  
6489  /*
6490   * DP_SEC_GSP_SEND enum
6491   */
6492  
6493  typedef enum DP_SEC_GSP_SEND {
6494  NOT_SENT                                 = 0x00000000,
6495  FORCE_SENT                               = 0x00000001,
6496  } DP_SEC_GSP_SEND;
6497  
6498  /*
6499   * DP_SEC_GSP_SEND_ANY_LINE enum
6500   */
6501  
6502  typedef enum DP_SEC_GSP_SEND_ANY_LINE {
6503  SEND_AT_LINK_NUMBER                      = 0x00000000,
6504  SEND_AT_EARLIEST_TIME                    = 0x00000001,
6505  } DP_SEC_GSP_SEND_ANY_LINE;
6506  
6507  /*
6508   * DP_SEC_GSP_SEND_PPS enum
6509   */
6510  
6511  typedef enum DP_SEC_GSP_SEND_PPS {
6512  SEND_NORMAL_PACKET                       = 0x00000000,
6513  SEND_PPS_PACKET                          = 0x00000001,
6514  } DP_SEC_GSP_SEND_PPS;
6515  
6516  /*
6517   * DP_SEC_LINE_REFERENCE enum
6518   */
6519  
6520  typedef enum DP_SEC_LINE_REFERENCE {
6521  REFER_TO_DP_SOF                          = 0x00000000,
6522  REFER_TO_OTG_SOF                         = 0x00000001,
6523  } DP_SEC_LINE_REFERENCE;
6524  
6525  /*
6526   * DP_SEC_TIMESTAMP_MODE enum
6527   */
6528  
6529  typedef enum DP_SEC_TIMESTAMP_MODE {
6530  DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE       = 0x00000000,
6531  DP_SEC_TIMESTAMP_AUTO_CALC_MODE          = 0x00000001,
6532  } DP_SEC_TIMESTAMP_MODE;
6533  
6534  /*
6535   * DP_STEER_OVERFLOW_ACK enum
6536   */
6537  
6538  typedef enum DP_STEER_OVERFLOW_ACK {
6539  DP_STEER_OVERFLOW_ACK_NO_EFFECT          = 0x00000000,
6540  DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT      = 0x00000001,
6541  } DP_STEER_OVERFLOW_ACK;
6542  
6543  /*
6544   * DP_STEER_OVERFLOW_MASK enum
6545   */
6546  
6547  typedef enum DP_STEER_OVERFLOW_MASK {
6548  DP_STEER_OVERFLOW_MASKED                 = 0x00000000,
6549  DP_STEER_OVERFLOW_UNMASK                 = 0x00000001,
6550  } DP_STEER_OVERFLOW_MASK;
6551  
6552  /*
6553   * DP_SYNC_POLARITY enum
6554   */
6555  
6556  typedef enum DP_SYNC_POLARITY {
6557  DP_SYNC_POLARITY_ACTIVE_HIGH             = 0x00000000,
6558  DP_SYNC_POLARITY_ACTIVE_LOW              = 0x00000001,
6559  } DP_SYNC_POLARITY;
6560  
6561  /*
6562   * DP_TU_OVERFLOW_ACK enum
6563   */
6564  
6565  typedef enum DP_TU_OVERFLOW_ACK {
6566  DP_TU_OVERFLOW_ACK_NO_EFFECT             = 0x00000000,
6567  DP_TU_OVERFLOW_ACK_CLR_INTERRUPT         = 0x00000001,
6568  } DP_TU_OVERFLOW_ACK;
6569  
6570  /*
6571   * DP_UDI_LANES enum
6572   */
6573  
6574  typedef enum DP_UDI_LANES {
6575  DP_UDI_1_LANE                            = 0x00000000,
6576  DP_UDI_2_LANES                           = 0x00000001,
6577  DP_UDI_LANES_RESERVED                    = 0x00000002,
6578  DP_UDI_4_LANES                           = 0x00000003,
6579  } DP_UDI_LANES;
6580  
6581  /*
6582   * DP_VID_ENHANCED_FRAME_MODE enum
6583   */
6584  
6585  typedef enum DP_VID_ENHANCED_FRAME_MODE {
6586  VID_NORMAL_FRAME_MODE                    = 0x00000000,
6587  VID_ENHANCED_MODE                        = 0x00000001,
6588  } DP_VID_ENHANCED_FRAME_MODE;
6589  
6590  /*
6591   * DP_VID_M_N_DOUBLE_BUFFER_MODE enum
6592   */
6593  
6594  typedef enum DP_VID_M_N_DOUBLE_BUFFER_MODE {
6595  DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE = 0x00000000,
6596  DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START  = 0x00000001,
6597  } DP_VID_M_N_DOUBLE_BUFFER_MODE;
6598  
6599  /*
6600   * DP_VID_M_N_GEN_EN enum
6601   */
6602  
6603  typedef enum DP_VID_M_N_GEN_EN {
6604  DP_VID_M_N_PROGRAMMED_VIA_REG            = 0x00000000,
6605  DP_VID_M_N_CALC_AUTO                     = 0x00000001,
6606  } DP_VID_M_N_GEN_EN;
6607  
6608  /*
6609   * DP_VID_N_MUL enum
6610   */
6611  
6612  typedef enum DP_VID_N_MUL {
6613  DP_VID_M_1X_INPUT_PIXEL_RATE             = 0x00000000,
6614  DP_VID_M_2X_INPUT_PIXEL_RATE             = 0x00000001,
6615  DP_VID_M_4X_INPUT_PIXEL_RATE             = 0x00000002,
6616  DP_VID_M_8X_INPUT_PIXEL_RATE             = 0x00000003,
6617  } DP_VID_N_MUL;
6618  
6619  /*
6620   * DP_VID_STREAM_DISABLE_ACK enum
6621   */
6622  
6623  typedef enum DP_VID_STREAM_DISABLE_ACK {
6624  ID_STREAM_DISABLE_NO_ACK                 = 0x00000000,
6625  ID_STREAM_DISABLE_ACKED                  = 0x00000001,
6626  } DP_VID_STREAM_DISABLE_ACK;
6627  
6628  /*
6629   * DP_VID_STREAM_DISABLE_MASK enum
6630   */
6631  
6632  typedef enum DP_VID_STREAM_DISABLE_MASK {
6633  VID_STREAM_DISABLE_MASKED                = 0x00000000,
6634  VID_STREAM_DISABLE_UNMASK                = 0x00000001,
6635  } DP_VID_STREAM_DISABLE_MASK;
6636  
6637  /*
6638   * DP_VID_STREAM_DIS_DEFER enum
6639   */
6640  
6641  typedef enum DP_VID_STREAM_DIS_DEFER {
6642  DP_VID_STREAM_DIS_NO_DEFER               = 0x00000000,
6643  DP_VID_STREAM_DIS_DEFER_TO_HBLANK        = 0x00000001,
6644  DP_VID_STREAM_DIS_DEFER_TO_VBLANK        = 0x00000002,
6645  } DP_VID_STREAM_DIS_DEFER;
6646  
6647  /*
6648   * DP_VID_VBID_FIELD_POL enum
6649   */
6650  
6651  typedef enum DP_VID_VBID_FIELD_POL {
6652  DP_VID_VBID_FIELD_POL_NORMAL             = 0x00000000,
6653  DP_VID_VBID_FIELD_POL_INV                = 0x00000001,
6654  } DP_VID_VBID_FIELD_POL;
6655  
6656  /*
6657   * FEC_ACTIVE_STATUS enum
6658   */
6659  
6660  typedef enum FEC_ACTIVE_STATUS {
6661  DPHY_FEC_NOT_ACTIVE                      = 0x00000000,
6662  DPHY_FEC_ACTIVE                          = 0x00000001,
6663  } FEC_ACTIVE_STATUS;
6664  
6665  /*******************************************************
6666   * DIG Enums
6667   *******************************************************/
6668  
6669  /*
6670   * DIG_BE_CNTL_HPD_SELECT enum
6671   */
6672  
6673  typedef enum DIG_BE_CNTL_HPD_SELECT {
6674  DIG_BE_CNTL_HPD1                         = 0x00000000,
6675  DIG_BE_CNTL_HPD2                         = 0x00000001,
6676  DIG_BE_CNTL_HPD3                         = 0x00000002,
6677  DIG_BE_CNTL_HPD4                         = 0x00000003,
6678  DIG_BE_CNTL_HPD5                         = 0x00000004,
6679  DIG_BE_CNTL_NO_HPD                       = 0x00000005,
6680  } DIG_BE_CNTL_HPD_SELECT;
6681  
6682  /*
6683   * DIG_BE_CNTL_MODE enum
6684   */
6685  
6686  typedef enum DIG_BE_CNTL_MODE {
6687  DIG_BE_DP_SST_MODE                       = 0x00000000,
6688  DIG_BE_RESERVED1                         = 0x00000001,
6689  DIG_BE_TMDS_DVI_MODE                     = 0x00000002,
6690  DIG_BE_TMDS_HDMI_MODE                    = 0x00000003,
6691  DIG_BE_RESERVED4                         = 0x00000004,
6692  DIG_BE_DP_MST_MODE                       = 0x00000005,
6693  DIG_BE_RESERVED2                         = 0x00000006,
6694  DIG_BE_RESERVED3                         = 0x00000007,
6695  } DIG_BE_CNTL_MODE;
6696  
6697  /*
6698   * DIG_DIGITAL_BYPASS_ENABLE enum
6699   */
6700  
6701  typedef enum DIG_DIGITAL_BYPASS_ENABLE {
6702  DIG_DIGITAL_BYPASS_OFF                   = 0x00000000,
6703  DIG_DIGITAL_BYPASS_ON                    = 0x00000001,
6704  } DIG_DIGITAL_BYPASS_ENABLE;
6705  
6706  /*
6707   * DIG_DIGITAL_BYPASS_SEL enum
6708   */
6709  
6710  typedef enum DIG_DIGITAL_BYPASS_SEL {
6711  DIG_DIGITAL_BYPASS_SEL_BYPASS            = 0x00000000,
6712  DIG_DIGITAL_BYPASS_SEL_36BPP             = 0x00000001,
6713  DIG_DIGITAL_BYPASS_SEL_48BPP_LSB         = 0x00000002,
6714  DIG_DIGITAL_BYPASS_SEL_48BPP_MSB         = 0x00000003,
6715  DIG_DIGITAL_BYPASS_SEL_10BPP_LSB         = 0x00000004,
6716  DIG_DIGITAL_BYPASS_SEL_12BPC_LSB         = 0x00000005,
6717  DIG_DIGITAL_BYPASS_SEL_ALPHA             = 0x00000006,
6718  } DIG_DIGITAL_BYPASS_SEL;
6719  
6720  /*
6721   * DIG_FE_CNTL_SOURCE_SELECT enum
6722   */
6723  
6724  typedef enum DIG_FE_CNTL_SOURCE_SELECT {
6725  DIG_FE_SOURCE_FROM_OTG0                  = 0x00000000,
6726  DIG_FE_SOURCE_FROM_OTG1                  = 0x00000001,
6727  DIG_FE_SOURCE_FROM_OTG2                  = 0x00000002,
6728  DIG_FE_SOURCE_FROM_OTG3                  = 0x00000003,
6729  DIG_FE_SOURCE_RESERVED                   = 0x00000004,
6730  } DIG_FE_CNTL_SOURCE_SELECT;
6731  
6732  /*
6733   * DIG_FE_CNTL_STEREOSYNC_SELECT enum
6734   */
6735  
6736  typedef enum DIG_FE_CNTL_STEREOSYNC_SELECT {
6737  DIG_FE_STEREOSYNC_FROM_OTG0              = 0x00000000,
6738  DIG_FE_STEREOSYNC_FROM_OTG1              = 0x00000001,
6739  DIG_FE_STEREOSYNC_FROM_OTG2              = 0x00000002,
6740  DIG_FE_STEREOSYNC_FROM_OTG3              = 0x00000003,
6741  DIG_FE_STEREOSYNC_RESERVED               = 0x00000004,
6742  } DIG_FE_CNTL_STEREOSYNC_SELECT;
6743  
6744  /*
6745   * DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX enum
6746   */
6747  
6748  typedef enum DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX {
6749  DIG_FIFO_NOT_FORCE_RECOMP_MINMAX         = 0x00000000,
6750  DIG_FIFO_FORCE_RECOMP_MINMAX             = 0x00000001,
6751  } DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX;
6752  
6753  /*
6754   * DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL enum
6755   */
6756  
6757  typedef enum DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL {
6758  DIG_FIFO_USE_OVERWRITE_LEVEL             = 0x00000000,
6759  DIG_FIFO_USE_CAL_AVERAGE_LEVEL           = 0x00000001,
6760  } DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL;
6761  
6762  /*
6763   * DIG_FIFO_FORCE_RECAL_AVERAGE enum
6764   */
6765  
6766  typedef enum DIG_FIFO_FORCE_RECAL_AVERAGE {
6767  DIG_FIFO_NOT_FORCE_RECAL_AVERAGE         = 0x00000000,
6768  DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL       = 0x00000001,
6769  } DIG_FIFO_FORCE_RECAL_AVERAGE;
6770  
6771  /*
6772   * DIG_FIFO_OUTPUT_PROCESSING_MODE enum
6773   */
6774  
6775  typedef enum DIG_FIFO_OUTPUT_PROCESSING_MODE {
6776  DIG_FIFO_1_PIX_PER_CYCLE                 = 0x00000000,
6777  DIG_FIFO_2_PIX_PER_CYCLE                 = 0x00000001,
6778  } DIG_FIFO_OUTPUT_PROCESSING_MODE;
6779  
6780  /*
6781   * DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR enum
6782   */
6783  
6784  typedef enum DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR {
6785  DIG_FIFO_NO_ERROR_OCCURRED               = 0x00000000,
6786  DIG_FIFO_UNDERFLOW_OCCURRED              = 0x00000001,
6787  DIG_FIFO_OVERFLOW_OCCURRED               = 0x00000002,
6788  } DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR;
6789  
6790  /*
6791   * DIG_FIFO_READ_CLOCK_SRC enum
6792   */
6793  
6794  typedef enum DIG_FIFO_READ_CLOCK_SRC {
6795  DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG        = 0x00000000,
6796  DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE = 0x00000001,
6797  } DIG_FIFO_READ_CLOCK_SRC;
6798  
6799  /*
6800   * DIG_INPUT_PIXEL_SEL enum
6801   */
6802  
6803  typedef enum DIG_INPUT_PIXEL_SEL {
6804  DIG_ALL_PIXEL                            = 0x00000000,
6805  DIG_EVEN_PIXEL_ONLY                      = 0x00000001,
6806  DIG_ODD_PIXEL_ONLY                       = 0x00000002,
6807  } DIG_INPUT_PIXEL_SEL;
6808  
6809  /*
6810   * DIG_OUTPUT_CRC_CNTL_LINK_SEL enum
6811   */
6812  
6813  typedef enum DIG_OUTPUT_CRC_CNTL_LINK_SEL {
6814  DIG_OUTPUT_CRC_ON_LINK0                  = 0x00000000,
6815  DIG_OUTPUT_CRC_ON_LINK1                  = 0x00000001,
6816  } DIG_OUTPUT_CRC_CNTL_LINK_SEL;
6817  
6818  /*
6819   * DIG_OUTPUT_CRC_DATA_SEL enum
6820   */
6821  
6822  typedef enum DIG_OUTPUT_CRC_DATA_SEL {
6823  DIG_OUTPUT_CRC_FOR_FULLFRAME             = 0x00000000,
6824  DIG_OUTPUT_CRC_FOR_ACTIVEONLY            = 0x00000001,
6825  DIG_OUTPUT_CRC_FOR_VBI                   = 0x00000002,
6826  DIG_OUTPUT_CRC_FOR_AUDIO                 = 0x00000003,
6827  } DIG_OUTPUT_CRC_DATA_SEL;
6828  
6829  /*
6830   * DIG_RANDOM_PATTERN_SEED_RAN_PAT enum
6831   */
6832  
6833  typedef enum DIG_RANDOM_PATTERN_SEED_RAN_PAT {
6834  DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS = 0x00000000,
6835  DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH  = 0x00000001,
6836  } DIG_RANDOM_PATTERN_SEED_RAN_PAT;
6837  
6838  /*
6839   * DIG_SL_PIXEL_GROUPING enum
6840   */
6841  
6842  typedef enum DIG_SL_PIXEL_GROUPING {
6843  DIG_SINGLETON_PIXELS                     = 0x00000000,
6844  DIG_PAIR_PIXELS                          = 0x00000001,
6845  } DIG_SL_PIXEL_GROUPING;
6846  
6847  /*
6848   * DIG_TEST_PATTERN_EXTERNAL_RESET_EN enum
6849   */
6850  
6851  typedef enum DIG_TEST_PATTERN_EXTERNAL_RESET_EN {
6852  DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE   = 0x00000000,
6853  DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG = 0x00000001,
6854  } DIG_TEST_PATTERN_EXTERNAL_RESET_EN;
6855  
6856  /*
6857   * DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL enum
6858   */
6859  
6860  typedef enum DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL {
6861  DIG_10BIT_TEST_PATTERN                   = 0x00000000,
6862  DIG_ALTERNATING_TEST_PATTERN             = 0x00000001,
6863  } DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL;
6864  
6865  /*
6866   * DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN enum
6867   */
6868  
6869  typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN {
6870  DIG_TEST_PATTERN_NORMAL                  = 0x00000000,
6871  DIG_TEST_PATTERN_RANDOM                  = 0x00000001,
6872  } DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN;
6873  
6874  /*
6875   * DIG_TEST_PATTERN_RANDOM_PATTERN_RESET enum
6876   */
6877  
6878  typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_RESET {
6879  DIG_RANDOM_PATTERN_ENABLED               = 0x00000000,
6880  DIG_RANDOM_PATTERN_RESETED               = 0x00000001,
6881  } DIG_TEST_PATTERN_RANDOM_PATTERN_RESET;
6882  
6883  /*
6884   * DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN enum
6885   */
6886  
6887  typedef enum DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN {
6888  DIG_IN_NORMAL_OPERATION                  = 0x00000000,
6889  DIG_IN_DEBUG_MODE                        = 0x00000001,
6890  } DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN;
6891  
6892  /*
6893   * DOLBY_VISION_ENABLE enum
6894   */
6895  
6896  typedef enum DOLBY_VISION_ENABLE {
6897  DOLBY_VISION_DISABLED                    = 0x00000000,
6898  DOLBY_VISION_ENABLED                     = 0x00000001,
6899  } DOLBY_VISION_ENABLE;
6900  
6901  /*
6902   * HDMI_ACP_SEND enum
6903   */
6904  
6905  typedef enum HDMI_ACP_SEND {
6906  HDMI_ACP_NOT_SEND                        = 0x00000000,
6907  HDMI_ACP_PKT_SEND                        = 0x00000001,
6908  } HDMI_ACP_SEND;
6909  
6910  /*
6911   * HDMI_ACR_AUDIO_PRIORITY enum
6912   */
6913  
6914  typedef enum HDMI_ACR_AUDIO_PRIORITY {
6915  HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0x00000000,
6916  HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 0x00000001,
6917  } HDMI_ACR_AUDIO_PRIORITY;
6918  
6919  /*
6920   * HDMI_ACR_CONT enum
6921   */
6922  
6923  typedef enum HDMI_ACR_CONT {
6924  HDMI_ACR_CONT_DISABLE                    = 0x00000000,
6925  HDMI_ACR_CONT_ENABLE                     = 0x00000001,
6926  } HDMI_ACR_CONT;
6927  
6928  /*
6929   * HDMI_ACR_N_MULTIPLE enum
6930   */
6931  
6932  typedef enum HDMI_ACR_N_MULTIPLE {
6933  HDMI_ACR_0_MULTIPLE_RESERVED             = 0x00000000,
6934  HDMI_ACR_1_MULTIPLE                      = 0x00000001,
6935  HDMI_ACR_2_MULTIPLE                      = 0x00000002,
6936  HDMI_ACR_3_MULTIPLE_RESERVED             = 0x00000003,
6937  HDMI_ACR_4_MULTIPLE                      = 0x00000004,
6938  HDMI_ACR_5_MULTIPLE_RESERVED             = 0x00000005,
6939  HDMI_ACR_6_MULTIPLE_RESERVED             = 0x00000006,
6940  HDMI_ACR_7_MULTIPLE_RESERVED             = 0x00000007,
6941  } HDMI_ACR_N_MULTIPLE;
6942  
6943  /*
6944   * HDMI_ACR_SELECT enum
6945   */
6946  
6947  typedef enum HDMI_ACR_SELECT {
6948  HDMI_ACR_SELECT_HW                       = 0x00000000,
6949  HDMI_ACR_SELECT_32K                      = 0x00000001,
6950  HDMI_ACR_SELECT_44K                      = 0x00000002,
6951  HDMI_ACR_SELECT_48K                      = 0x00000003,
6952  } HDMI_ACR_SELECT;
6953  
6954  /*
6955   * HDMI_ACR_SEND enum
6956   */
6957  
6958  typedef enum HDMI_ACR_SEND {
6959  HDMI_ACR_NOT_SEND                        = 0x00000000,
6960  HDMI_ACR_PKT_SEND                        = 0x00000001,
6961  } HDMI_ACR_SEND;
6962  
6963  /*
6964   * HDMI_ACR_SOURCE enum
6965   */
6966  
6967  typedef enum HDMI_ACR_SOURCE {
6968  HDMI_ACR_SOURCE_HW                       = 0x00000000,
6969  HDMI_ACR_SOURCE_SW                       = 0x00000001,
6970  } HDMI_ACR_SOURCE;
6971  
6972  /*
6973   * HDMI_AUDIO_DELAY_EN enum
6974   */
6975  
6976  typedef enum HDMI_AUDIO_DELAY_EN {
6977  HDMI_AUDIO_DELAY_DISABLE                 = 0x00000000,
6978  HDMI_AUDIO_DELAY_58CLK                   = 0x00000001,
6979  HDMI_AUDIO_DELAY_56CLK                   = 0x00000002,
6980  HDMI_AUDIO_DELAY_RESERVED                = 0x00000003,
6981  } HDMI_AUDIO_DELAY_EN;
6982  
6983  /*
6984   * HDMI_AUDIO_INFO_CONT enum
6985   */
6986  
6987  typedef enum HDMI_AUDIO_INFO_CONT {
6988  HDMI_AUDIO_INFO_CONT_DISABLE             = 0x00000000,
6989  HDMI_AUDIO_INFO_CONT_ENABLE              = 0x00000001,
6990  } HDMI_AUDIO_INFO_CONT;
6991  
6992  /*
6993   * HDMI_AUDIO_INFO_SEND enum
6994   */
6995  
6996  typedef enum HDMI_AUDIO_INFO_SEND {
6997  HDMI_AUDIO_INFO_NOT_SEND                 = 0x00000000,
6998  HDMI_AUDIO_INFO_PKT_SEND                 = 0x00000001,
6999  } HDMI_AUDIO_INFO_SEND;
7000  
7001  /*
7002   * HDMI_CLOCK_CHANNEL_RATE enum
7003   */
7004  
7005  typedef enum HDMI_CLOCK_CHANNEL_RATE {
7006  HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE = 0x00000000,
7007  HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE = 0x00000001,
7008  } HDMI_CLOCK_CHANNEL_RATE;
7009  
7010  /*
7011   * HDMI_DATA_SCRAMBLE_EN enum
7012   */
7013  
7014  typedef enum HDMI_DATA_SCRAMBLE_EN {
7015  HDMI_DATA_SCRAMBLE_DISABLE               = 0x00000000,
7016  HDMI_DATA_SCRAMBLE_ENABLE                = 0x00000001,
7017  } HDMI_DATA_SCRAMBLE_EN;
7018  
7019  /*
7020   * HDMI_DEEP_COLOR_DEPTH enum
7021   */
7022  
7023  typedef enum HDMI_DEEP_COLOR_DEPTH {
7024  HDMI_DEEP_COLOR_DEPTH_24BPP              = 0x00000000,
7025  HDMI_DEEP_COLOR_DEPTH_30BPP              = 0x00000001,
7026  HDMI_DEEP_COLOR_DEPTH_36BPP              = 0x00000002,
7027  HDMI_DEEP_COLOR_DEPTH_48BPP              = 0x00000003,
7028  } HDMI_DEEP_COLOR_DEPTH;
7029  
7030  /*
7031   * HDMI_DEFAULT_PAHSE enum
7032   */
7033  
7034  typedef enum HDMI_DEFAULT_PAHSE {
7035  HDMI_DEFAULT_PHASE_IS_0                  = 0x00000000,
7036  HDMI_DEFAULT_PHASE_IS_1                  = 0x00000001,
7037  } HDMI_DEFAULT_PAHSE;
7038  
7039  /*
7040   * HDMI_ERROR_ACK enum
7041   */
7042  
7043  typedef enum HDMI_ERROR_ACK {
7044  HDMI_ERROR_ACK_INT                       = 0x00000000,
7045  HDMI_ERROR_NOT_ACK                       = 0x00000001,
7046  } HDMI_ERROR_ACK;
7047  
7048  /*
7049   * HDMI_ERROR_MASK enum
7050   */
7051  
7052  typedef enum HDMI_ERROR_MASK {
7053  HDMI_ERROR_MASK_INT                      = 0x00000000,
7054  HDMI_ERROR_NOT_MASK                      = 0x00000001,
7055  } HDMI_ERROR_MASK;
7056  
7057  /*
7058   * HDMI_GC_AVMUTE enum
7059   */
7060  
7061  typedef enum HDMI_GC_AVMUTE {
7062  HDMI_GC_AVMUTE_SET                       = 0x00000000,
7063  HDMI_GC_AVMUTE_UNSET                     = 0x00000001,
7064  } HDMI_GC_AVMUTE;
7065  
7066  /*
7067   * HDMI_GC_AVMUTE_CONT enum
7068   */
7069  
7070  typedef enum HDMI_GC_AVMUTE_CONT {
7071  HDMI_GC_AVMUTE_CONT_DISABLE              = 0x00000000,
7072  HDMI_GC_AVMUTE_CONT_ENABLE               = 0x00000001,
7073  } HDMI_GC_AVMUTE_CONT;
7074  
7075  /*
7076   * HDMI_GC_CONT enum
7077   */
7078  
7079  typedef enum HDMI_GC_CONT {
7080  HDMI_GC_CONT_DISABLE                     = 0x00000000,
7081  HDMI_GC_CONT_ENABLE                      = 0x00000001,
7082  } HDMI_GC_CONT;
7083  
7084  /*
7085   * HDMI_GC_SEND enum
7086   */
7087  
7088  typedef enum HDMI_GC_SEND {
7089  HDMI_GC_NOT_SEND                         = 0x00000000,
7090  HDMI_GC_PKT_SEND                         = 0x00000001,
7091  } HDMI_GC_SEND;
7092  
7093  /*
7094   * HDMI_GENERIC_CONT enum
7095   */
7096  
7097  typedef enum HDMI_GENERIC_CONT {
7098  HDMI_GENERIC_CONT_DISABLE                = 0x00000000,
7099  HDMI_GENERIC_CONT_ENABLE                 = 0x00000001,
7100  } HDMI_GENERIC_CONT;
7101  
7102  /*
7103   * HDMI_GENERIC_SEND enum
7104   */
7105  
7106  typedef enum HDMI_GENERIC_SEND {
7107  HDMI_GENERIC_NOT_SEND                    = 0x00000000,
7108  HDMI_GENERIC_PKT_SEND                    = 0x00000001,
7109  } HDMI_GENERIC_SEND;
7110  
7111  /*
7112   * HDMI_ISRC_CONT enum
7113   */
7114  
7115  typedef enum HDMI_ISRC_CONT {
7116  HDMI_ISRC_CONT_DISABLE                   = 0x00000000,
7117  HDMI_ISRC_CONT_ENABLE                    = 0x00000001,
7118  } HDMI_ISRC_CONT;
7119  
7120  /*
7121   * HDMI_ISRC_SEND enum
7122   */
7123  
7124  typedef enum HDMI_ISRC_SEND {
7125  HDMI_ISRC_NOT_SEND                       = 0x00000000,
7126  HDMI_ISRC_PKT_SEND                       = 0x00000001,
7127  } HDMI_ISRC_SEND;
7128  
7129  /*
7130   * HDMI_KEEPOUT_MODE enum
7131   */
7132  
7133  typedef enum HDMI_KEEPOUT_MODE {
7134  HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC        = 0x00000000,
7135  HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC      = 0x00000001,
7136  } HDMI_KEEPOUT_MODE;
7137  
7138  /*
7139   * HDMI_METADATA_ENABLE enum
7140   */
7141  
7142  typedef enum HDMI_METADATA_ENABLE {
7143  HDMI_METADATA_NOT_SEND                   = 0x00000000,
7144  HDMI_METADATA_PKT_SEND                   = 0x00000001,
7145  } HDMI_METADATA_ENABLE;
7146  
7147  /*
7148   * HDMI_MPEG_INFO_CONT enum
7149   */
7150  
7151  typedef enum HDMI_MPEG_INFO_CONT {
7152  HDMI_MPEG_INFO_CONT_DISABLE              = 0x00000000,
7153  HDMI_MPEG_INFO_CONT_ENABLE               = 0x00000001,
7154  } HDMI_MPEG_INFO_CONT;
7155  
7156  /*
7157   * HDMI_MPEG_INFO_SEND enum
7158   */
7159  
7160  typedef enum HDMI_MPEG_INFO_SEND {
7161  HDMI_MPEG_INFO_NOT_SEND                  = 0x00000000,
7162  HDMI_MPEG_INFO_PKT_SEND                  = 0x00000001,
7163  } HDMI_MPEG_INFO_SEND;
7164  
7165  /*
7166   * HDMI_NO_EXTRA_NULL_PACKET_FILLED enum
7167   */
7168  
7169  typedef enum HDMI_NO_EXTRA_NULL_PACKET_FILLED {
7170  HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE     = 0x00000000,
7171  HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE    = 0x00000001,
7172  } HDMI_NO_EXTRA_NULL_PACKET_FILLED;
7173  
7174  /*
7175   * HDMI_NULL_SEND enum
7176   */
7177  
7178  typedef enum HDMI_NULL_SEND {
7179  HDMI_NULL_NOT_SEND                       = 0x00000000,
7180  HDMI_NULL_PKT_SEND                       = 0x00000001,
7181  } HDMI_NULL_SEND;
7182  
7183  /*
7184   * HDMI_PACKET_GEN_VERSION enum
7185   */
7186  
7187  typedef enum HDMI_PACKET_GEN_VERSION {
7188  HDMI_PACKET_GEN_VERSION_OLD              = 0x00000000,
7189  HDMI_PACKET_GEN_VERSION_NEW              = 0x00000001,
7190  } HDMI_PACKET_GEN_VERSION;
7191  
7192  /*
7193   * HDMI_PACKET_LINE_REFERENCE enum
7194   */
7195  
7196  typedef enum HDMI_PACKET_LINE_REFERENCE {
7197  HDMI_PKT_LINE_REF_VSYNC                  = 0x00000000,
7198  HDMI_PKT_LINE_REF_OTGSOF                 = 0x00000001,
7199  } HDMI_PACKET_LINE_REFERENCE;
7200  
7201  /*
7202   * HDMI_PACKING_PHASE_OVERRIDE enum
7203   */
7204  
7205  typedef enum HDMI_PACKING_PHASE_OVERRIDE {
7206  HDMI_PACKING_PHASE_SET_BY_HW             = 0x00000000,
7207  HDMI_PACKING_PHASE_SET_BY_SW             = 0x00000001,
7208  } HDMI_PACKING_PHASE_OVERRIDE;
7209  
7210  /*
7211   * LVTMA_RANDOM_PATTERN_SEED_RAN_PAT enum
7212   */
7213  
7214  typedef enum LVTMA_RANDOM_PATTERN_SEED_RAN_PAT {
7215  LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS     = 0x00000000,
7216  LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH   = 0x00000001,
7217  } LVTMA_RANDOM_PATTERN_SEED_RAN_PAT;
7218  
7219  /*
7220   * TMDS_COLOR_FORMAT enum
7221   */
7222  
7223  typedef enum TMDS_COLOR_FORMAT {
7224  TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP = 0x00000000,
7225  TMDS_COLOR_FORMAT_TWIN30BPP_LSB          = 0x00000001,
7226  TMDS_COLOR_FORMAT_DUAL30BPP              = 0x00000002,
7227  TMDS_COLOR_FORMAT_RESERVED               = 0x00000003,
7228  } TMDS_COLOR_FORMAT;
7229  
7230  /*
7231   * TMDS_CTL0_DATA_INVERT enum
7232   */
7233  
7234  typedef enum TMDS_CTL0_DATA_INVERT {
7235  TMDS_CTL0_DATA_NORMAL                    = 0x00000000,
7236  TMDS_CTL0_DATA_INVERT_EN                 = 0x00000001,
7237  } TMDS_CTL0_DATA_INVERT;
7238  
7239  /*
7240   * TMDS_CTL0_DATA_MODULATION enum
7241   */
7242  
7243  typedef enum TMDS_CTL0_DATA_MODULATION {
7244  TMDS_CTL0_DATA_MODULATION_DISABLE        = 0x00000000,
7245  TMDS_CTL0_DATA_MODULATION_BIT0           = 0x00000001,
7246  TMDS_CTL0_DATA_MODULATION_BIT1           = 0x00000002,
7247  TMDS_CTL0_DATA_MODULATION_BIT2           = 0x00000003,
7248  } TMDS_CTL0_DATA_MODULATION;
7249  
7250  /*
7251   * TMDS_CTL0_DATA_SEL enum
7252   */
7253  
7254  typedef enum TMDS_CTL0_DATA_SEL {
7255  TMDS_CTL0_DATA_SEL0_RESERVED             = 0x00000000,
7256  TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE       = 0x00000001,
7257  TMDS_CTL0_DATA_SEL2_VSYNC                = 0x00000002,
7258  TMDS_CTL0_DATA_SEL3_RESERVED             = 0x00000003,
7259  TMDS_CTL0_DATA_SEL4_HSYNC                = 0x00000004,
7260  TMDS_CTL0_DATA_SEL5_SEL7_RESERVED        = 0x00000005,
7261  TMDS_CTL0_DATA_SEL8_RANDOM_DATA          = 0x00000006,
7262  TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA    = 0x00000007,
7263  } TMDS_CTL0_DATA_SEL;
7264  
7265  /*
7266   * TMDS_CTL0_PATTERN_OUT_EN enum
7267   */
7268  
7269  typedef enum TMDS_CTL0_PATTERN_OUT_EN {
7270  TMDS_CTL0_PATTERN_OUT_DISABLE            = 0x00000000,
7271  TMDS_CTL0_PATTERN_OUT_ENABLE             = 0x00000001,
7272  } TMDS_CTL0_PATTERN_OUT_EN;
7273  
7274  /*
7275   * TMDS_CTL1_DATA_INVERT enum
7276   */
7277  
7278  typedef enum TMDS_CTL1_DATA_INVERT {
7279  TMDS_CTL1_DATA_NORMAL                    = 0x00000000,
7280  TMDS_CTL1_DATA_INVERT_EN                 = 0x00000001,
7281  } TMDS_CTL1_DATA_INVERT;
7282  
7283  /*
7284   * TMDS_CTL1_DATA_MODULATION enum
7285   */
7286  
7287  typedef enum TMDS_CTL1_DATA_MODULATION {
7288  TMDS_CTL1_DATA_MODULATION_DISABLE        = 0x00000000,
7289  TMDS_CTL1_DATA_MODULATION_BIT0           = 0x00000001,
7290  TMDS_CTL1_DATA_MODULATION_BIT1           = 0x00000002,
7291  TMDS_CTL1_DATA_MODULATION_BIT2           = 0x00000003,
7292  } TMDS_CTL1_DATA_MODULATION;
7293  
7294  /*
7295   * TMDS_CTL1_DATA_SEL enum
7296   */
7297  
7298  typedef enum TMDS_CTL1_DATA_SEL {
7299  TMDS_CTL1_DATA_SEL0_RESERVED             = 0x00000000,
7300  TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE       = 0x00000001,
7301  TMDS_CTL1_DATA_SEL2_VSYNC                = 0x00000002,
7302  TMDS_CTL1_DATA_SEL3_RESERVED             = 0x00000003,
7303  TMDS_CTL1_DATA_SEL4_HSYNC                = 0x00000004,
7304  TMDS_CTL1_DATA_SEL5_SEL7_RESERVED        = 0x00000005,
7305  TMDS_CTL1_DATA_SEL8_BLANK_TIME           = 0x00000006,
7306  TMDS_CTL1_DATA_SEL9_SEL15_RESERVED       = 0x00000007,
7307  } TMDS_CTL1_DATA_SEL;
7308  
7309  /*
7310   * TMDS_CTL1_PATTERN_OUT_EN enum
7311   */
7312  
7313  typedef enum TMDS_CTL1_PATTERN_OUT_EN {
7314  TMDS_CTL1_PATTERN_OUT_DISABLE            = 0x00000000,
7315  TMDS_CTL1_PATTERN_OUT_ENABLE             = 0x00000001,
7316  } TMDS_CTL1_PATTERN_OUT_EN;
7317  
7318  /*
7319   * TMDS_CTL2_DATA_INVERT enum
7320   */
7321  
7322  typedef enum TMDS_CTL2_DATA_INVERT {
7323  TMDS_CTL2_DATA_NORMAL                    = 0x00000000,
7324  TMDS_CTL2_DATA_INVERT_EN                 = 0x00000001,
7325  } TMDS_CTL2_DATA_INVERT;
7326  
7327  /*
7328   * TMDS_CTL2_DATA_MODULATION enum
7329   */
7330  
7331  typedef enum TMDS_CTL2_DATA_MODULATION {
7332  TMDS_CTL2_DATA_MODULATION_DISABLE        = 0x00000000,
7333  TMDS_CTL2_DATA_MODULATION_BIT0           = 0x00000001,
7334  TMDS_CTL2_DATA_MODULATION_BIT1           = 0x00000002,
7335  TMDS_CTL2_DATA_MODULATION_BIT2           = 0x00000003,
7336  } TMDS_CTL2_DATA_MODULATION;
7337  
7338  /*
7339   * TMDS_CTL2_DATA_SEL enum
7340   */
7341  
7342  typedef enum TMDS_CTL2_DATA_SEL {
7343  TMDS_CTL2_DATA_SEL0_RESERVED             = 0x00000000,
7344  TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE       = 0x00000001,
7345  TMDS_CTL2_DATA_SEL2_VSYNC                = 0x00000002,
7346  TMDS_CTL2_DATA_SEL3_RESERVED             = 0x00000003,
7347  TMDS_CTL2_DATA_SEL4_HSYNC                = 0x00000004,
7348  TMDS_CTL2_DATA_SEL5_SEL7_RESERVED        = 0x00000005,
7349  TMDS_CTL2_DATA_SEL8_BLANK_TIME           = 0x00000006,
7350  TMDS_CTL2_DATA_SEL9_SEL15_RESERVED       = 0x00000007,
7351  } TMDS_CTL2_DATA_SEL;
7352  
7353  /*
7354   * TMDS_CTL2_PATTERN_OUT_EN enum
7355   */
7356  
7357  typedef enum TMDS_CTL2_PATTERN_OUT_EN {
7358  TMDS_CTL2_PATTERN_OUT_DISABLE            = 0x00000000,
7359  TMDS_CTL2_PATTERN_OUT_ENABLE             = 0x00000001,
7360  } TMDS_CTL2_PATTERN_OUT_EN;
7361  
7362  /*
7363   * TMDS_CTL3_DATA_INVERT enum
7364   */
7365  
7366  typedef enum TMDS_CTL3_DATA_INVERT {
7367  TMDS_CTL3_DATA_NORMAL                    = 0x00000000,
7368  TMDS_CTL3_DATA_INVERT_EN                 = 0x00000001,
7369  } TMDS_CTL3_DATA_INVERT;
7370  
7371  /*
7372   * TMDS_CTL3_DATA_MODULATION enum
7373   */
7374  
7375  typedef enum TMDS_CTL3_DATA_MODULATION {
7376  TMDS_CTL3_DATA_MODULATION_DISABLE        = 0x00000000,
7377  TMDS_CTL3_DATA_MODULATION_BIT0           = 0x00000001,
7378  TMDS_CTL3_DATA_MODULATION_BIT1           = 0x00000002,
7379  TMDS_CTL3_DATA_MODULATION_BIT2           = 0x00000003,
7380  } TMDS_CTL3_DATA_MODULATION;
7381  
7382  /*
7383   * TMDS_CTL3_DATA_SEL enum
7384   */
7385  
7386  typedef enum TMDS_CTL3_DATA_SEL {
7387  TMDS_CTL3_DATA_SEL0_RESERVED             = 0x00000000,
7388  TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE       = 0x00000001,
7389  TMDS_CTL3_DATA_SEL2_VSYNC                = 0x00000002,
7390  TMDS_CTL3_DATA_SEL3_RESERVED             = 0x00000003,
7391  TMDS_CTL3_DATA_SEL4_HSYNC                = 0x00000004,
7392  TMDS_CTL3_DATA_SEL5_SEL7_RESERVED        = 0x00000005,
7393  TMDS_CTL3_DATA_SEL8_BLANK_TIME           = 0x00000006,
7394  TMDS_CTL3_DATA_SEL9_SEL15_RESERVED       = 0x00000007,
7395  } TMDS_CTL3_DATA_SEL;
7396  
7397  /*
7398   * TMDS_CTL3_PATTERN_OUT_EN enum
7399   */
7400  
7401  typedef enum TMDS_CTL3_PATTERN_OUT_EN {
7402  TMDS_CTL3_PATTERN_OUT_DISABLE            = 0x00000000,
7403  TMDS_CTL3_PATTERN_OUT_ENABLE             = 0x00000001,
7404  } TMDS_CTL3_PATTERN_OUT_EN;
7405  
7406  /*
7407   * TMDS_DATA_SYNCHRONIZATION_DSINTSEL enum
7408   */
7409  
7410  typedef enum TMDS_DATA_SYNCHRONIZATION_DSINTSEL {
7411  TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS = 0x00000000,
7412  TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL = 0x00000001,
7413  } TMDS_DATA_SYNCHRONIZATION_DSINTSEL;
7414  
7415  /*
7416   * TMDS_PIXEL_ENCODING enum
7417   */
7418  
7419  typedef enum TMDS_PIXEL_ENCODING {
7420  TMDS_PIXEL_ENCODING_444_OR_420           = 0x00000000,
7421  TMDS_PIXEL_ENCODING_422                  = 0x00000001,
7422  } TMDS_PIXEL_ENCODING;
7423  
7424  /*
7425   * TMDS_REG_TEST_OUTPUTA_CNTLA enum
7426   */
7427  
7428  typedef enum TMDS_REG_TEST_OUTPUTA_CNTLA {
7429  TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0      = 0x00000000,
7430  TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1      = 0x00000001,
7431  TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2      = 0x00000002,
7432  TMDS_REG_TEST_OUTPUTA_CNTLA_NA           = 0x00000003,
7433  } TMDS_REG_TEST_OUTPUTA_CNTLA;
7434  
7435  /*
7436   * TMDS_REG_TEST_OUTPUTB_CNTLB enum
7437   */
7438  
7439  typedef enum TMDS_REG_TEST_OUTPUTB_CNTLB {
7440  TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0      = 0x00000000,
7441  TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1      = 0x00000001,
7442  TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2      = 0x00000002,
7443  TMDS_REG_TEST_OUTPUTB_CNTLB_NA           = 0x00000003,
7444  } TMDS_REG_TEST_OUTPUTB_CNTLB;
7445  
7446  /*
7447   * TMDS_STEREOSYNC_CTL_SEL_REG enum
7448   */
7449  
7450  typedef enum TMDS_STEREOSYNC_CTL_SEL_REG {
7451  TMDS_STEREOSYNC_CTL0                     = 0x00000000,
7452  TMDS_STEREOSYNC_CTL1                     = 0x00000001,
7453  TMDS_STEREOSYNC_CTL2                     = 0x00000002,
7454  TMDS_STEREOSYNC_CTL3                     = 0x00000003,
7455  } TMDS_STEREOSYNC_CTL_SEL_REG;
7456  
7457  /*
7458   * TMDS_SYNC_PHASE enum
7459   */
7460  
7461  typedef enum TMDS_SYNC_PHASE {
7462  TMDS_NOT_SYNC_PHASE_ON_FRAME_START       = 0x00000000,
7463  TMDS_SYNC_PHASE_ON_FRAME_START           = 0x00000001,
7464  } TMDS_SYNC_PHASE;
7465  
7466  /*
7467   * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA enum
7468   */
7469  
7470  typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA {
7471  TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT    = 0x00000000,
7472  TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT  = 0x00000001,
7473  } TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA;
7474  
7475  /*
7476   * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB enum
7477   */
7478  
7479  typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB {
7480  TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT    = 0x00000000,
7481  TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT  = 0x00000001,
7482  } TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB;
7483  
7484  /*
7485   * TMDS_TRANSMITTER_CONTROL_IDSCKSELA enum
7486   */
7487  
7488  typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELA {
7489  TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK   = 0x00000000,
7490  TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK     = 0x00000001,
7491  } TMDS_TRANSMITTER_CONTROL_IDSCKSELA;
7492  
7493  /*
7494   * TMDS_TRANSMITTER_CONTROL_IDSCKSELB enum
7495   */
7496  
7497  typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELB {
7498  TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK   = 0x00000000,
7499  TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK     = 0x00000001,
7500  } TMDS_TRANSMITTER_CONTROL_IDSCKSELB;
7501  
7502  /*
7503   * TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN enum
7504   */
7505  
7506  typedef enum TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN {
7507  TMDS_TRANSMITTER_PLLSEL_BY_HW            = 0x00000000,
7508  TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW  = 0x00000001,
7509  } TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN;
7510  
7511  /*
7512   * TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK enum
7513   */
7514  
7515  typedef enum TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK {
7516  TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE = 0x00000000,
7517  TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON = 0x00000001,
7518  TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON = 0x00000002,
7519  TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE = 0x00000003,
7520  } TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK;
7521  
7522  /*
7523   * TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN enum
7524   */
7525  
7526  typedef enum TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN {
7527  TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE   = 0x00000000,
7528  TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE    = 0x00000001,
7529  } TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN;
7530  
7531  /*
7532   * TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK enum
7533   */
7534  
7535  typedef enum TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK {
7536  TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD      = 0x00000000,
7537  TMDS_TRANSMITTER_PLL_RST_ON_HPD          = 0x00000001,
7538  } TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK;
7539  
7540  /*
7541   * TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS enum
7542   */
7543  
7544  typedef enum TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS {
7545  TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK   = 0x00000000,
7546  TMDS_TRANSMITTER_TDCLK_FROM_PADS         = 0x00000001,
7547  } TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS;
7548  
7549  /*
7550   * TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS enum
7551   */
7552  
7553  typedef enum TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS {
7554  TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK   = 0x00000000,
7555  TMDS_TRANSMITTER_TMCLK_FROM_PADS         = 0x00000001,
7556  } TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS;
7557  
7558  /*
7559   * TMDS_TRANSMITTER_ENABLE_HPD_MASK enum
7560   */
7561  
7562  typedef enum TMDS_TRANSMITTER_ENABLE_HPD_MASK {
7563  TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE   = 0x00000000,
7564  TMDS_TRANSMITTER_HPD_MASK_OVERRIDE       = 0x00000001,
7565  } TMDS_TRANSMITTER_ENABLE_HPD_MASK;
7566  
7567  /*
7568   * TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK enum
7569   */
7570  
7571  typedef enum TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK {
7572  TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE = 0x00000000,
7573  TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE = 0x00000001,
7574  } TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK;
7575  
7576  /*
7577   * TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK enum
7578   */
7579  
7580  typedef enum TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK {
7581  TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE = 0x00000000,
7582  TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE = 0x00000001,
7583  } TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK;
7584  
7585  /*******************************************************
7586   * DP_AUX Enums
7587   *******************************************************/
7588  
7589  /*
7590   * DP_AUX_ARB_CONTROL_ARB_PRIORITY enum
7591   */
7592  
7593  typedef enum DP_AUX_ARB_CONTROL_ARB_PRIORITY {
7594  DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW = 0x00000000,
7595  DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW = 0x00000001,
7596  DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC = 0x00000002,
7597  DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS = 0x00000003,
7598  } DP_AUX_ARB_CONTROL_ARB_PRIORITY;
7599  
7600  /*
7601   * DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG enum
7602   */
7603  
7604  typedef enum DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG {
7605  DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0x00000000,
7606  DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG   = 0x00000001,
7607  } DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG;
7608  
7609  /*
7610   * DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ enum
7611   */
7612  
7613  typedef enum DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ {
7614  DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ  = 0x00000000,
7615  DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ      = 0x00000001,
7616  } DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ;
7617  
7618  /*
7619   * DP_AUX_ARB_STATUS enum
7620   */
7621  
7622  typedef enum DP_AUX_ARB_STATUS {
7623  DP_AUX_IDLE                              = 0x00000000,
7624  DP_AUX_IN_USE_LS                         = 0x00000001,
7625  DP_AUX_IN_USE_GTC                        = 0x00000002,
7626  DP_AUX_IN_USE_SW                         = 0x00000003,
7627  DP_AUX_IN_USE_PHYWAKE                    = 0x00000004,
7628  } DP_AUX_ARB_STATUS;
7629  
7630  /*
7631   * DP_AUX_CONTROL_HPD_SEL enum
7632   */
7633  
7634  typedef enum DP_AUX_CONTROL_HPD_SEL {
7635  DP_AUX_CONTROL_HPD1_SELECTED             = 0x00000000,
7636  DP_AUX_CONTROL_HPD2_SELECTED             = 0x00000001,
7637  DP_AUX_CONTROL_HPD3_SELECTED             = 0x00000002,
7638  DP_AUX_CONTROL_HPD4_SELECTED             = 0x00000003,
7639  DP_AUX_CONTROL_HPD5_SELECTED             = 0x00000004,
7640  DP_AUX_CONTROL_NO_HPD_SELECTED           = 0x00000005,
7641  } DP_AUX_CONTROL_HPD_SEL;
7642  
7643  /*
7644   * DP_AUX_CONTROL_TEST_MODE enum
7645   */
7646  
7647  typedef enum DP_AUX_CONTROL_TEST_MODE {
7648  DP_AUX_CONTROL_TEST_MODE_DISABLE         = 0x00000000,
7649  DP_AUX_CONTROL_TEST_MODE_ENABLE          = 0x00000001,
7650  } DP_AUX_CONTROL_TEST_MODE;
7651  
7652  /*
7653   * DP_AUX_DEFINITE_ERR_REACHED_ACK enum
7654   */
7655  
7656  typedef enum DP_AUX_DEFINITE_ERR_REACHED_ACK {
7657  ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0x00000000,
7658  ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK    = 0x00000001,
7659  } DP_AUX_DEFINITE_ERR_REACHED_ACK;
7660  
7661  /*
7662   * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT enum
7663   */
7664  
7665  typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT {
7666  DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00000000,
7667  DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00000001,
7668  } DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT;
7669  
7670  /*
7671   * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START enum
7672   */
7673  
7674  typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START {
7675  DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START = 0x00000000,
7676  DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START = 0x00000001,
7677  } DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START;
7678  
7679  /*
7680   * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP enum
7681   */
7682  
7683  typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP {
7684  DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP = 0x00000000,
7685  DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP = 0x00000001,
7686  } DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP;
7687  
7688  /*
7689   * DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN enum
7690   */
7691  
7692  typedef enum DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN {
7693  DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES = 0x00000000,
7694  DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES = 0x00000001,
7695  DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES = 0x00000002,
7696  DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED = 0x00000003,
7697  } DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN;
7698  
7699  /*
7700   * DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN enum
7701   */
7702  
7703  typedef enum DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN {
7704  DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS = 0x00000000,
7705  DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS = 0x00000001,
7706  DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS = 0x00000002,
7707  DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS = 0x00000003,
7708  } DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN;
7709  
7710  /*
7711   * DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW enum
7712   */
7713  
7714  typedef enum DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW {
7715  DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD = 0x00000000,
7716  DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD = 0x00000001,
7717  DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD = 0x00000002,
7718  DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD = 0x00000003,
7719  DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD = 0x00000004,
7720  DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD = 0x00000005,
7721  DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD = 0x00000006,
7722  DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD = 0x00000007,
7723  } DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW;
7724  
7725  /*
7726   * DP_AUX_DPHY_RX_CONTROL_START_WINDOW enum
7727   */
7728  
7729  typedef enum DP_AUX_DPHY_RX_CONTROL_START_WINDOW {
7730  DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0x00000000,
7731  DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 0x00000001,
7732  DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 0x00000002,
7733  DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD = 0x00000003,
7734  DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD = 0x00000004,
7735  DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD = 0x00000005,
7736  DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD = 0x00000006,
7737  DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD = 0x00000007,
7738  } DP_AUX_DPHY_RX_CONTROL_START_WINDOW;
7739  
7740  /*
7741   * DP_AUX_DPHY_RX_DETECTION_THRESHOLD enum
7742   */
7743  
7744  typedef enum DP_AUX_DPHY_RX_DETECTION_THRESHOLD {
7745  DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 = 0x00000000,
7746  DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 = 0x00000001,
7747  DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 = 0x00000002,
7748  DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 = 0x00000003,
7749  DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 = 0x00000004,
7750  DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 = 0x00000005,
7751  DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 = 0x00000006,
7752  DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 = 0x00000007,
7753  } DP_AUX_DPHY_RX_DETECTION_THRESHOLD;
7754  
7755  /*
7756   * DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY enum
7757   */
7758  
7759  typedef enum DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY {
7760  DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0x00000000,
7761  DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US = 0x00000001,
7762  DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US = 0x00000002,
7763  DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US = 0x00000003,
7764  DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US = 0x00000004,
7765  DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US = 0x00000005,
7766  } DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY;
7767  
7768  /*
7769   * DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE enum
7770   */
7771  
7772  typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE {
7773  DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0x00000000,
7774  DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 0x00000001,
7775  DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 0x00000002,
7776  DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 0x00000003,
7777  } DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE;
7778  
7779  /*
7780   * DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL enum
7781   */
7782  
7783  typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL {
7784  DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK = 0x00000000,
7785  DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF = 0x00000001,
7786  } DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL;
7787  
7788  /*
7789   * DP_AUX_ERR_OCCURRED_ACK enum
7790   */
7791  
7792  typedef enum DP_AUX_ERR_OCCURRED_ACK {
7793  DP_AUX_ERR_OCCURRED__NOT_ACK             = 0x00000000,
7794  DP_AUX_ERR_OCCURRED__ACK                 = 0x00000001,
7795  } DP_AUX_ERR_OCCURRED_ACK;
7796  
7797  /*
7798   * DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ enum
7799   */
7800  
7801  typedef enum DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ {
7802  DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX = 0x00000000,
7803  DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX = 0x00000001,
7804  } DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ;
7805  
7806  /*
7807   * DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW enum
7808   */
7809  
7810  typedef enum DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW {
7811  DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US = 0x00000000,
7812  DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US = 0x00000001,
7813  DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US = 0x00000002,
7814  DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US = 0x00000003,
7815  } DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW;
7816  
7817  /*
7818   * DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT enum
7819   */
7820  
7821  typedef enum DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT {
7822  DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS = 0x00000000,
7823  DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS = 0x00000001,
7824  DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS = 0x00000002,
7825  DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED = 0x00000003,
7826  } DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT;
7827  
7828  /*
7829   * DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN enum
7830   */
7831  
7832  typedef enum DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN {
7833  DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0 = 0x00000000,
7834  DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64 = 0x00000001,
7835  DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128 = 0x00000002,
7836  DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256 = 0x00000003,
7837  } DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN;
7838  
7839  /*
7840   * DP_AUX_INT_ACK enum
7841   */
7842  
7843  typedef enum DP_AUX_INT_ACK {
7844  DP_AUX_INT__NOT_ACK                      = 0x00000000,
7845  DP_AUX_INT__ACK                          = 0x00000001,
7846  } DP_AUX_INT_ACK;
7847  
7848  /*
7849   * DP_AUX_LS_UPDATE_ACK enum
7850   */
7851  
7852  typedef enum DP_AUX_LS_UPDATE_ACK {
7853  DP_AUX_INT_LS_UPDATE_NOT_ACK             = 0x00000000,
7854  DP_AUX_INT_LS_UPDATE_ACK                 = 0x00000001,
7855  } DP_AUX_LS_UPDATE_ACK;
7856  
7857  /*
7858   * DP_AUX_PHY_WAKE_PRIORITY enum
7859   */
7860  
7861  typedef enum DP_AUX_PHY_WAKE_PRIORITY {
7862  DP_AUX_PHY_WAKE_HIGH_PRIORITY            = 0x00000000,
7863  DP_AUX_PHY_WAKE_LOW_PRIORITY             = 0x00000001,
7864  } DP_AUX_PHY_WAKE_PRIORITY;
7865  
7866  /*
7867   * DP_AUX_POTENTIAL_ERR_REACHED_ACK enum
7868   */
7869  
7870  typedef enum DP_AUX_POTENTIAL_ERR_REACHED_ACK {
7871  DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK    = 0x00000000,
7872  DP_AUX_POTENTIAL_ERR_REACHED__ACK        = 0x00000001,
7873  } DP_AUX_POTENTIAL_ERR_REACHED_ACK;
7874  
7875  /*
7876   * DP_AUX_RESET enum
7877   */
7878  
7879  typedef enum DP_AUX_RESET {
7880  DP_AUX_RESET_DEASSERTED                  = 0x00000000,
7881  DP_AUX_RESET_ASSERTED                    = 0x00000001,
7882  } DP_AUX_RESET;
7883  
7884  /*
7885   * DP_AUX_RESET_DONE enum
7886   */
7887  
7888  typedef enum DP_AUX_RESET_DONE {
7889  DP_AUX_RESET_SEQUENCE_NOT_DONE           = 0x00000000,
7890  DP_AUX_RESET_SEQUENCE_DONE               = 0x00000001,
7891  } DP_AUX_RESET_DONE;
7892  
7893  /*
7894   * DP_AUX_RX_TIMEOUT_LEN_MUL enum
7895   */
7896  
7897  typedef enum DP_AUX_RX_TIMEOUT_LEN_MUL {
7898  DP_AUX_RX_TIMEOUT_LEN_NO_MUL             = 0x00000000,
7899  DP_AUX_RX_TIMEOUT_LEN_MUL_2              = 0x00000001,
7900  DP_AUX_RX_TIMEOUT_LEN_MUL_4              = 0x00000002,
7901  DP_AUX_RX_TIMEOUT_LEN_MUL_8              = 0x00000003,
7902  } DP_AUX_RX_TIMEOUT_LEN_MUL;
7903  
7904  /*
7905   * DP_AUX_SW_CONTROL_LS_READ_TRIG enum
7906   */
7907  
7908  typedef enum DP_AUX_SW_CONTROL_LS_READ_TRIG {
7909  DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG      = 0x00000000,
7910  DP_AUX_SW_CONTROL_LS_READ__TRIG          = 0x00000001,
7911  } DP_AUX_SW_CONTROL_LS_READ_TRIG;
7912  
7913  /*
7914   * DP_AUX_SW_CONTROL_SW_GO enum
7915   */
7916  
7917  typedef enum DP_AUX_SW_CONTROL_SW_GO {
7918  DP_AUX_SW_CONTROL_SW__NOT_GO             = 0x00000000,
7919  DP_AUX_SW_CONTROL_SW__GO                 = 0x00000001,
7920  } DP_AUX_SW_CONTROL_SW_GO;
7921  
7922  /*
7923   * DP_AUX_TX_PRECHARGE_LEN_MUL enum
7924   */
7925  
7926  typedef enum DP_AUX_TX_PRECHARGE_LEN_MUL {
7927  DP_AUX_TX_PRECHARGE_LEN_NO_MUL           = 0x00000000,
7928  DP_AUX_TX_PRECHARGE_LEN_MUL_2            = 0x00000001,
7929  DP_AUX_TX_PRECHARGE_LEN_MUL_4            = 0x00000002,
7930  DP_AUX_TX_PRECHARGE_LEN_MUL_8            = 0x00000003,
7931  } DP_AUX_TX_PRECHARGE_LEN_MUL;
7932  
7933  /*******************************************************
7934   * DOUT_I2C Enums
7935   *******************************************************/
7936  
7937  /*
7938   * DOUT_I2C_ACK enum
7939   */
7940  
7941  typedef enum DOUT_I2C_ACK {
7942  DOUT_I2C_NO_ACK                          = 0x00000000,
7943  DOUT_I2C_ACK_TO_CLEAN                    = 0x00000001,
7944  } DOUT_I2C_ACK;
7945  
7946  /*
7947   * DOUT_I2C_ARBITRATION_ABORT_XFER enum
7948   */
7949  
7950  typedef enum DOUT_I2C_ARBITRATION_ABORT_XFER {
7951  DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0x00000000,
7952  DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER = 0x00000001,
7953  } DOUT_I2C_ARBITRATION_ABORT_XFER;
7954  
7955  /*
7956   * DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG enum
7957   */
7958  
7959  typedef enum DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG {
7960  DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0x00000000,
7961  DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG = 0x00000001,
7962  } DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG;
7963  
7964  /*
7965   * DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO enum
7966   */
7967  
7968  typedef enum DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO {
7969  DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED    = 0x00000000,
7970  DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED   = 0x00000001,
7971  } DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO;
7972  
7973  /*
7974   * DOUT_I2C_ARBITRATION_SW_PRIORITY enum
7975   */
7976  
7977  typedef enum DOUT_I2C_ARBITRATION_SW_PRIORITY {
7978  DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL  = 0x00000000,
7979  DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH    = 0x00000001,
7980  DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 0x00000002,
7981  DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 0x00000003,
7982  } DOUT_I2C_ARBITRATION_SW_PRIORITY;
7983  
7984  /*
7985   * DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ enum
7986   */
7987  
7988  typedef enum DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ {
7989  DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0x00000000,
7990  DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ    = 0x00000001,
7991  } DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ;
7992  
7993  /*
7994   * DOUT_I2C_CONTROL_DBG_REF_SEL enum
7995   */
7996  
7997  typedef enum DOUT_I2C_CONTROL_DBG_REF_SEL {
7998  DOUT_I2C_CONTROL_NORMAL_DEBUG            = 0x00000000,
7999  DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG    = 0x00000001,
8000  } DOUT_I2C_CONTROL_DBG_REF_SEL;
8001  
8002  /*
8003   * DOUT_I2C_CONTROL_DDC_SELECT enum
8004   */
8005  
8006  typedef enum DOUT_I2C_CONTROL_DDC_SELECT {
8007  DOUT_I2C_CONTROL_SELECT_DDC1             = 0x00000000,
8008  DOUT_I2C_CONTROL_SELECT_DDC2             = 0x00000001,
8009  DOUT_I2C_CONTROL_SELECT_DDC3             = 0x00000002,
8010  DOUT_I2C_CONTROL_SELECT_DDC4             = 0x00000003,
8011  DOUT_I2C_CONTROL_SELECT_DDC5             = 0x00000004,
8012  DOUT_I2C_CONTROL_SELECT_DDCVGA           = 0x00000005,
8013  } DOUT_I2C_CONTROL_DDC_SELECT;
8014  
8015  /*
8016   * DOUT_I2C_CONTROL_GO enum
8017   */
8018  
8019  typedef enum DOUT_I2C_CONTROL_GO {
8020  DOUT_I2C_CONTROL_STOP_TRANSFER           = 0x00000000,
8021  DOUT_I2C_CONTROL_START_TRANSFER          = 0x00000001,
8022  } DOUT_I2C_CONTROL_GO;
8023  
8024  /*
8025   * DOUT_I2C_CONTROL_SEND_RESET enum
8026   */
8027  
8028  typedef enum DOUT_I2C_CONTROL_SEND_RESET {
8029  DOUT_I2C_CONTROL__NOT_SEND_RESET         = 0x00000000,
8030  DOUT_I2C_CONTROL__SEND_RESET             = 0x00000001,
8031  } DOUT_I2C_CONTROL_SEND_RESET;
8032  
8033  /*
8034   * DOUT_I2C_CONTROL_SEND_RESET_LENGTH enum
8035   */
8036  
8037  typedef enum DOUT_I2C_CONTROL_SEND_RESET_LENGTH {
8038  DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9    = 0x00000000,
8039  DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10   = 0x00000001,
8040  } DOUT_I2C_CONTROL_SEND_RESET_LENGTH;
8041  
8042  /*
8043   * DOUT_I2C_CONTROL_SOFT_RESET enum
8044   */
8045  
8046  typedef enum DOUT_I2C_CONTROL_SOFT_RESET {
8047  DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0x00000000,
8048  DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER    = 0x00000001,
8049  } DOUT_I2C_CONTROL_SOFT_RESET;
8050  
8051  /*
8052   * DOUT_I2C_CONTROL_SW_STATUS_RESET enum
8053   */
8054  
8055  typedef enum DOUT_I2C_CONTROL_SW_STATUS_RESET {
8056  DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS     = 0x00000000,
8057  DOUT_I2C_CONTROL_RESET_SW_STATUS         = 0x00000001,
8058  } DOUT_I2C_CONTROL_SW_STATUS_RESET;
8059  
8060  /*
8061   * DOUT_I2C_CONTROL_TRANSACTION_COUNT enum
8062   */
8063  
8064  typedef enum DOUT_I2C_CONTROL_TRANSACTION_COUNT {
8065  DOUT_I2C_CONTROL_TRANS0                  = 0x00000000,
8066  DOUT_I2C_CONTROL_TRANS0_TRANS1           = 0x00000001,
8067  DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2    = 0x00000002,
8068  DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3 = 0x00000003,
8069  } DOUT_I2C_CONTROL_TRANSACTION_COUNT;
8070  
8071  /*
8072   * DOUT_I2C_DATA_INDEX_WRITE enum
8073   */
8074  
8075  typedef enum DOUT_I2C_DATA_INDEX_WRITE {
8076  DOUT_I2C_DATA__NOT_INDEX_WRITE           = 0x00000000,
8077  DOUT_I2C_DATA__INDEX_WRITE               = 0x00000001,
8078  } DOUT_I2C_DATA_INDEX_WRITE;
8079  
8080  /*
8081   * DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN enum
8082   */
8083  
8084  typedef enum DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN {
8085  DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR = 0x00000000,
8086  DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL     = 0x00000001,
8087  } DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN;
8088  
8089  /*
8090   * DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN enum
8091   */
8092  
8093  typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN {
8094  DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR = 0x00000000,
8095  DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA     = 0x00000001,
8096  } DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN;
8097  
8098  /*
8099   * DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL enum
8100   */
8101  
8102  typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL {
8103  DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS = 0x00000000,
8104  DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS = 0x00000001,
8105  } DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL;
8106  
8107  /*
8108   * DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE enum
8109   */
8110  
8111  typedef enum DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE {
8112  DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT   = 0x00000000,
8113  DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT = 0x00000001,
8114  } DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE;
8115  
8116  /*
8117   * DOUT_I2C_DDC_SPEED_THRESHOLD enum
8118   */
8119  
8120  typedef enum DOUT_I2C_DDC_SPEED_THRESHOLD {
8121  DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO = 0x00000000,
8122  DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE = 0x00000001,
8123  DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE = 0x00000002,
8124  DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE = 0x00000003,
8125  } DOUT_I2C_DDC_SPEED_THRESHOLD;
8126  
8127  /*
8128   * DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET enum
8129   */
8130  
8131  typedef enum DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET {
8132  DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0x00000000,
8133  DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0x00000001,
8134  } DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET;
8135  
8136  /*
8137   * DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE enum
8138   */
8139  
8140  typedef enum DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE {
8141  DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL = 0x00000000,
8142  DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE = 0x00000001,
8143  } DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE;
8144  
8145  /*
8146   * DOUT_I2C_TRANSACTION_STOP_ON_NACK enum
8147   */
8148  
8149  typedef enum DOUT_I2C_TRANSACTION_STOP_ON_NACK {
8150  DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS  = 0x00000000,
8151  DOUT_I2C_TRANSACTION_STOP_ALL_TRANS      = 0x00000001,
8152  } DOUT_I2C_TRANSACTION_STOP_ON_NACK;
8153  
8154  /*******************************************************
8155   * DIO_MISC Enums
8156   *******************************************************/
8157  
8158  /*
8159   * CLOCK_GATING_EN enum
8160   */
8161  
8162  typedef enum CLOCK_GATING_EN {
8163  CLOCK_GATING_ENABLE                      = 0x00000000,
8164  CLOCK_GATING_DISABLE                     = 0x00000001,
8165  } CLOCK_GATING_EN;
8166  
8167  /*
8168   * DAC_MUX_SELECT enum
8169   */
8170  
8171  typedef enum DAC_MUX_SELECT {
8172  DAC_MUX_SELECT_DACA                      = 0x00000000,
8173  DAC_MUX_SELECT_DACB                      = 0x00000001,
8174  } DAC_MUX_SELECT;
8175  
8176  /*
8177   * DIOMEM_PWR_DIS_CTRL enum
8178   */
8179  
8180  typedef enum DIOMEM_PWR_DIS_CTRL {
8181  DIOMEM_ENABLE_MEM_PWR_CTRL               = 0x00000000,
8182  DIOMEM_DISABLE_MEM_PWR_CTRL              = 0x00000001,
8183  } DIOMEM_PWR_DIS_CTRL;
8184  
8185  /*
8186   * DIOMEM_PWR_FORCE_CTRL enum
8187   */
8188  
8189  typedef enum DIOMEM_PWR_FORCE_CTRL {
8190  DIOMEM_NO_FORCE_REQUEST                  = 0x00000000,
8191  DIOMEM_FORCE_LIGHT_SLEEP_REQUEST         = 0x00000001,
8192  DIOMEM_FORCE_DEEP_SLEEP_REQUEST          = 0x00000002,
8193  DIOMEM_FORCE_SHUT_DOWN_REQUEST           = 0x00000003,
8194  } DIOMEM_PWR_FORCE_CTRL;
8195  
8196  /*
8197   * DIOMEM_PWR_FORCE_CTRL2 enum
8198   */
8199  
8200  typedef enum DIOMEM_PWR_FORCE_CTRL2 {
8201  DIOMEM_NO_FORCE_REQ                      = 0x00000000,
8202  DIOMEM_FORCE_LIGHT_SLEEP_REQ             = 0x00000001,
8203  } DIOMEM_PWR_FORCE_CTRL2;
8204  
8205  /*
8206   * DIOMEM_PWR_SEL_CTRL enum
8207   */
8208  
8209  typedef enum DIOMEM_PWR_SEL_CTRL {
8210  DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE          = 0x00000000,
8211  DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE         = 0x00000001,
8212  DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE        = 0x00000002,
8213  } DIOMEM_PWR_SEL_CTRL;
8214  
8215  /*
8216   * DIOMEM_PWR_SEL_CTRL2 enum
8217   */
8218  
8219  typedef enum DIOMEM_PWR_SEL_CTRL2 {
8220  DIOMEM_DYNAMIC_DEEP_SLEEP_EN             = 0x00000000,
8221  DIOMEM_DYNAMIC_LIGHT_SLEEP_EN            = 0x00000001,
8222  } DIOMEM_PWR_SEL_CTRL2;
8223  
8224  /*
8225   * DIO_DBG_BLOCK_SEL enum
8226   */
8227  
8228  typedef enum DIO_DBG_BLOCK_SEL {
8229  DIO_DBG_BLOCK_SEL_DIO                    = 0x00000000,
8230  DIO_DBG_BLOCK_SEL_DIGFE_A                = 0x0000000b,
8231  DIO_DBG_BLOCK_SEL_DIGFE_B                = 0x0000000c,
8232  DIO_DBG_BLOCK_SEL_DIGFE_C                = 0x0000000d,
8233  DIO_DBG_BLOCK_SEL_DIGFE_D                = 0x0000000e,
8234  DIO_DBG_BLOCK_SEL_DIGFE_E                = 0x0000000f,
8235  DIO_DBG_BLOCK_SEL_DIGA                   = 0x00000012,
8236  DIO_DBG_BLOCK_SEL_DIGB                   = 0x00000013,
8237  DIO_DBG_BLOCK_SEL_DIGC                   = 0x00000014,
8238  DIO_DBG_BLOCK_SEL_DIGD                   = 0x00000015,
8239  DIO_DBG_BLOCK_SEL_DIGE                   = 0x00000016,
8240  DIO_DBG_BLOCK_SEL_DPFE_A                 = 0x00000019,
8241  DIO_DBG_BLOCK_SEL_DPFE_B                 = 0x0000001a,
8242  DIO_DBG_BLOCK_SEL_DPFE_C                 = 0x0000001b,
8243  DIO_DBG_BLOCK_SEL_DPFE_D                 = 0x0000001c,
8244  DIO_DBG_BLOCK_SEL_DPFE_E                 = 0x0000001d,
8245  DIO_DBG_BLOCK_SEL_DPA                    = 0x00000020,
8246  DIO_DBG_BLOCK_SEL_DPB                    = 0x00000021,
8247  DIO_DBG_BLOCK_SEL_DPC                    = 0x00000022,
8248  DIO_DBG_BLOCK_SEL_DPD                    = 0x00000023,
8249  DIO_DBG_BLOCK_SEL_DPE                    = 0x00000024,
8250  DIO_DBG_BLOCK_SEL_AUX0                   = 0x00000027,
8251  DIO_DBG_BLOCK_SEL_AUX1                   = 0x00000028,
8252  DIO_DBG_BLOCK_SEL_AUX2                   = 0x00000029,
8253  DIO_DBG_BLOCK_SEL_AUX3                   = 0x0000002a,
8254  DIO_DBG_BLOCK_SEL_AUX4                   = 0x0000002b,
8255  DIO_DBG_BLOCK_SEL_PERFMON_DIO            = 0x0000002d,
8256  DIO_DBG_BLOCK_SEL_RESERVED               = 0x0000002e,
8257  } DIO_DBG_BLOCK_SEL;
8258  
8259  /*
8260   * DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE enum
8261   */
8262  
8263  typedef enum DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE {
8264  DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL       = 0x00000000,
8265  DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE       = 0x00000001,
8266  } DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE;
8267  
8268  /*
8269   * DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE enum
8270   */
8271  
8272  typedef enum DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE {
8273  DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_0 = 0x00000000,
8274  DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_1 = 0x00000001,
8275  } DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE;
8276  
8277  /*
8278   * ENUM_DIO_DCN_ACTIVE_STATUS enum
8279   */
8280  
8281  typedef enum ENUM_DIO_DCN_ACTIVE_STATUS {
8282  ENUM_DCN_NOT_ACTIVE                      = 0x00000000,
8283  ENUM_DCN_ACTIVE                          = 0x00000001,
8284  } ENUM_DIO_DCN_ACTIVE_STATUS;
8285  
8286  /*
8287   * GENERIC_STEREOSYNC_SEL enum
8288   */
8289  
8290  typedef enum GENERIC_STEREOSYNC_SEL {
8291  GENERIC_STEREOSYNC_SEL_D1                = 0x00000000,
8292  GENERIC_STEREOSYNC_SEL_D2                = 0x00000001,
8293  GENERIC_STEREOSYNC_SEL_D3                = 0x00000002,
8294  GENERIC_STEREOSYNC_SEL_D4                = 0x00000003,
8295  GENERIC_STEREOSYNC_SEL_RESERVED          = 0x00000004,
8296  } GENERIC_STEREOSYNC_SEL;
8297  
8298  /*
8299   * PM_ASSERT_RESET enum
8300   */
8301  
8302  typedef enum PM_ASSERT_RESET {
8303  PM_ASSERT_RESET_0                        = 0x00000000,
8304  PM_ASSERT_RESET_1                        = 0x00000001,
8305  } PM_ASSERT_RESET;
8306  
8307  /*
8308   * SOFT_RESET enum
8309   */
8310  
8311  typedef enum SOFT_RESET {
8312  SOFT_RESET_0                             = 0x00000000,
8313  SOFT_RESET_1                             = 0x00000001,
8314  } SOFT_RESET;
8315  
8316  /*
8317   * TMDS_MUX_SELECT enum
8318   */
8319  
8320  typedef enum TMDS_MUX_SELECT {
8321  TMDS_MUX_SELECT_B                        = 0x00000000,
8322  TMDS_MUX_SELECT_G                        = 0x00000001,
8323  TMDS_MUX_SELECT_R                        = 0x00000002,
8324  TMDS_MUX_SELECT_RESERVED                 = 0x00000003,
8325  } TMDS_MUX_SELECT;
8326  
8327  /*******************************************************
8328   * DME Enums
8329   *******************************************************/
8330  
8331  /*
8332   * DME_MEM_POWER_STATE_ENUM enum
8333   */
8334  
8335  typedef enum DME_MEM_POWER_STATE_ENUM {
8336  DME_MEM_POWER_STATE_ENUM_ON              = 0x00000000,
8337  DME_MEM_POWER_STATE_ENUM_LS              = 0x00000001,
8338  DME_MEM_POWER_STATE_ENUM_DS              = 0x00000002,
8339  DME_MEM_POWER_STATE_ENUM_SD              = 0x00000003,
8340  } DME_MEM_POWER_STATE_ENUM;
8341  
8342  /*
8343   * DME_MEM_PWR_DIS_CTRL enum
8344   */
8345  
8346  typedef enum DME_MEM_PWR_DIS_CTRL {
8347  DME_MEM_ENABLE_MEM_PWR_CTRL              = 0x00000000,
8348  DME_MEM_DISABLE_MEM_PWR_CTRL             = 0x00000001,
8349  } DME_MEM_PWR_DIS_CTRL;
8350  
8351  /*
8352   * DME_MEM_PWR_FORCE_CTRL enum
8353   */
8354  
8355  typedef enum DME_MEM_PWR_FORCE_CTRL {
8356  DME_MEM_NO_FORCE_REQUEST                 = 0x00000000,
8357  DME_MEM_FORCE_LIGHT_SLEEP_REQUEST        = 0x00000001,
8358  DME_MEM_FORCE_DEEP_SLEEP_REQUEST         = 0x00000002,
8359  DME_MEM_FORCE_SHUT_DOWN_REQUEST          = 0x00000003,
8360  } DME_MEM_PWR_FORCE_CTRL;
8361  
8362  /*
8363   * METADATA_HUBP_SEL enum
8364   */
8365  
8366  typedef enum METADATA_HUBP_SEL {
8367  METADATA_HUBP_SEL_0                      = 0x00000000,
8368  METADATA_HUBP_SEL_1                      = 0x00000001,
8369  METADATA_HUBP_SEL_2                      = 0x00000002,
8370  METADATA_HUBP_SEL_3                      = 0x00000003,
8371  METADATA_HUBP_SEL_RESERVED               = 0x00000004,
8372  } METADATA_HUBP_SEL;
8373  
8374  /*
8375   * METADATA_STREAM_TYPE_SEL enum
8376   */
8377  
8378  typedef enum METADATA_STREAM_TYPE_SEL {
8379  METADATA_STREAM_DP                       = 0x00000000,
8380  METADATA_STREAM_DVE                      = 0x00000001,
8381  } METADATA_STREAM_TYPE_SEL;
8382  
8383  /*******************************************************
8384   * VPG Enums
8385   *******************************************************/
8386  
8387  /*
8388   * VPG_MEM_PWR_DIS_CTRL enum
8389   */
8390  
8391  typedef enum VPG_MEM_PWR_DIS_CTRL {
8392  VPG_MEM_ENABLE_MEM_PWR_CTRL              = 0x00000000,
8393  VPG_MEM_DISABLE_MEM_PWR_CTRL             = 0x00000001,
8394  } VPG_MEM_PWR_DIS_CTRL;
8395  
8396  /*
8397   * VPG_MEM_PWR_FORCE_CTRL enum
8398   */
8399  
8400  typedef enum VPG_MEM_PWR_FORCE_CTRL {
8401  VPG_MEM_NO_FORCE_REQ                     = 0x00000000,
8402  VPG_MEM_FORCE_LIGHT_SLEEP_REQ            = 0x00000001,
8403  } VPG_MEM_PWR_FORCE_CTRL;
8404  
8405  /*******************************************************
8406   * AFMT Enums
8407   *******************************************************/
8408  
8409  /*
8410   * AFMT_ACP_TYPE enum
8411   */
8412  
8413  typedef enum AFMT_ACP_TYPE {
8414  ACP_TYPE_GENERIC_AUDIO                   = 0x00000000,
8415  ACP_TYPE_ICE60958_AUDIO                  = 0x00000001,
8416  ACP_TYPE_DVD_AUDIO                       = 0x00000002,
8417  ACP_TYPE_SUPER_AUDIO_CD                  = 0x00000003,
8418  } AFMT_ACP_TYPE;
8419  
8420  /*
8421   * AFMT_AUDIO_CRC_CONTROL_CH_SEL enum
8422   */
8423  
8424  typedef enum AFMT_AUDIO_CRC_CONTROL_CH_SEL {
8425  AFMT_AUDIO_CRC_CH0_SIG                   = 0x00000000,
8426  AFMT_AUDIO_CRC_CH1_SIG                   = 0x00000001,
8427  AFMT_AUDIO_CRC_CH2_SIG                   = 0x00000002,
8428  AFMT_AUDIO_CRC_CH3_SIG                   = 0x00000003,
8429  AFMT_AUDIO_CRC_CH4_SIG                   = 0x00000004,
8430  AFMT_AUDIO_CRC_CH5_SIG                   = 0x00000005,
8431  AFMT_AUDIO_CRC_CH6_SIG                   = 0x00000006,
8432  AFMT_AUDIO_CRC_CH7_SIG                   = 0x00000007,
8433  AFMT_AUDIO_CRC_RESERVED_8                = 0x00000008,
8434  AFMT_AUDIO_CRC_RESERVED_9                = 0x00000009,
8435  AFMT_AUDIO_CRC_RESERVED_10               = 0x0000000a,
8436  AFMT_AUDIO_CRC_RESERVED_11               = 0x0000000b,
8437  AFMT_AUDIO_CRC_RESERVED_12               = 0x0000000c,
8438  AFMT_AUDIO_CRC_RESERVED_13               = 0x0000000d,
8439  AFMT_AUDIO_CRC_RESERVED_14               = 0x0000000e,
8440  AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT        = 0x0000000f,
8441  } AFMT_AUDIO_CRC_CONTROL_CH_SEL;
8442  
8443  /*
8444   * AFMT_AUDIO_CRC_CONTROL_CONT enum
8445   */
8446  
8447  typedef enum AFMT_AUDIO_CRC_CONTROL_CONT {
8448  AFMT_AUDIO_CRC_ONESHOT                   = 0x00000000,
8449  AFMT_AUDIO_CRC_AUTO_RESTART              = 0x00000001,
8450  } AFMT_AUDIO_CRC_CONTROL_CONT;
8451  
8452  /*
8453   * AFMT_AUDIO_CRC_CONTROL_SOURCE enum
8454   */
8455  
8456  typedef enum AFMT_AUDIO_CRC_CONTROL_SOURCE {
8457  AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT    = 0x00000000,
8458  AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT   = 0x00000001,
8459  } AFMT_AUDIO_CRC_CONTROL_SOURCE;
8460  
8461  /*
8462   * AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD enum
8463   */
8464  
8465  typedef enum AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD {
8466  AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS = 0x00000000,
8467  AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER       = 0x00000001,
8468  } AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD;
8469  
8470  /*
8471   * AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND enum
8472   */
8473  
8474  typedef enum AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND {
8475  AFMT_AUDIO_PACKET_SENT_DISABLED          = 0x00000000,
8476  AFMT_AUDIO_PACKET_SENT_ENABLED           = 0x00000001,
8477  } AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND;
8478  
8479  /*
8480   * AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS enum
8481   */
8482  
8483  typedef enum AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS {
8484  AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED = 0x00000000,
8485  AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED = 0x00000001,
8486  } AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS;
8487  
8488  /*
8489   * AFMT_AUDIO_SRC_CONTROL_SELECT enum
8490   */
8491  
8492  typedef enum AFMT_AUDIO_SRC_CONTROL_SELECT {
8493  AFMT_AUDIO_SRC_FROM_AZ_STREAM0           = 0x00000000,
8494  AFMT_AUDIO_SRC_FROM_AZ_STREAM1           = 0x00000001,
8495  AFMT_AUDIO_SRC_FROM_AZ_STREAM2           = 0x00000002,
8496  AFMT_AUDIO_SRC_FROM_AZ_STREAM3           = 0x00000003,
8497  AFMT_AUDIO_SRC_FROM_AZ_STREAM4           = 0x00000004,
8498  AFMT_AUDIO_SRC_FROM_AZ_STREAM5           = 0x00000005,
8499  } AFMT_AUDIO_SRC_CONTROL_SELECT;
8500  
8501  /*
8502   * AFMT_HDMI_AUDIO_SEND_MAX_PACKETS enum
8503   */
8504  
8505  typedef enum AFMT_HDMI_AUDIO_SEND_MAX_PACKETS {
8506  HDMI_NOT_SEND_MAX_AUDIO_PACKETS          = 0x00000000,
8507  HDMI_SEND_MAX_AUDIO_PACKETS              = 0x00000001,
8508  } AFMT_HDMI_AUDIO_SEND_MAX_PACKETS;
8509  
8510  /*
8511   * AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE enum
8512   */
8513  
8514  typedef enum AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE {
8515  AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK  = 0x00000000,
8516  AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS = 0x00000001,
8517  } AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE;
8518  
8519  /*
8520   * AFMT_INTERRUPT_STATUS_CHG_MASK enum
8521   */
8522  
8523  typedef enum AFMT_INTERRUPT_STATUS_CHG_MASK {
8524  AFMT_INTERRUPT_DISABLE                   = 0x00000000,
8525  AFMT_INTERRUPT_ENABLE                    = 0x00000001,
8526  } AFMT_INTERRUPT_STATUS_CHG_MASK;
8527  
8528  /*
8529   * AFMT_MEM_PWR_DIS_CTRL enum
8530   */
8531  
8532  typedef enum AFMT_MEM_PWR_DIS_CTRL {
8533  AFMT_MEM_ENABLE_MEM_PWR_CTRL             = 0x00000000,
8534  AFMT_MEM_DISABLE_MEM_PWR_CTRL            = 0x00000001,
8535  } AFMT_MEM_PWR_DIS_CTRL;
8536  
8537  /*
8538   * AFMT_MEM_PWR_FORCE_CTRL enum
8539   */
8540  
8541  typedef enum AFMT_MEM_PWR_FORCE_CTRL {
8542  AFMT_MEM_NO_FORCE_REQUEST                = 0x00000000,
8543  AFMT_MEM_FORCE_LIGHT_SLEEP_REQUEST       = 0x00000001,
8544  AFMT_MEM_FORCE_DEEP_SLEEP_REQUEST        = 0x00000002,
8545  AFMT_MEM_FORCE_SHUT_DOWN_REQUEST         = 0x00000003,
8546  } AFMT_MEM_PWR_FORCE_CTRL;
8547  
8548  /*
8549   * AFMT_RAMP_CONTROL0_SIGN enum
8550   */
8551  
8552  typedef enum AFMT_RAMP_CONTROL0_SIGN {
8553  AFMT_RAMP_SIGNED                         = 0x00000000,
8554  AFMT_RAMP_UNSIGNED                       = 0x00000001,
8555  } AFMT_RAMP_CONTROL0_SIGN;
8556  
8557  /*
8558   * AFMT_VBI_PACKET_CONTROL_ACP_SOURCE enum
8559   */
8560  
8561  typedef enum AFMT_VBI_PACKET_CONTROL_ACP_SOURCE {
8562  AFMT_ACP_SOURCE_FROM_AZALIA              = 0x00000000,
8563  AFMT_ACP_SOURCE_FROM_AFMT_REGISTERS      = 0x00000001,
8564  } AFMT_VBI_PACKET_CONTROL_ACP_SOURCE;
8565  
8566  /*
8567   * AUDIO_LAYOUT_SELECT enum
8568   */
8569  
8570  typedef enum AUDIO_LAYOUT_SELECT {
8571  AUDIO_LAYOUT_0                           = 0x00000000,
8572  AUDIO_LAYOUT_1                           = 0x00000001,
8573  } AUDIO_LAYOUT_SELECT;
8574  
8575  /*******************************************************
8576   * HPO_TOP Enums
8577   *******************************************************/
8578  
8579  /*
8580   * HPO_TOP_CLOCK_GATING_DISABLE enum
8581   */
8582  
8583  typedef enum HPO_TOP_CLOCK_GATING_DISABLE {
8584  HPO_TOP_CLOCK_GATING_EN                  = 0x00000000,
8585  HPO_TOP_CLOCK_GATING_DIS                 = 0x00000001,
8586  } HPO_TOP_CLOCK_GATING_DISABLE;
8587  
8588  /*
8589   * HPO_TOP_TEST_CLK_SEL enum
8590   */
8591  
8592  typedef enum HPO_TOP_TEST_CLK_SEL {
8593  HPO_TOP_PERMANENT_DISPCLK                = 0x00000000,
8594  HPO_TOP_REGISTER_GATED_DISPCLK           = 0x00000001,
8595  HPO_TOP_PERMANENT_SOCCLK                 = 0x00000002,
8596  HPO_TOP_TEST_CLOCK_RESERVED              = 0x00000003,
8597  HPO_TOP_PERMANENT_HDMISTREAMCLK0         = 0x00000004,
8598  HPO_TOP_FEATURE_GATED_HDMISTREAMCLK0     = 0x00000005,
8599  HPO_TOP_REGISTER_GATED_HDMISTREAMCLK0    = 0x00000006,
8600  HPO_TOP_FEATURE_GATED_DISPCLK_IN_HDMISTREAMENC0 = 0x00000007,
8601  HPO_TOP_FEATURE_GATED_SOCCLK_IN_HDMISTREAMENC0 = 0x00000008,
8602  HPO_TOP_PERMANENT_HDMICHARCLK0           = 0x00000009,
8603  HPO_TOP_FEATURE_GATED_HDMICHARCLK0       = 0x0000000a,
8604  HPO_TOP_REGISTER_GATED_HDMICHARCLK0      = 0x0000000b,
8605  } HPO_TOP_TEST_CLK_SEL;
8606  
8607  /*******************************************************
8608   * DP_STREAM_MAPPER Enums
8609   *******************************************************/
8610  
8611  /*
8612   * DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET enum
8613   */
8614  
8615  typedef enum DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET {
8616  DP_STREAM_MAPPER_LINK0                   = 0x00000000,
8617  DP_STREAM_MAPPER_LINK1                   = 0x00000001,
8618  DP_STREAM_MAPPER_RESERVED                = 0x00000002,
8619  } DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET;
8620  
8621  /*******************************************************
8622   * HDMI_STREAM_ENC Enums
8623   *******************************************************/
8624  
8625  /*
8626   * HDMI_STREAM_ENC_DB_DISABLE_CONTROL enum
8627   */
8628  
8629  typedef enum HDMI_STREAM_ENC_DB_DISABLE_CONTROL {
8630  HDMI_STREAM_ENC_DB_ENABLE                = 0x00000000,
8631  HDMI_STREAM_ENC_DB_DISABLE               = 0x00000001,
8632  } HDMI_STREAM_ENC_DB_DISABLE_CONTROL;
8633  
8634  /*
8635   * HDMI_STREAM_ENC_DSC_MODE enum
8636   */
8637  
8638  typedef enum HDMI_STREAM_ENC_DSC_MODE {
8639  STREAM_DSC_DISABLE                       = 0x00000000,
8640  STREAM_DSC_444_RGB                       = 0x00000001,
8641  STREAM_DSC_NATIVE_422_420                = 0x00000002,
8642  } HDMI_STREAM_ENC_DSC_MODE;
8643  
8644  /*
8645   * HDMI_STREAM_ENC_ENABLE_CONTROL enum
8646   */
8647  
8648  typedef enum HDMI_STREAM_ENC_ENABLE_CONTROL {
8649  HDMI_STREAM_ENC_DISABLE                  = 0x00000000,
8650  HDMI_STREAM_ENC_ENABLE                   = 0x00000001,
8651  } HDMI_STREAM_ENC_ENABLE_CONTROL;
8652  
8653  /*
8654   * HDMI_STREAM_ENC_ODM_COMBINE_MODE enum
8655   */
8656  
8657  typedef enum HDMI_STREAM_ENC_ODM_COMBINE_MODE {
8658  STREAM_ODM_COMBINE_1_SEGMENT             = 0x00000000,
8659  STREAM_ODM_COMBINE_2_SEGMENT             = 0x00000001,
8660  STREAM_ODM_COMBINE_RESERVED              = 0x00000002,
8661  STREAM_ODM_COMBINE_4_SEGMENT             = 0x00000003,
8662  } HDMI_STREAM_ENC_ODM_COMBINE_MODE;
8663  
8664  /*
8665   * HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR enum
8666   */
8667  
8668  typedef enum HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR {
8669  HDMI_STREAM_ENC_NO_ERROR_OCCURRED        = 0x00000000,
8670  HDMI_STREAM_ENC_UNDERFLOW_OCCURRED       = 0x00000001,
8671  HDMI_STREAM_ENC_OVERFLOW_OCCURRED        = 0x00000002,
8672  } HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR;
8673  
8674  /*
8675   * HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT enum
8676   */
8677  
8678  typedef enum HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT {
8679  HDMI_STREAM_ENC_HARDWARE                 = 0x00000000,
8680  HDMI_STREAM_ENC_PROGRAMMABLE             = 0x00000001,
8681  } HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT;
8682  
8683  /*
8684   * HDMI_STREAM_ENC_PIXEL_ENCODING enum
8685   */
8686  
8687  typedef enum HDMI_STREAM_ENC_PIXEL_ENCODING {
8688  STREAM_PIXEL_ENCODING_444_RGB            = 0x00000000,
8689  STREAM_PIXEL_ENCODING_422                = 0x00000001,
8690  STREAM_PIXEL_ENCODING_420                = 0x00000002,
8691  } HDMI_STREAM_ENC_PIXEL_ENCODING;
8692  
8693  /*
8694   * HDMI_STREAM_ENC_READ_CLOCK_CONTROL enum
8695   */
8696  
8697  typedef enum HDMI_STREAM_ENC_READ_CLOCK_CONTROL {
8698  HDMI_STREAM_ENC_DCCG                     = 0x00000000,
8699  HDMI_STREAM_ENC_DISPLAY_PIPE             = 0x00000001,
8700  } HDMI_STREAM_ENC_READ_CLOCK_CONTROL;
8701  
8702  /*
8703   * HDMI_STREAM_ENC_RESET_CONTROL enum
8704   */
8705  
8706  typedef enum HDMI_STREAM_ENC_RESET_CONTROL {
8707  HDMI_STREAM_ENC_NOT_RESET                = 0x00000000,
8708  HDMI_STREAM_ENC_RESET                    = 0x00000001,
8709  } HDMI_STREAM_ENC_RESET_CONTROL;
8710  
8711  /*
8712   * HDMI_STREAM_ENC_STREAM_ACTIVE enum
8713   */
8714  
8715  typedef enum HDMI_STREAM_ENC_STREAM_ACTIVE {
8716  HDMI_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE  = 0x00000000,
8717  HDMI_STREAM_ENC_VIDEO_STREAM_ACTIVE      = 0x00000001,
8718  } HDMI_STREAM_ENC_STREAM_ACTIVE;
8719  
8720  /*******************************************************
8721   * HDMI_TB_ENC Enums
8722   *******************************************************/
8723  
8724  /*
8725   * BORROWBUFFER_MEM_POWER_STATE_ENUM enum
8726   */
8727  
8728  typedef enum BORROWBUFFER_MEM_POWER_STATE_ENUM {
8729  BORROWBUFFER_MEM_POWER_STATE_ENUM_ON     = 0x00000000,
8730  BORROWBUFFER_MEM_POWER_STATE_ENUM_LS     = 0x00000001,
8731  BORROWBUFFER_MEM_POWER_STATE_ENUM_DS     = 0x00000002,
8732  BORROWBUFFER_MEM_POWER_STATE_ENUM_SD     = 0x00000003,
8733  } BORROWBUFFER_MEM_POWER_STATE_ENUM;
8734  
8735  /*
8736   * HDMI_BORROW_MODE enum
8737   */
8738  
8739  typedef enum HDMI_BORROW_MODE {
8740  TB_BORROW_MODE_NONE                      = 0x00000000,
8741  TB_BORROW_MODE_ACTIVE                    = 0x00000001,
8742  TB_BORROW_MODE_BLANK                     = 0x00000002,
8743  TB_BORROW_MODE_RESERVED                  = 0x00000003,
8744  } HDMI_BORROW_MODE;
8745  
8746  /*
8747   * HDMI_TB_ENC_ACP_SEND enum
8748   */
8749  
8750  typedef enum HDMI_TB_ENC_ACP_SEND {
8751  TB_ACP_NOT_SEND                          = 0x00000000,
8752  TB_ACP_PKT_SEND                          = 0x00000001,
8753  } HDMI_TB_ENC_ACP_SEND;
8754  
8755  /*
8756   * HDMI_TB_ENC_ACR_AUDIO_PRIORITY enum
8757   */
8758  
8759  typedef enum HDMI_TB_ENC_ACR_AUDIO_PRIORITY {
8760  TB_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0x00000000,
8761  TB_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 0x00000001,
8762  } HDMI_TB_ENC_ACR_AUDIO_PRIORITY;
8763  
8764  /*
8765   * HDMI_TB_ENC_ACR_CONT enum
8766   */
8767  
8768  typedef enum HDMI_TB_ENC_ACR_CONT {
8769  TB_ACR_CONT_DISABLE                      = 0x00000000,
8770  TB_ACR_CONT_ENABLE                       = 0x00000001,
8771  } HDMI_TB_ENC_ACR_CONT;
8772  
8773  /*
8774   * HDMI_TB_ENC_ACR_N_MULTIPLE enum
8775   */
8776  
8777  typedef enum HDMI_TB_ENC_ACR_N_MULTIPLE {
8778  TB_ACR_0_MULTIPLE_RESERVED               = 0x00000000,
8779  TB_ACR_1_MULTIPLE                        = 0x00000001,
8780  TB_ACR_2_MULTIPLE                        = 0x00000002,
8781  TB_ACR_3_MULTIPLE_RESERVED               = 0x00000003,
8782  TB_ACR_4_MULTIPLE                        = 0x00000004,
8783  TB_ACR_5_MULTIPLE_RESERVED               = 0x00000005,
8784  TB_ACR_6_MULTIPLE_RESERVED               = 0x00000006,
8785  TB_ACR_7_MULTIPLE_RESERVED               = 0x00000007,
8786  } HDMI_TB_ENC_ACR_N_MULTIPLE;
8787  
8788  /*
8789   * HDMI_TB_ENC_ACR_SELECT enum
8790   */
8791  
8792  typedef enum HDMI_TB_ENC_ACR_SELECT {
8793  TB_ACR_SELECT_HW                         = 0x00000000,
8794  TB_ACR_SELECT_32K                        = 0x00000001,
8795  TB_ACR_SELECT_44K                        = 0x00000002,
8796  TB_ACR_SELECT_48K                        = 0x00000003,
8797  } HDMI_TB_ENC_ACR_SELECT;
8798  
8799  /*
8800   * HDMI_TB_ENC_ACR_SEND enum
8801   */
8802  
8803  typedef enum HDMI_TB_ENC_ACR_SEND {
8804  TB_ACR_NOT_SEND                          = 0x00000000,
8805  TB_ACR_PKT_SEND                          = 0x00000001,
8806  } HDMI_TB_ENC_ACR_SEND;
8807  
8808  /*
8809   * HDMI_TB_ENC_ACR_SOURCE enum
8810   */
8811  
8812  typedef enum HDMI_TB_ENC_ACR_SOURCE {
8813  TB_ACR_SOURCE_HW                         = 0x00000000,
8814  TB_ACR_SOURCE_SW                         = 0x00000001,
8815  } HDMI_TB_ENC_ACR_SOURCE;
8816  
8817  /*
8818   * HDMI_TB_ENC_AUDIO_INFO_CONT enum
8819   */
8820  
8821  typedef enum HDMI_TB_ENC_AUDIO_INFO_CONT {
8822  TB_AUDIO_INFO_CONT_DISABLE               = 0x00000000,
8823  TB_AUDIO_INFO_CONT_ENABLE                = 0x00000001,
8824  } HDMI_TB_ENC_AUDIO_INFO_CONT;
8825  
8826  /*
8827   * HDMI_TB_ENC_AUDIO_INFO_SEND enum
8828   */
8829  
8830  typedef enum HDMI_TB_ENC_AUDIO_INFO_SEND {
8831  TB_AUDIO_INFO_NOT_SEND                   = 0x00000000,
8832  TB_AUDIO_INFO_PKT_SEND                   = 0x00000001,
8833  } HDMI_TB_ENC_AUDIO_INFO_SEND;
8834  
8835  /*
8836   * HDMI_TB_ENC_CRC_SRC_SEL enum
8837   */
8838  
8839  typedef enum HDMI_TB_ENC_CRC_SRC_SEL {
8840  TB_CRC_TB_ENC_INPUT                      = 0x00000000,
8841  TB_CRC_DSC_PACKER                        = 0x00000001,
8842  TB_CRC_DEEP_COLOR_PACKER                 = 0x00000002,
8843  TB_CRC_ENCRYPTOR_INPUT                   = 0x00000003,
8844  } HDMI_TB_ENC_CRC_SRC_SEL;
8845  
8846  /*
8847   * HDMI_TB_ENC_CRC_TYPE enum
8848   */
8849  
8850  typedef enum HDMI_TB_ENC_CRC_TYPE {
8851  TB_CRC_ALL_TRIBYTES                      = 0x00000000,
8852  TB_CRC_ACTIVE_TRIBYTES                   = 0x00000001,
8853  TB_CRC_DATAISLAND_TRIBYTES               = 0x00000002,
8854  TB_CRC_ACTIVE_AND_DATAISLAND_TRIBYTES    = 0x00000003,
8855  } HDMI_TB_ENC_CRC_TYPE;
8856  
8857  /*
8858   * HDMI_TB_ENC_DEEP_COLOR_DEPTH enum
8859   */
8860  
8861  typedef enum HDMI_TB_ENC_DEEP_COLOR_DEPTH {
8862  TB_DEEP_COLOR_DEPTH_24BPP                = 0x00000000,
8863  TB_DEEP_COLOR_DEPTH_30BPP                = 0x00000001,
8864  TB_DEEP_COLOR_DEPTH_36BPP                = 0x00000002,
8865  TB_DEEP_COLOR_DEPTH_RESERVED             = 0x00000003,
8866  } HDMI_TB_ENC_DEEP_COLOR_DEPTH;
8867  
8868  /*
8869   * HDMI_TB_ENC_DEFAULT_PAHSE enum
8870   */
8871  
8872  typedef enum HDMI_TB_ENC_DEFAULT_PAHSE {
8873  TB_DEFAULT_PHASE_IS_0                    = 0x00000000,
8874  TB_DEFAULT_PHASE_IS_1                    = 0x00000001,
8875  } HDMI_TB_ENC_DEFAULT_PAHSE;
8876  
8877  /*
8878   * HDMI_TB_ENC_DSC_MODE enum
8879   */
8880  
8881  typedef enum HDMI_TB_ENC_DSC_MODE {
8882  TB_DSC_DISABLE                           = 0x00000000,
8883  TB_DSC_444_RGB                           = 0x00000001,
8884  TB_DSC_NATIVE_422_420                    = 0x00000002,
8885  } HDMI_TB_ENC_DSC_MODE;
8886  
8887  /*
8888   * HDMI_TB_ENC_ENABLE enum
8889   */
8890  
8891  typedef enum HDMI_TB_ENC_ENABLE {
8892  TB_DISABLE                               = 0x00000000,
8893  TB_ENABLE                                = 0x00000001,
8894  } HDMI_TB_ENC_ENABLE;
8895  
8896  /*
8897   * HDMI_TB_ENC_GC_AVMUTE enum
8898   */
8899  
8900  typedef enum HDMI_TB_ENC_GC_AVMUTE {
8901  TB_GC_AVMUTE_SET                         = 0x00000000,
8902  TB_GC_AVMUTE_UNSET                       = 0x00000001,
8903  } HDMI_TB_ENC_GC_AVMUTE;
8904  
8905  /*
8906   * HDMI_TB_ENC_GC_AVMUTE_CONT enum
8907   */
8908  
8909  typedef enum HDMI_TB_ENC_GC_AVMUTE_CONT {
8910  TB_GC_AVMUTE_CONT_DISABLE                = 0x00000000,
8911  TB_GC_AVMUTE_CONT_ENABLE                 = 0x00000001,
8912  } HDMI_TB_ENC_GC_AVMUTE_CONT;
8913  
8914  /*
8915   * HDMI_TB_ENC_GC_CONT enum
8916   */
8917  
8918  typedef enum HDMI_TB_ENC_GC_CONT {
8919  TB_GC_CONT_DISABLE                       = 0x00000000,
8920  TB_GC_CONT_ENABLE                        = 0x00000001,
8921  } HDMI_TB_ENC_GC_CONT;
8922  
8923  /*
8924   * HDMI_TB_ENC_GC_SEND enum
8925   */
8926  
8927  typedef enum HDMI_TB_ENC_GC_SEND {
8928  TB_GC_NOT_SEND                           = 0x00000000,
8929  TB_GC_PKT_SEND                           = 0x00000001,
8930  } HDMI_TB_ENC_GC_SEND;
8931  
8932  /*
8933   * HDMI_TB_ENC_GENERIC_CONT enum
8934   */
8935  
8936  typedef enum HDMI_TB_ENC_GENERIC_CONT {
8937  TB_GENERIC_CONT_DISABLE                  = 0x00000000,
8938  TB_GENERIC_CONT_ENABLE                   = 0x00000001,
8939  } HDMI_TB_ENC_GENERIC_CONT;
8940  
8941  /*
8942   * HDMI_TB_ENC_GENERIC_LOCK_EN enum
8943   */
8944  
8945  typedef enum HDMI_TB_ENC_GENERIC_LOCK_EN {
8946  HDMI_TB_ENC_GENERIC_LOCK_DISABLE         = 0x00000000,
8947  HDMI_TB_ENC_GENERIC_LOCK_ENABLE          = 0x00000001,
8948  } HDMI_TB_ENC_GENERIC_LOCK_EN;
8949  
8950  /*
8951   * HDMI_TB_ENC_GENERIC_SEND enum
8952   */
8953  
8954  typedef enum HDMI_TB_ENC_GENERIC_SEND {
8955  TB_GENERIC_NOT_SEND                      = 0x00000000,
8956  TB_GENERIC_PKT_SEND                      = 0x00000001,
8957  } HDMI_TB_ENC_GENERIC_SEND;
8958  
8959  /*
8960   * HDMI_TB_ENC_ISRC_CONT enum
8961   */
8962  
8963  typedef enum HDMI_TB_ENC_ISRC_CONT {
8964  TB_ISRC_CONT_DISABLE                     = 0x00000000,
8965  TB_ISRC_CONT_ENABLE                      = 0x00000001,
8966  } HDMI_TB_ENC_ISRC_CONT;
8967  
8968  /*
8969   * HDMI_TB_ENC_ISRC_SEND enum
8970   */
8971  
8972  typedef enum HDMI_TB_ENC_ISRC_SEND {
8973  TB_ISRC_NOT_SEND                         = 0x00000000,
8974  TB_ISRC_PKT_SEND                         = 0x00000001,
8975  } HDMI_TB_ENC_ISRC_SEND;
8976  
8977  /*
8978   * HDMI_TB_ENC_METADATA_ENABLE enum
8979   */
8980  
8981  typedef enum HDMI_TB_ENC_METADATA_ENABLE {
8982  TB_METADATA_NOT_SEND                     = 0x00000000,
8983  TB_METADATA_PKT_SEND                     = 0x00000001,
8984  } HDMI_TB_ENC_METADATA_ENABLE;
8985  
8986  /*
8987   * HDMI_TB_ENC_PACKET_LINE_REFERENCE enum
8988   */
8989  
8990  typedef enum HDMI_TB_ENC_PACKET_LINE_REFERENCE {
8991  TB_PKT_LINE_REF_END_OF_ACTIVE            = 0x00000000,
8992  TB_PKT_LINE_REF_OTGSOF                   = 0x00000001,
8993  } HDMI_TB_ENC_PACKET_LINE_REFERENCE;
8994  
8995  /*
8996   * HDMI_TB_ENC_PIXEL_ENCODING enum
8997   */
8998  
8999  typedef enum HDMI_TB_ENC_PIXEL_ENCODING {
9000  TB_PIXEL_ENCODING_444_RGB                = 0x00000000,
9001  TB_PIXEL_ENCODING_422                    = 0x00000001,
9002  TB_PIXEL_ENCODING_420                    = 0x00000002,
9003  } HDMI_TB_ENC_PIXEL_ENCODING;
9004  
9005  /*
9006   * HDMI_TB_ENC_RESET enum
9007   */
9008  
9009  typedef enum HDMI_TB_ENC_RESET {
9010  TB_NOT_RESET                             = 0x00000000,
9011  TB_RESET                                 = 0x00000001,
9012  } HDMI_TB_ENC_RESET;
9013  
9014  /*
9015   * HDMI_TB_ENC_SYNC_PHASE enum
9016   */
9017  
9018  typedef enum HDMI_TB_ENC_SYNC_PHASE {
9019  TB_NOT_SYNC_PHASE_ON_FRAME_START         = 0x00000000,
9020  TB_SYNC_PHASE_ON_FRAME_START             = 0x00000001,
9021  } HDMI_TB_ENC_SYNC_PHASE;
9022  
9023  /*
9024   * INPUT_FIFO_ERROR_TYPE enum
9025   */
9026  
9027  typedef enum INPUT_FIFO_ERROR_TYPE {
9028  TB_NO_ERROR_OCCURRED                     = 0x00000000,
9029  TB_OVERFLOW_OCCURRED                     = 0x00000001,
9030  } INPUT_FIFO_ERROR_TYPE;
9031  
9032  /*******************************************************
9033   * DP_STREAM_ENC Enums
9034   *******************************************************/
9035  
9036  /*
9037   * DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR enum
9038   */
9039  
9040  typedef enum DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR {
9041  DP_STREAM_ENC_NO_ERROR_OCCURRED          = 0x00000000,
9042  DP_STREAM_ENC_UNDERFLOW_OCCURRED         = 0x00000001,
9043  DP_STREAM_ENC_OVERFLOW_OCCURRED          = 0x00000002,
9044  } DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR;
9045  
9046  /*
9047   * DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT enum
9048   */
9049  
9050  typedef enum DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT {
9051  DP_STREAM_ENC_HARDWARE                   = 0x00000000,
9052  DP_STREAM_ENC_PROGRAMMABLE               = 0x00000001,
9053  } DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT;
9054  
9055  /*
9056   * DP_STREAM_ENC_READ_CLOCK_CONTROL enum
9057   */
9058  
9059  typedef enum DP_STREAM_ENC_READ_CLOCK_CONTROL {
9060  DP_STREAM_ENC_DCCG                       = 0x00000000,
9061  DP_STREAM_ENC_DISPLAY_PIPE               = 0x00000001,
9062  } DP_STREAM_ENC_READ_CLOCK_CONTROL;
9063  
9064  /*
9065   * DP_STREAM_ENC_RESET_CONTROL enum
9066   */
9067  
9068  typedef enum DP_STREAM_ENC_RESET_CONTROL {
9069  DP_STREAM_ENC_NOT_RESET                  = 0x00000000,
9070  DP_STREAM_ENC_RESET                      = 0x00000001,
9071  } DP_STREAM_ENC_RESET_CONTROL;
9072  
9073  /*
9074   * DP_STREAM_ENC_STREAM_ACTIVE enum
9075   */
9076  
9077  typedef enum DP_STREAM_ENC_STREAM_ACTIVE {
9078  DP_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE    = 0x00000000,
9079  DP_STREAM_ENC_VIDEO_STREAM_ACTIVE        = 0x00000001,
9080  } DP_STREAM_ENC_STREAM_ACTIVE;
9081  
9082  /*******************************************************
9083   * DP_SYM32_ENC Enums
9084   *******************************************************/
9085  
9086  /*
9087   * ENUM_DP_SYM32_ENC_AUDIO_MUTE enum
9088   */
9089  
9090  typedef enum ENUM_DP_SYM32_ENC_AUDIO_MUTE {
9091  DP_SYM32_ENC_SDP_AUDIO_MUTE_NOT_FORCED   = 0x00000000,
9092  DP_SYM32_ENC_SDP_AUDIO_MUTE_FORCED       = 0x00000001,
9093  } ENUM_DP_SYM32_ENC_AUDIO_MUTE;
9094  
9095  /*
9096   * ENUM_DP_SYM32_ENC_CONTINUOUS_MODE enum
9097   */
9098  
9099  typedef enum ENUM_DP_SYM32_ENC_CONTINUOUS_MODE {
9100  DP_SYM32_ENC_ONE_SHOT_MODE               = 0x00000000,
9101  DP_SYM32_ENC_CONTINUOUS_MODE             = 0x00000001,
9102  } ENUM_DP_SYM32_ENC_CONTINUOUS_MODE;
9103  
9104  /*
9105   * ENUM_DP_SYM32_ENC_CRC_VALID enum
9106   */
9107  
9108  typedef enum ENUM_DP_SYM32_ENC_CRC_VALID {
9109  DP_SYM32_ENC_CRC_NOT_VALID               = 0x00000000,
9110  DP_SYM32_ENC_CRC_VALID                   = 0x00000001,
9111  } ENUM_DP_SYM32_ENC_CRC_VALID;
9112  
9113  /*
9114   * ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH enum
9115   */
9116  
9117  typedef enum ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH {
9118  DP_SYM32_ENC_COMPONENT_DEPTH_6BPC        = 0x00000000,
9119  DP_SYM32_ENC_COMPONENT_DEPTH_8BPC        = 0x00000001,
9120  DP_SYM32_ENC_COMPONENT_DEPTH_10BPC       = 0x00000002,
9121  DP_SYM32_ENC_COMPONENT_DEPTH_12BPC       = 0x00000003,
9122  } ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH;
9123  
9124  /*
9125   * ENUM_DP_SYM32_ENC_ENABLE enum
9126   */
9127  
9128  typedef enum ENUM_DP_SYM32_ENC_ENABLE {
9129  DP_SYM32_ENC_DISABLE                     = 0x00000000,
9130  DP_SYM32_ENC_ENABLE                      = 0x00000001,
9131  } ENUM_DP_SYM32_ENC_ENABLE;
9132  
9133  /*
9134   * ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED enum
9135   */
9136  
9137  typedef enum ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED {
9138  DP_SYM32_ENC_GSP_DEADLINE_NOT_MISSED     = 0x00000000,
9139  DP_SYM32_ENC_GSP_DEADLINE_MISSED         = 0x00000001,
9140  } ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED;
9141  
9142  /*
9143   * ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION enum
9144   */
9145  
9146  typedef enum ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION {
9147  DP_SYM32_ENC_GSP_SEND_AT_LINE_NUMBER     = 0x00000000,
9148  DP_SYM32_ENC_GSP_SEND_AT_EARLIEST_TIME   = 0x00000001,
9149  } ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION;
9150  
9151  /*
9152   * ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE enum
9153   */
9154  
9155  typedef enum ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE {
9156  DP_SYM32_ENC_GSP_PAYLOAD_SIZE_32         = 0x00000000,
9157  DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED0  = 0x00000001,
9158  DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED1  = 0x00000002,
9159  DP_SYM32_ENC_GSP_PAYLOAD_SIZE_128        = 0x00000003,
9160  } ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE;
9161  
9162  /*
9163   * ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING enum
9164   */
9165  
9166  typedef enum ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING {
9167  DP_SYM32_ENC_GSP_TRIGGER_NOT_PENDING     = 0x00000000,
9168  DP_SYM32_ENC_GSP_TRIGGER_PENDING         = 0x00000001,
9169  } ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING;
9170  
9171  /*
9172   * ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM enum
9173   */
9174  
9175  typedef enum ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM {
9176  DP_SYM32_ENC_MEM_PWR_NO_FORCE_REQUEST    = 0x00000000,
9177  DP_SYM32_ENC_MEM_PWR_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
9178  DP_SYM32_ENC_MEM_PWR_FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
9179  DP_SYM32_ENC_MEM_PWR_FORCE_SHUT_DOWN_REQUEST = 0x00000003,
9180  } ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM;
9181  
9182  /*
9183   * ENUM_DP_SYM32_ENC_OVERFLOW_STATUS enum
9184   */
9185  
9186  typedef enum ENUM_DP_SYM32_ENC_OVERFLOW_STATUS {
9187  DP_SYM32_ENC_NO_OVERFLOW_OCCURRED        = 0x00000000,
9188  DP_SYM32_ENC_OVERFLOW_OCCURRED           = 0x00000001,
9189  } ENUM_DP_SYM32_ENC_OVERFLOW_STATUS;
9190  
9191  /*
9192   * ENUM_DP_SYM32_ENC_PENDING enum
9193   */
9194  
9195  typedef enum ENUM_DP_SYM32_ENC_PENDING {
9196  DP_SYM32_ENC_NOT_PENDING                 = 0x00000000,
9197  DP_SYM32_ENC_PENDING                     = 0x00000001,
9198  } ENUM_DP_SYM32_ENC_PENDING;
9199  
9200  /*
9201   * ENUM_DP_SYM32_ENC_PIXEL_ENCODING enum
9202   */
9203  
9204  typedef enum ENUM_DP_SYM32_ENC_PIXEL_ENCODING {
9205  DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444 = 0x00000000,
9206  DP_SYM32_ENC_PIXEL_ENCODING_YCBCR422     = 0x00000001,
9207  DP_SYM32_ENC_PIXEL_ENCODING_YCBCR420     = 0x00000002,
9208  DP_SYM32_ENC_PIXEL_ENCODING_Y_ONLY       = 0x00000003,
9209  } ENUM_DP_SYM32_ENC_PIXEL_ENCODING;
9210  
9211  /*
9212   * ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE enum
9213   */
9214  
9215  typedef enum ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE {
9216  DP_SYM32_ENC_UNCOMPRESSED_FORMAT         = 0x00000000,
9217  DP_SYM32_ENC_COMPRESSED_FORMAT           = 0x00000001,
9218  } ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE;
9219  
9220  /*
9221   * ENUM_DP_SYM32_ENC_POWER_STATE_ENUM enum
9222   */
9223  
9224  typedef enum ENUM_DP_SYM32_ENC_POWER_STATE_ENUM {
9225  DP_SYM32_ENC_POWER_STATE_ENUM_ON         = 0x00000000,
9226  DP_SYM32_ENC_POWER_STATE_ENUM_LS         = 0x00000001,
9227  DP_SYM32_ENC_POWER_STATE_ENUM_DS         = 0x00000002,
9228  DP_SYM32_ENC_POWER_STATE_ENUM_SD         = 0x00000003,
9229  } ENUM_DP_SYM32_ENC_POWER_STATE_ENUM;
9230  
9231  /*
9232   * ENUM_DP_SYM32_ENC_RESET enum
9233   */
9234  
9235  typedef enum ENUM_DP_SYM32_ENC_RESET {
9236  DP_SYM32_ENC_NOT_RESET                   = 0x00000000,
9237  DP_SYM32_ENC_RESET                       = 0x00000001,
9238  } ENUM_DP_SYM32_ENC_RESET;
9239  
9240  /*
9241   * ENUM_DP_SYM32_ENC_SDP_PRIORITY enum
9242   */
9243  
9244  typedef enum ENUM_DP_SYM32_ENC_SDP_PRIORITY {
9245  DP_SYM32_ENC_SDP_LOW_PRIORITY            = 0x00000000,
9246  DP_SYM32_ENC_SDP_HIGH_PRIORITY           = 0x00000001,
9247  } ENUM_DP_SYM32_ENC_SDP_PRIORITY;
9248  
9249  /*
9250   * ENUM_DP_SYM32_ENC_SOF_REFERENCE enum
9251   */
9252  
9253  typedef enum ENUM_DP_SYM32_ENC_SOF_REFERENCE {
9254  DP_SYM32_ENC_DP_SOF                      = 0x00000000,
9255  DP_SYM32_ENC_OTG_SOF                     = 0x00000001,
9256  } ENUM_DP_SYM32_ENC_SOF_REFERENCE;
9257  
9258  /*
9259   * ENUM_DP_SYM32_ENC_VID_STREAM_DEFER enum
9260   */
9261  
9262  typedef enum ENUM_DP_SYM32_ENC_VID_STREAM_DEFER {
9263  DP_SYM32_ENC_VID_STREAM_NO_DEFER         = 0x00000000,
9264  DP_SYM32_ENC_VID_STREAM_DEFER_TO_HBLANK  = 0x00000001,
9265  DP_SYM32_ENC_VID_STREAM_DEFER_TO_VBLANK  = 0x00000002,
9266  } ENUM_DP_SYM32_ENC_VID_STREAM_DEFER;
9267  
9268  /*******************************************************
9269   * DP_DPHY_SYM32 Enums
9270   *******************************************************/
9271  
9272  /*
9273   * ENUM_DP_DPHY_SYM32_CRC_END_EVENT enum
9274   */
9275  
9276  typedef enum ENUM_DP_DPHY_SYM32_CRC_END_EVENT {
9277  DP_DPHY_SYM32_CRC_END_LLCP               = 0x00000000,
9278  DP_DPHY_SYM32_CRC_END_PS_ONLY            = 0x00000001,
9279  DP_DPHY_SYM32_CRC_END_PS_LT_SR           = 0x00000002,
9280  DP_DPHY_SYM32_CRC_END_PS_ANY             = 0x00000003,
9281  } ENUM_DP_DPHY_SYM32_CRC_END_EVENT;
9282  
9283  /*
9284   * ENUM_DP_DPHY_SYM32_CRC_START_EVENT enum
9285   */
9286  
9287  typedef enum ENUM_DP_DPHY_SYM32_CRC_START_EVENT {
9288  DP_DPHY_SYM32_CRC_START_LLCP             = 0x00000000,
9289  DP_DPHY_SYM32_CRC_START_PS_ONLY          = 0x00000001,
9290  DP_DPHY_SYM32_CRC_START_PS_LT_SR         = 0x00000002,
9291  DP_DPHY_SYM32_CRC_START_PS_POST_LT_SR    = 0x00000003,
9292  DP_DPHY_SYM32_CRC_START_TP_START         = 0x00000004,
9293  } ENUM_DP_DPHY_SYM32_CRC_START_EVENT;
9294  
9295  /*
9296   * ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE enum
9297   */
9298  
9299  typedef enum ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE {
9300  DP_DPHY_SYM32_CRC_TAP_SOURCE_SCHEDULER   = 0x00000000,
9301  DP_DPHY_SYM32_CRC_TAP_SOURCE_SYMBOL_HANDLER = 0x00000001,
9302  DP_DPHY_SYM32_CRC_TAP_SOURCE_TP_GEN_MUX  = 0x00000002,
9303  } ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE;
9304  
9305  /*
9306   * ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS enum
9307   */
9308  
9309  typedef enum ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS {
9310  DP_DPHY_SYM32_CRC_USE_END_EVENT          = 0x00000000,
9311  DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS        = 0x00000001,
9312  } ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS;
9313  
9314  /*
9315   * ENUM_DP_DPHY_SYM32_ENABLE enum
9316   */
9317  
9318  typedef enum ENUM_DP_DPHY_SYM32_ENABLE {
9319  DP_DPHY_SYM32_DISABLE                    = 0x00000000,
9320  DP_DPHY_SYM32_ENABLE                     = 0x00000001,
9321  } ENUM_DP_DPHY_SYM32_ENABLE;
9322  
9323  /*
9324   * ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE enum
9325   */
9326  
9327  typedef enum ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE {
9328  DP_DPHY_SYM32_ENCRYPT_TYPE0              = 0x00000000,
9329  DP_DPHY_SYM32_ENCRYPT_TYPE1              = 0x00000001,
9330  } ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE;
9331  
9332  /*
9333   * ENUM_DP_DPHY_SYM32_MODE enum
9334   */
9335  
9336  typedef enum ENUM_DP_DPHY_SYM32_MODE {
9337  DP_DPHY_SYM32_LT_TPS1                    = 0x00000000,
9338  DP_DPHY_SYM32_LT_TPS2                    = 0x00000001,
9339  DP_DPHY_SYM32_ACTIVE                     = 0x00000002,
9340  DP_DPHY_SYM32_TEST                       = 0x00000003,
9341  } ENUM_DP_DPHY_SYM32_MODE;
9342  
9343  /*
9344   * ENUM_DP_DPHY_SYM32_NUM_LANES enum
9345   */
9346  
9347  typedef enum ENUM_DP_DPHY_SYM32_NUM_LANES {
9348  DP_DPHY_SYM32_1LANE                      = 0x00000000,
9349  DP_DPHY_SYM32_2LANE                      = 0x00000001,
9350  DP_DPHY_SYM32_RESERVED                   = 0x00000002,
9351  DP_DPHY_SYM32_4LANE                      = 0x00000003,
9352  } ENUM_DP_DPHY_SYM32_NUM_LANES;
9353  
9354  /*
9355   * ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING enum
9356   */
9357  
9358  typedef enum ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING {
9359  DP_DPHY_SYM32_NO_RATE_UPDATE_PENDING     = 0x00000000,
9360  DP_DPHY_SYM32_RATE_UPDATE_PENDING        = 0x00000001,
9361  } ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING;
9362  
9363  /*
9364   * ENUM_DP_DPHY_SYM32_RESET enum
9365   */
9366  
9367  typedef enum ENUM_DP_DPHY_SYM32_RESET {
9368  DP_DPHY_SYM32_NOT_RESET                  = 0x00000000,
9369  DP_DPHY_SYM32_RESET                      = 0x00000001,
9370  } ENUM_DP_DPHY_SYM32_RESET;
9371  
9372  /*
9373   * ENUM_DP_DPHY_SYM32_RESET_STATUS enum
9374   */
9375  
9376  typedef enum ENUM_DP_DPHY_SYM32_RESET_STATUS {
9377  DP_DPHY_SYM32_RESET_STATUS_DEASSERTED    = 0x00000000,
9378  DP_DPHY_SYM32_RESET_STATUS_ASSERTED      = 0x00000001,
9379  } ENUM_DP_DPHY_SYM32_RESET_STATUS;
9380  
9381  /*
9382   * ENUM_DP_DPHY_SYM32_SAT_UPDATE enum
9383   */
9384  
9385  typedef enum ENUM_DP_DPHY_SYM32_SAT_UPDATE {
9386  DP_DPHY_SYM32_SAT_NO_UPDATE              = 0x00000000,
9387  DP_DPHY_SYM32_SAT_TRIGGER_UPDATE         = 0x00000001,
9388  DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE       = 0x00000002,
9389  } ENUM_DP_DPHY_SYM32_SAT_UPDATE;
9390  
9391  /*
9392   * ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING enum
9393   */
9394  
9395  typedef enum ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING {
9396  DP_DPHY_SYM32_SAT_NO_UPDATE_PENDING      = 0x00000000,
9397  DP_DPHY_SYM32_SAT_TRIGGER_UPDATE_PENDING = 0x00000001,
9398  DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE_PENDING = 0x00000002,
9399  } ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING;
9400  
9401  /*
9402   * ENUM_DP_DPHY_SYM32_STATUS enum
9403   */
9404  
9405  typedef enum ENUM_DP_DPHY_SYM32_STATUS {
9406  DP_DPHY_SYM32_STATUS_IDLE                = 0x00000000,
9407  DP_DPHY_SYM32_STATUS_ENABLED             = 0x00000001,
9408  } ENUM_DP_DPHY_SYM32_STATUS;
9409  
9410  /*
9411   * ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE enum
9412   */
9413  
9414  typedef enum ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE {
9415  DP_DPHY_SYM32_STREAM_OVR_NONE            = 0x00000000,
9416  DP_DPHY_SYM32_STREAM_OVR_REPLACE         = 0x00000001,
9417  DP_DPHY_SYM32_STREAM_OVR_ALWAYS          = 0x00000002,
9418  } ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE;
9419  
9420  /*
9421   * ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE enum
9422   */
9423  
9424  typedef enum ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE {
9425  DP_DPHY_SYM32_STREAM_OVR_TYPE_DATA       = 0x00000000,
9426  DP_DPHY_SYM32_STREAM_OVR_TYPE_CONTROL    = 0x00000001,
9427  } ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE;
9428  
9429  /*
9430   * ENUM_DP_DPHY_SYM32_TP_PRBS_SEL enum
9431   */
9432  
9433  typedef enum ENUM_DP_DPHY_SYM32_TP_PRBS_SEL {
9434  DP_DPHY_SYM32_TP_PRBS_SEL_PRBS7          = 0x00000000,
9435  DP_DPHY_SYM32_TP_PRBS_SEL_PRBS9          = 0x00000001,
9436  DP_DPHY_SYM32_TP_PRBS_SEL_PRBS11         = 0x00000002,
9437  DP_DPHY_SYM32_TP_PRBS_SEL_PRBS15         = 0x00000003,
9438  DP_DPHY_SYM32_TP_PRBS_SEL_PRBS23         = 0x00000004,
9439  DP_DPHY_SYM32_TP_PRBS_SEL_PRBS31         = 0x00000005,
9440  } ENUM_DP_DPHY_SYM32_TP_PRBS_SEL;
9441  
9442  /*
9443   * ENUM_DP_DPHY_SYM32_TP_SELECT enum
9444   */
9445  
9446  typedef enum ENUM_DP_DPHY_SYM32_TP_SELECT {
9447  DP_DPHY_SYM32_TP_SELECT_TPS1             = 0x00000000,
9448  DP_DPHY_SYM32_TP_SELECT_TPS2             = 0x00000001,
9449  DP_DPHY_SYM32_TP_SELECT_PRBS             = 0x00000002,
9450  DP_DPHY_SYM32_TP_SELECT_CUSTOM           = 0x00000003,
9451  DP_DPHY_SYM32_TP_SELECT_SQUARE           = 0x00000004,
9452  } ENUM_DP_DPHY_SYM32_TP_SELECT;
9453  
9454  /*******************************************************
9455   * APG Enums
9456   *******************************************************/
9457  
9458  /*
9459   * APG_AUDIO_CRC_CONTROL_CH_SEL enum
9460   */
9461  
9462  typedef enum APG_AUDIO_CRC_CONTROL_CH_SEL {
9463  APG_AUDIO_CRC_CH0_SIG                    = 0x00000000,
9464  APG_AUDIO_CRC_CH1_SIG                    = 0x00000001,
9465  APG_AUDIO_CRC_CH2_SIG                    = 0x00000002,
9466  APG_AUDIO_CRC_CH3_SIG                    = 0x00000003,
9467  APG_AUDIO_CRC_CH4_SIG                    = 0x00000004,
9468  APG_AUDIO_CRC_CH5_SIG                    = 0x00000005,
9469  APG_AUDIO_CRC_CH6_SIG                    = 0x00000006,
9470  APG_AUDIO_CRC_CH7_SIG                    = 0x00000007,
9471  APG_AUDIO_CRC_RESERVED_8                 = 0x00000008,
9472  APG_AUDIO_CRC_RESERVED_9                 = 0x00000009,
9473  APG_AUDIO_CRC_RESERVED_10                = 0x0000000a,
9474  APG_AUDIO_CRC_RESERVED_11                = 0x0000000b,
9475  APG_AUDIO_CRC_RESERVED_12                = 0x0000000c,
9476  APG_AUDIO_CRC_RESERVED_13                = 0x0000000d,
9477  APG_AUDIO_CRC_RESERVED_14                = 0x0000000e,
9478  APG_AUDIO_CRC_RESERVED_15                = 0x0000000f,
9479  } APG_AUDIO_CRC_CONTROL_CH_SEL;
9480  
9481  /*
9482   * APG_AUDIO_CRC_CONTROL_CONT enum
9483   */
9484  
9485  typedef enum APG_AUDIO_CRC_CONTROL_CONT {
9486  APG_AUDIO_CRC_ONESHOT                    = 0x00000000,
9487  APG_AUDIO_CRC_CONTINUOUS                 = 0x00000001,
9488  } APG_AUDIO_CRC_CONTROL_CONT;
9489  
9490  /*
9491   * APG_DBG_ACP_TYPE enum
9492   */
9493  
9494  typedef enum APG_DBG_ACP_TYPE {
9495  APG_ACP_TYPE_GENERIC_AUDIO               = 0x00000000,
9496  APG_ACP_TYPE_ICE60958_AUDIO              = 0x00000001,
9497  APG_ACP_TYPE_DVD_AUDIO                   = 0x00000002,
9498  APG_ACP_TYPE_SUPER_AUDIO_CD              = 0x00000003,
9499  } APG_DBG_ACP_TYPE;
9500  
9501  /*
9502   * APG_DBG_AUDIO_DTO_BASE enum
9503   */
9504  
9505  typedef enum APG_DBG_AUDIO_DTO_BASE {
9506  BASE_RATE_48KHZ                          = 0x00000000,
9507  BASE_RATE_44P1KHZ                        = 0x00000001,
9508  } APG_DBG_AUDIO_DTO_BASE;
9509  
9510  /*
9511   * APG_DBG_AUDIO_DTO_DIV enum
9512   */
9513  
9514  typedef enum APG_DBG_AUDIO_DTO_DIV {
9515  DIVISOR_BY1                              = 0x00000000,
9516  DIVISOR_BY2_RESERVED                     = 0x00000001,
9517  DIVISOR_BY3                              = 0x00000002,
9518  DIVISOR_BY4_RESERVED                     = 0x00000003,
9519  DIVISOR_BY5_RESERVED                     = 0x00000004,
9520  DIVISOR_BY6_RESERVED                     = 0x00000005,
9521  DIVISOR_BY7_RESERVED                     = 0x00000006,
9522  DIVISOR_BY8_RESERVED                     = 0x00000007,
9523  } APG_DBG_AUDIO_DTO_DIV;
9524  
9525  /*
9526   * APG_DBG_AUDIO_DTO_MULTI enum
9527   */
9528  
9529  typedef enum APG_DBG_AUDIO_DTO_MULTI {
9530  MULTIPLE_BY1                             = 0x00000000,
9531  MULTIPLE_BY2                             = 0x00000001,
9532  MULTIPLE_BY3_RESERVED                    = 0x00000002,
9533  MULTIPLE_BY4                             = 0x00000003,
9534  MULTIPLE_RESERVED                        = 0x00000004,
9535  } APG_DBG_AUDIO_DTO_MULTI;
9536  
9537  /*
9538   * APG_DBG_MUX_SEL enum
9539   */
9540  
9541  typedef enum APG_DBG_MUX_SEL {
9542  APG_FUNCTIONAL_MODE                      = 0x00000000,
9543  APG_DEBUG_AUDIO_MODE                     = 0x00000001,
9544  } APG_DBG_MUX_SEL;
9545  
9546  /*
9547   * APG_DP_ASP_CHANNEL_COUNT_OVERRIDE enum
9548   */
9549  
9550  typedef enum APG_DP_ASP_CHANNEL_COUNT_OVERRIDE {
9551  APG_DP_ASP_CHANNEL_COUNT_FROM_AZ         = 0x00000000,
9552  APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 0x00000001,
9553  } APG_DP_ASP_CHANNEL_COUNT_OVERRIDE;
9554  
9555  /*
9556   * APG_MEM_POWER_STATE enum
9557   */
9558  
9559  typedef enum APG_MEM_POWER_STATE {
9560  APG_MEM_POWER_STATE_ON                   = 0x00000000,
9561  APG_MEM_POWER_STATE_LS                   = 0x00000001,
9562  APG_MEM_POWER_STATE_DS                   = 0x00000002,
9563  APG_MEM_POWER_STATE_SD                   = 0x00000003,
9564  } APG_MEM_POWER_STATE;
9565  
9566  /*
9567   * APG_MEM_PWR_DIS_CTRL enum
9568   */
9569  
9570  typedef enum APG_MEM_PWR_DIS_CTRL {
9571  APG_MEM_ENABLE_MEM_PWR_CTRL              = 0x00000000,
9572  APG_MEM_DISABLE_MEM_PWR_CTRL             = 0x00000001,
9573  } APG_MEM_PWR_DIS_CTRL;
9574  
9575  /*
9576   * APG_MEM_PWR_FORCE_CTRL enum
9577   */
9578  
9579  typedef enum APG_MEM_PWR_FORCE_CTRL {
9580  APG_MEM_NO_FORCE_REQUEST                 = 0x00000000,
9581  APG_MEM_FORCE_LIGHT_SLEEP_REQUEST        = 0x00000001,
9582  APG_MEM_FORCE_DEEP_SLEEP_REQUEST         = 0x00000002,
9583  APG_MEM_FORCE_SHUT_DOWN_REQUEST          = 0x00000003,
9584  } APG_MEM_PWR_FORCE_CTRL;
9585  
9586  /*
9587   * APG_PACKET_CONTROL_ACP_SOURCE enum
9588   */
9589  
9590  typedef enum APG_PACKET_CONTROL_ACP_SOURCE {
9591  APG_ACP_SOURCE_NO_OVERRIDE               = 0x00000000,
9592  APG_ACP_OVERRIDE                         = 0x00000001,
9593  } APG_PACKET_CONTROL_ACP_SOURCE;
9594  
9595  /*
9596   * APG_PACKET_CONTROL_AUDIO_INFO_SOURCE enum
9597   */
9598  
9599  typedef enum APG_PACKET_CONTROL_AUDIO_INFO_SOURCE {
9600  APG_INFOFRAME_SOURCE_NO_OVERRIDE         = 0x00000000,
9601  APG_INFOFRAME_SOURCE_FROM_APG_REGISTERS  = 0x00000001,
9602  } APG_PACKET_CONTROL_AUDIO_INFO_SOURCE;
9603  
9604  /*
9605   * APG_RAMP_CONTROL_SIGN enum
9606   */
9607  
9608  typedef enum APG_RAMP_CONTROL_SIGN {
9609  APG_RAMP_SIGNED                          = 0x00000000,
9610  APG_RAMP_UNSIGNED                        = 0x00000001,
9611  } APG_RAMP_CONTROL_SIGN;
9612  
9613  /*******************************************************
9614   * DCIO Enums
9615   *******************************************************/
9616  
9617  /*
9618   * DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL enum
9619   */
9620  
9621  typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL {
9622  DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1 = 0x00000000,
9623  DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2 = 0x00000001,
9624  DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3 = 0x00000002,
9625  DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4 = 0x00000003,
9626  DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5 = 0x00000004,
9627  DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6 = 0x00000005,
9628  } DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL;
9629  
9630  /*
9631   * DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL enum
9632   */
9633  
9634  typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL {
9635  DCIO_TEST_CLK_SEL_DISPCLK                = 0x00000000,
9636  DCIO_TEST_CLK_SEL_GATED_DISPCLK          = 0x00000001,
9637  DCIO_TEST_CLK_SEL_SOCCLK                 = 0x00000002,
9638  } DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL;
9639  
9640  /*
9641   * DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS enum
9642   */
9643  
9644  typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS {
9645  DCIO_DISPCLK_R_DCIO_GATE_DISABLE         = 0x00000000,
9646  DCIO_DISPCLK_R_DCIO_GATE_ENABLE          = 0x00000001,
9647  } DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS;
9648  
9649  /*
9650   * DCIO_DBG_ASYNC_4BIT_SEL enum
9651   */
9652  
9653  typedef enum DCIO_DBG_ASYNC_4BIT_SEL {
9654  DCIO_DBG_ASYNC_4BIT_SEL_3TO0             = 0x00000000,
9655  DCIO_DBG_ASYNC_4BIT_SEL_7TO4             = 0x00000001,
9656  DCIO_DBG_ASYNC_4BIT_SEL_11TO8            = 0x00000002,
9657  DCIO_DBG_ASYNC_4BIT_SEL_15TO12           = 0x00000003,
9658  DCIO_DBG_ASYNC_4BIT_SEL_19TO16           = 0x00000004,
9659  DCIO_DBG_ASYNC_4BIT_SEL_23TO20           = 0x00000005,
9660  DCIO_DBG_ASYNC_4BIT_SEL_27TO24           = 0x00000006,
9661  DCIO_DBG_ASYNC_4BIT_SEL_31TO28           = 0x00000007,
9662  } DCIO_DBG_ASYNC_4BIT_SEL;
9663  
9664  /*
9665   * DCIO_DBG_ASYNC_BLOCK_SEL enum
9666   */
9667  
9668  typedef enum DCIO_DBG_ASYNC_BLOCK_SEL {
9669  DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE        = 0x00000000,
9670  DCIO_DBG_ASYNC_BLOCK_SEL_DCCG            = 0x00000001,
9671  DCIO_DBG_ASYNC_BLOCK_SEL_DCIO            = 0x00000002,
9672  DCIO_DBG_ASYNC_BLOCK_SEL_DIO             = 0x00000003,
9673  } DCIO_DBG_ASYNC_BLOCK_SEL;
9674  
9675  /*
9676   * DCIO_DCRXPHY_SOFT_RESET enum
9677   */
9678  
9679  typedef enum DCIO_DCRXPHY_SOFT_RESET {
9680  DCIO_DCRXPHY_SOFT_RESET_DEASSERT         = 0x00000000,
9681  DCIO_DCRXPHY_SOFT_RESET_ASSERT           = 0x00000001,
9682  } DCIO_DCRXPHY_SOFT_RESET;
9683  
9684  /*
9685   * DCIO_DC_GENERICA_SEL enum
9686   */
9687  
9688  typedef enum DCIO_DC_GENERICA_SEL {
9689  DCIO_GENERICA_SEL_STEREOSYNC             = 0x00000001,
9690  DCIO_GENERICA_SEL_GENERICA_DCCG          = 0x0000000a,
9691  DCIO_GENERICA_SEL_SYNCEN                 = 0x0000000b,
9692  } DCIO_DC_GENERICA_SEL;
9693  
9694  /*
9695   * DCIO_DC_GENERICB_SEL enum
9696   */
9697  
9698  typedef enum DCIO_DC_GENERICB_SEL {
9699  DCIO_GENERICB_SEL_STEREOSYNC             = 0x00000001,
9700  DCIO_GENERICB_SEL_GENERICB_DCCG          = 0x0000000a,
9701  DCIO_GENERICB_SEL_SYNCEN                 = 0x0000000b,
9702  } DCIO_DC_GENERICB_SEL;
9703  
9704  /*
9705   * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL enum
9706   */
9707  
9708  typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL {
9709  DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2         = 0x00000000,
9710  DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2         = 0x00000001,
9711  DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2         = 0x00000002,
9712  DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2         = 0x00000003,
9713  DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2         = 0x00000004,
9714  DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2         = 0x00000005,
9715  DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2         = 0x00000006,
9716  } DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL;
9717  
9718  /*
9719   * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL enum
9720   */
9721  
9722  typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL {
9723  DCIO_UNIPHYA_FBDIV_CLK                   = 0x00000000,
9724  DCIO_UNIPHYB_FBDIV_CLK                   = 0x00000001,
9725  DCIO_UNIPHYC_FBDIV_CLK                   = 0x00000002,
9726  DCIO_UNIPHYD_FBDIV_CLK                   = 0x00000003,
9727  DCIO_UNIPHYE_FBDIV_CLK                   = 0x00000004,
9728  DCIO_UNIPHYF_FBDIV_CLK                   = 0x00000005,
9729  DCIO_UNIPHYG_FBDIV_CLK                   = 0x00000006,
9730  } DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL;
9731  
9732  /*
9733   * DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL enum
9734   */
9735  
9736  typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL {
9737  DCIO_UNIPHYA_FBDIV_SSC_CLK               = 0x00000000,
9738  DCIO_UNIPHYB_FBDIV_SSC_CLK               = 0x00000001,
9739  DCIO_UNIPHYC_FBDIV_SSC_CLK               = 0x00000002,
9740  DCIO_UNIPHYD_FBDIV_SSC_CLK               = 0x00000003,
9741  DCIO_UNIPHYE_FBDIV_SSC_CLK               = 0x00000004,
9742  DCIO_UNIPHYF_FBDIV_SSC_CLK               = 0x00000005,
9743  DCIO_UNIPHYG_FBDIV_SSC_CLK               = 0x00000006,
9744  } DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL;
9745  
9746  /*
9747   * DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL enum
9748   */
9749  
9750  typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL {
9751  DCIO_UNIPHYA_TEST_REFDIV_CLK             = 0x00000000,
9752  DCIO_UNIPHYB_TEST_REFDIV_CLK             = 0x00000001,
9753  DCIO_UNIPHYC_TEST_REFDIV_CLK             = 0x00000002,
9754  DCIO_UNIPHYD_TEST_REFDIV_CLK             = 0x00000003,
9755  DCIO_UNIPHYE_TEST_REFDIV_CLK             = 0x00000004,
9756  DCIO_UNIPHYF_TEST_REFDIV_CLK             = 0x00000005,
9757  DCIO_UNIPHYG_TEST_REFDIV_CLK             = 0x00000006,
9758  } DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL;
9759  
9760  /*
9761   * DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE enum
9762   */
9763  
9764  typedef enum DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE {
9765  DCIO_DPRX_LOOPBACK_ENABLE_NORMAL         = 0x00000000,
9766  DCIO_DPRX_LOOPBACK_ENABLE_LOOP           = 0x00000001,
9767  } DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE;
9768  
9769  /*
9770   * DCIO_DC_GPU_TIMER_READ_SELECT enum
9771   */
9772  
9773  typedef enum DCIO_DC_GPU_TIMER_READ_SELECT {
9774  DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0x00000000,
9775  DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 0x00000001,
9776  DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 0x00000002,
9777  DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 0x00000003,
9778  DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 0x00000004,
9779  DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 0x00000005,
9780  } DCIO_DC_GPU_TIMER_READ_SELECT;
9781  
9782  /*
9783   * DCIO_DC_GPU_TIMER_START_POSITION enum
9784   */
9785  
9786  typedef enum DCIO_DC_GPU_TIMER_START_POSITION {
9787  DCIO_GPU_TIMER_START_0_END_27            = 0x00000000,
9788  DCIO_GPU_TIMER_START_1_END_28            = 0x00000001,
9789  DCIO_GPU_TIMER_START_2_END_29            = 0x00000002,
9790  DCIO_GPU_TIMER_START_3_END_30            = 0x00000003,
9791  DCIO_GPU_TIMER_START_4_END_31            = 0x00000004,
9792  DCIO_GPU_TIMER_START_6_END_33            = 0x00000005,
9793  DCIO_GPU_TIMER_START_8_END_35            = 0x00000006,
9794  DCIO_GPU_TIMER_START_10_END_37           = 0x00000007,
9795  } DCIO_DC_GPU_TIMER_START_POSITION;
9796  
9797  /*
9798   * DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL enum
9799   */
9800  
9801  typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL {
9802  DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE        = 0x00000000,
9803  DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1          = 0x00000001,
9804  DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2          = 0x00000002,
9805  DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 0x00000003,
9806  } DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL;
9807  
9808  /*
9809   * DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL enum
9810   */
9811  
9812  typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL {
9813  DCIO_HSYNCA_OUTPUT_SEL_DISABLE           = 0x00000000,
9814  DCIO_HSYNCA_OUTPUT_SEL_PPLL1             = 0x00000001,
9815  DCIO_HSYNCA_OUTPUT_SEL_PPLL2             = 0x00000002,
9816  DCIO_HSYNCA_OUTPUT_SEL_RESERVED          = 0x00000003,
9817  } DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL;
9818  
9819  /*
9820   * DCIO_DIO_EXT_VSYNC_MASK enum
9821   */
9822  
9823  typedef enum DCIO_DIO_EXT_VSYNC_MASK {
9824  DCIO_EXT_VSYNC_MASK_NONE                 = 0x00000000,
9825  DCIO_EXT_VSYNC_MASK_PIPE0                = 0x00000001,
9826  DCIO_EXT_VSYNC_MASK_PIPE1                = 0x00000002,
9827  DCIO_EXT_VSYNC_MASK_PIPE2                = 0x00000003,
9828  DCIO_EXT_VSYNC_MASK_PIPE3                = 0x00000004,
9829  DCIO_EXT_VSYNC_MASK_PIPE4                = 0x00000005,
9830  DCIO_EXT_VSYNC_MASK_PIPE5                = 0x00000006,
9831  DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE       = 0x00000007,
9832  } DCIO_DIO_EXT_VSYNC_MASK;
9833  
9834  /*
9835   * DCIO_DIO_OTG_EXT_VSYNC_MUX enum
9836   */
9837  
9838  typedef enum DCIO_DIO_OTG_EXT_VSYNC_MUX {
9839  DCIO_EXT_VSYNC_MUX_SWAPLOCKB             = 0x00000000,
9840  DCIO_EXT_VSYNC_MUX_OTG0                  = 0x00000001,
9841  DCIO_EXT_VSYNC_MUX_OTG1                  = 0x00000002,
9842  DCIO_EXT_VSYNC_MUX_OTG2                  = 0x00000003,
9843  DCIO_EXT_VSYNC_MUX_OTG3                  = 0x00000004,
9844  DCIO_EXT_VSYNC_MUX_OTG4                  = 0x00000005,
9845  DCIO_EXT_VSYNC_MUX_OTG5                  = 0x00000006,
9846  DCIO_EXT_VSYNC_MUX_GENERICB              = 0x00000007,
9847  } DCIO_DIO_OTG_EXT_VSYNC_MUX;
9848  
9849  /*
9850   * DCIO_DPCS_INTERRUPT_MASK enum
9851   */
9852  
9853  typedef enum DCIO_DPCS_INTERRUPT_MASK {
9854  DCIO_DPCS_INTERRUPT_DISABLE              = 0x00000000,
9855  DCIO_DPCS_INTERRUPT_ENABLE               = 0x00000001,
9856  } DCIO_DPCS_INTERRUPT_MASK;
9857  
9858  /*
9859   * DCIO_DPCS_INTERRUPT_TYPE enum
9860   */
9861  
9862  typedef enum DCIO_DPCS_INTERRUPT_TYPE {
9863  DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED     = 0x00000000,
9864  DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED     = 0x00000001,
9865  } DCIO_DPCS_INTERRUPT_TYPE;
9866  
9867  /*
9868   * DCIO_DSYNC_SOFT_RESET enum
9869   */
9870  
9871  typedef enum DCIO_DSYNC_SOFT_RESET {
9872  DCIO_DSYNC_SOFT_RESET_DEASSERT           = 0x00000000,
9873  DCIO_DSYNC_SOFT_RESET_ASSERT             = 0x00000001,
9874  } DCIO_DSYNC_SOFT_RESET;
9875  
9876  /*
9877   * DCIO_GENLK_CLK_GSL_MASK enum
9878   */
9879  
9880  typedef enum DCIO_GENLK_CLK_GSL_MASK {
9881  DCIO_GENLK_CLK_GSL_MASK_NO               = 0x00000000,
9882  DCIO_GENLK_CLK_GSL_MASK_TIMING           = 0x00000001,
9883  DCIO_GENLK_CLK_GSL_MASK_STEREO           = 0x00000002,
9884  } DCIO_GENLK_CLK_GSL_MASK;
9885  
9886  /*
9887   * DCIO_GENLK_VSYNC_GSL_MASK enum
9888   */
9889  
9890  typedef enum DCIO_GENLK_VSYNC_GSL_MASK {
9891  DCIO_GENLK_VSYNC_GSL_MASK_NO             = 0x00000000,
9892  DCIO_GENLK_VSYNC_GSL_MASK_TIMING         = 0x00000001,
9893  DCIO_GENLK_VSYNC_GSL_MASK_STEREO         = 0x00000002,
9894  } DCIO_GENLK_VSYNC_GSL_MASK;
9895  
9896  /*
9897   * DCIO_GSL_SEL enum
9898   */
9899  
9900  typedef enum DCIO_GSL_SEL {
9901  DCIO_GSL_SEL_GROUP_0                     = 0x00000000,
9902  DCIO_GSL_SEL_GROUP_1                     = 0x00000001,
9903  DCIO_GSL_SEL_GROUP_2                     = 0x00000002,
9904  } DCIO_GSL_SEL;
9905  
9906  /*
9907   * DCIO_PHY_HPO_ENC_SRC_SEL enum
9908   */
9909  
9910  typedef enum DCIO_PHY_HPO_ENC_SRC_SEL {
9911  HPO_SRC0                                 = 0x00000000,
9912  HPO_SRC_RESERVED                         = 0x00000001,
9913  } DCIO_PHY_HPO_ENC_SRC_SEL;
9914  
9915  /*
9916   * DCIO_SWAPLOCK_A_GSL_MASK enum
9917   */
9918  
9919  typedef enum DCIO_SWAPLOCK_A_GSL_MASK {
9920  DCIO_SWAPLOCK_A_GSL_MASK_NO              = 0x00000000,
9921  DCIO_SWAPLOCK_A_GSL_MASK_TIMING          = 0x00000001,
9922  DCIO_SWAPLOCK_A_GSL_MASK_STEREO          = 0x00000002,
9923  } DCIO_SWAPLOCK_A_GSL_MASK;
9924  
9925  /*
9926   * DCIO_SWAPLOCK_B_GSL_MASK enum
9927   */
9928  
9929  typedef enum DCIO_SWAPLOCK_B_GSL_MASK {
9930  DCIO_SWAPLOCK_B_GSL_MASK_NO              = 0x00000000,
9931  DCIO_SWAPLOCK_B_GSL_MASK_TIMING          = 0x00000001,
9932  DCIO_SWAPLOCK_B_GSL_MASK_STEREO          = 0x00000002,
9933  } DCIO_SWAPLOCK_B_GSL_MASK;
9934  
9935  /*
9936   * DCIO_UNIPHY_CHANNEL_XBAR_SOURCE enum
9937   */
9938  
9939  typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE {
9940  DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0      = 0x00000000,
9941  DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1      = 0x00000001,
9942  DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2      = 0x00000002,
9943  DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3      = 0x00000003,
9944  } DCIO_UNIPHY_CHANNEL_XBAR_SOURCE;
9945  
9946  /*
9947   * DCIO_UNIPHY_IMPCAL_SEL enum
9948   */
9949  
9950  typedef enum DCIO_UNIPHY_IMPCAL_SEL {
9951  DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE       = 0x00000000,
9952  DCIO_UNIPHY_IMPCAL_SEL_BINARY            = 0x00000001,
9953  } DCIO_UNIPHY_IMPCAL_SEL;
9954  
9955  /*
9956   * DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT enum
9957   */
9958  
9959  typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT {
9960  DCIO_UNIPHY_CHANNEL_NO_INVERSION         = 0x00000000,
9961  DCIO_UNIPHY_CHANNEL_INVERTED             = 0x00000001,
9962  } DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT;
9963  
9964  /*
9965   * DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK enum
9966   */
9967  
9968  typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK {
9969  DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0x00000000,
9970  DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW   = 0x00000001,
9971  DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 0x00000002,
9972  DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED = 0x00000003,
9973  } DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK;
9974  
9975  /*******************************************************
9976   * DCIO_CHIP Enums
9977   *******************************************************/
9978  
9979  /*
9980   * DCIOCHIP_AUX_ALL_PWR_OK enum
9981   */
9982  
9983  typedef enum DCIOCHIP_AUX_ALL_PWR_OK {
9984  DCIOCHIP_AUX_ALL_PWR_OK_0                = 0x00000000,
9985  DCIOCHIP_AUX_ALL_PWR_OK_1                = 0x00000001,
9986  } DCIOCHIP_AUX_ALL_PWR_OK;
9987  
9988  /*
9989   * DCIOCHIP_AUX_CSEL0P9 enum
9990   */
9991  
9992  typedef enum DCIOCHIP_AUX_CSEL0P9 {
9993  DCIOCHIP_AUX_CSEL_DEC1P0                 = 0x00000000,
9994  DCIOCHIP_AUX_CSEL_DEC0P9                 = 0x00000001,
9995  } DCIOCHIP_AUX_CSEL0P9;
9996  
9997  /*
9998   * DCIOCHIP_AUX_CSEL1P1 enum
9999   */
10000  
10001  typedef enum DCIOCHIP_AUX_CSEL1P1 {
10002  DCIOCHIP_AUX_CSEL_INC1P0                 = 0x00000000,
10003  DCIOCHIP_AUX_CSEL_INC1P1                 = 0x00000001,
10004  } DCIOCHIP_AUX_CSEL1P1;
10005  
10006  /*
10007   * DCIOCHIP_AUX_FALLSLEWSEL enum
10008   */
10009  
10010  typedef enum DCIOCHIP_AUX_FALLSLEWSEL {
10011  DCIOCHIP_AUX_FALLSLEWSEL_LOW             = 0x00000000,
10012  DCIOCHIP_AUX_FALLSLEWSEL_HIGH0           = 0x00000001,
10013  DCIOCHIP_AUX_FALLSLEWSEL_HIGH1           = 0x00000002,
10014  DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH       = 0x00000003,
10015  } DCIOCHIP_AUX_FALLSLEWSEL;
10016  
10017  /*
10018   * DCIOCHIP_AUX_HYS_TUNE enum
10019   */
10020  
10021  typedef enum DCIOCHIP_AUX_HYS_TUNE {
10022  DCIOCHIP_AUX_HYS_TUNE_0                  = 0x00000000,
10023  DCIOCHIP_AUX_HYS_TUNE_1                  = 0x00000001,
10024  DCIOCHIP_AUX_HYS_TUNE_2                  = 0x00000002,
10025  DCIOCHIP_AUX_HYS_TUNE_3                  = 0x00000003,
10026  } DCIOCHIP_AUX_HYS_TUNE;
10027  
10028  /*
10029   * DCIOCHIP_AUX_RECEIVER_SEL enum
10030   */
10031  
10032  typedef enum DCIOCHIP_AUX_RECEIVER_SEL {
10033  DCIOCHIP_AUX_RECEIVER_SEL_0              = 0x00000000,
10034  DCIOCHIP_AUX_RECEIVER_SEL_1              = 0x00000001,
10035  DCIOCHIP_AUX_RECEIVER_SEL_2              = 0x00000002,
10036  DCIOCHIP_AUX_RECEIVER_SEL_3              = 0x00000003,
10037  } DCIOCHIP_AUX_RECEIVER_SEL;
10038  
10039  /*
10040   * DCIOCHIP_AUX_RSEL0P9 enum
10041   */
10042  
10043  typedef enum DCIOCHIP_AUX_RSEL0P9 {
10044  DCIOCHIP_AUX_RSEL_DEC1P0                 = 0x00000000,
10045  DCIOCHIP_AUX_RSEL_DEC0P9                 = 0x00000001,
10046  } DCIOCHIP_AUX_RSEL0P9;
10047  
10048  /*
10049   * DCIOCHIP_AUX_RSEL1P1 enum
10050   */
10051  
10052  typedef enum DCIOCHIP_AUX_RSEL1P1 {
10053  DCIOCHIP_AUX_RSEL_INC1P0                 = 0x00000000,
10054  DCIOCHIP_AUX_RSEL_INC1P1                 = 0x00000001,
10055  } DCIOCHIP_AUX_RSEL1P1;
10056  
10057  /*
10058   * DCIOCHIP_AUX_SPIKESEL enum
10059   */
10060  
10061  typedef enum DCIOCHIP_AUX_SPIKESEL {
10062  DCIOCHIP_AUX_SPIKESEL_50NS               = 0x00000000,
10063  DCIOCHIP_AUX_SPIKESEL_10NS               = 0x00000001,
10064  } DCIOCHIP_AUX_SPIKESEL;
10065  
10066  /*
10067   * DCIOCHIP_AUX_VOD_TUNE enum
10068   */
10069  
10070  typedef enum DCIOCHIP_AUX_VOD_TUNE {
10071  DCIOCHIP_AUX_VOD_TUNE_0                  = 0x00000000,
10072  DCIOCHIP_AUX_VOD_TUNE_1                  = 0x00000001,
10073  DCIOCHIP_AUX_VOD_TUNE_2                  = 0x00000002,
10074  DCIOCHIP_AUX_VOD_TUNE_3                  = 0x00000003,
10075  } DCIOCHIP_AUX_VOD_TUNE;
10076  
10077  /*
10078   * DCIOCHIP_GPIO_MASK_EN enum
10079   */
10080  
10081  typedef enum DCIOCHIP_GPIO_MASK_EN {
10082  DCIOCHIP_GPIO_MASK_EN_HARDWARE           = 0x00000000,
10083  DCIOCHIP_GPIO_MASK_EN_SOFTWARE           = 0x00000001,
10084  } DCIOCHIP_GPIO_MASK_EN;
10085  
10086  /*
10087   * DCIOCHIP_HPD_SEL enum
10088   */
10089  
10090  typedef enum DCIOCHIP_HPD_SEL {
10091  DCIOCHIP_HPD_SEL_ASYNC                   = 0x00000000,
10092  DCIOCHIP_HPD_SEL_CLOCKED                 = 0x00000001,
10093  } DCIOCHIP_HPD_SEL;
10094  
10095  /*
10096   * DCIOCHIP_I2C_COMPSEL enum
10097   */
10098  
10099  typedef enum DCIOCHIP_I2C_COMPSEL {
10100  DCIOCHIP_I2C_REC_SCHMIT                  = 0x00000000,
10101  DCIOCHIP_I2C_REC_COMPARATOR              = 0x00000001,
10102  } DCIOCHIP_I2C_COMPSEL;
10103  
10104  /*
10105   * DCIOCHIP_I2C_FALLSLEWSEL enum
10106   */
10107  
10108  typedef enum DCIOCHIP_I2C_FALLSLEWSEL {
10109  DCIOCHIP_I2C_FALLSLEWSEL_00              = 0x00000000,
10110  DCIOCHIP_I2C_FALLSLEWSEL_01              = 0x00000001,
10111  DCIOCHIP_I2C_FALLSLEWSEL_10              = 0x00000002,
10112  DCIOCHIP_I2C_FALLSLEWSEL_11              = 0x00000003,
10113  } DCIOCHIP_I2C_FALLSLEWSEL;
10114  
10115  /*
10116   * DCIOCHIP_I2C_RECEIVER_SEL enum
10117   */
10118  
10119  typedef enum DCIOCHIP_I2C_RECEIVER_SEL {
10120  DCIOCHIP_I2C_RECEIVER_SEL_0              = 0x00000000,
10121  DCIOCHIP_I2C_RECEIVER_SEL_1              = 0x00000001,
10122  DCIOCHIP_I2C_RECEIVER_SEL_2              = 0x00000002,
10123  DCIOCHIP_I2C_RECEIVER_SEL_3              = 0x00000003,
10124  } DCIOCHIP_I2C_RECEIVER_SEL;
10125  
10126  /*
10127   * DCIOCHIP_I2C_VPH_1V2_EN enum
10128   */
10129  
10130  typedef enum DCIOCHIP_I2C_VPH_1V2_EN {
10131  DCIOCHIP_I2C_VPH_1V2_EN_0                = 0x00000000,
10132  DCIOCHIP_I2C_VPH_1V2_EN_1                = 0x00000001,
10133  } DCIOCHIP_I2C_VPH_1V2_EN;
10134  
10135  /*
10136   * DCIOCHIP_INVERT enum
10137   */
10138  
10139  typedef enum DCIOCHIP_INVERT {
10140  DCIOCHIP_POL_NON_INVERT                  = 0x00000000,
10141  DCIOCHIP_POL_INVERT                      = 0x00000001,
10142  } DCIOCHIP_INVERT;
10143  
10144  /*
10145   * DCIOCHIP_MASK enum
10146   */
10147  
10148  typedef enum DCIOCHIP_MASK {
10149  DCIOCHIP_MASK_DISABLE                    = 0x00000000,
10150  DCIOCHIP_MASK_ENABLE                     = 0x00000001,
10151  } DCIOCHIP_MASK;
10152  
10153  /*
10154   * DCIOCHIP_PAD_MODE enum
10155   */
10156  
10157  typedef enum DCIOCHIP_PAD_MODE {
10158  DCIOCHIP_PAD_MODE_DDC                    = 0x00000000,
10159  DCIOCHIP_PAD_MODE_DP                     = 0x00000001,
10160  } DCIOCHIP_PAD_MODE;
10161  
10162  /*
10163   * DCIOCHIP_PD_EN enum
10164   */
10165  
10166  typedef enum DCIOCHIP_PD_EN {
10167  DCIOCHIP_PD_EN_NOTALLOW                  = 0x00000000,
10168  DCIOCHIP_PD_EN_ALLOW                     = 0x00000001,
10169  } DCIOCHIP_PD_EN;
10170  
10171  /*
10172   * DCIOCHIP_REF_27_SRC_SEL enum
10173   */
10174  
10175  typedef enum DCIOCHIP_REF_27_SRC_SEL {
10176  DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER     = 0x00000000,
10177  DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 0x00000001,
10178  DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS      = 0x00000002,
10179  DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 0x00000003,
10180  } DCIOCHIP_REF_27_SRC_SEL;
10181  
10182  /*******************************************************
10183   * PWRSEQ Enums
10184   *******************************************************/
10185  
10186  /*
10187   * PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE enum
10188   */
10189  
10190  typedef enum PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE {
10191  PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_DISABLE    = 0x00000000,
10192  PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_ENABLE     = 0x00000001,
10193  } PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE;
10194  
10195  /*
10196   * PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN enum
10197   */
10198  
10199  typedef enum PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN {
10200  PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_NORMAL = 0x00000000,
10201  PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_PWM = 0x00000001,
10202  } PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN;
10203  
10204  /*
10205   * PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT enum
10206   */
10207  
10208  typedef enum PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT {
10209  PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL = 0x00000000,
10210  PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1 = 0x00000001,
10211  PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2 = 0x00000002,
10212  PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3 = 0x00000003,
10213  } PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT;
10214  
10215  /*
10216   * PWRSEQ_BL_PWM_CNTL_BL_PWM_EN enum
10217   */
10218  
10219  typedef enum PWRSEQ_BL_PWM_CNTL_BL_PWM_EN {
10220  PWRSEQ_BL_PWM_DISABLE                    = 0x00000000,
10221  PWRSEQ_BL_PWM_ENABLE                     = 0x00000001,
10222  } PWRSEQ_BL_PWM_CNTL_BL_PWM_EN;
10223  
10224  /*
10225   * PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN enum
10226   */
10227  
10228  typedef enum PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN {
10229  PWRSEQ_BL_PWM_FRACTIONAL_DISABLE         = 0x00000000,
10230  PWRSEQ_BL_PWM_FRACTIONAL_ENABLE          = 0x00000001,
10231  } PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN;
10232  
10233  /*
10234   * PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN enum
10235   */
10236  
10237  typedef enum PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN {
10238  PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0x00000000,
10239  PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 0x00000001,
10240  } PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN;
10241  
10242  /*
10243   * PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN enum
10244   */
10245  
10246  typedef enum PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN {
10247  PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0x00000000,
10248  PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM = 0x00000001,
10249  } PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN;
10250  
10251  /*
10252   * PWRSEQ_BL_PWM_GRP1_REG_LOCK enum
10253   */
10254  
10255  typedef enum PWRSEQ_BL_PWM_GRP1_REG_LOCK {
10256  PWRSEQ_BL_PWM_GRP1_REG_LOCK_DISABLE      = 0x00000000,
10257  PWRSEQ_BL_PWM_GRP1_REG_LOCK_ENABLE       = 0x00000001,
10258  } PWRSEQ_BL_PWM_GRP1_REG_LOCK;
10259  
10260  /*
10261   * PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START enum
10262   */
10263  
10264  typedef enum PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START {
10265  PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0x00000000,
10266  PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 0x00000001,
10267  } PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START;
10268  
10269  /*
10270   * PWRSEQ_GPIO_MASK_EN enum
10271   */
10272  
10273  typedef enum PWRSEQ_GPIO_MASK_EN {
10274  PWRSEQ_GPIO_MASK_EN_HARDWARE             = 0x00000000,
10275  PWRSEQ_GPIO_MASK_EN_SOFTWARE             = 0x00000001,
10276  } PWRSEQ_GPIO_MASK_EN;
10277  
10278  /*
10279   * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON enum
10280   */
10281  
10282  typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON {
10283  PWRSEQ_PANEL_BLON_OFF                    = 0x00000000,
10284  PWRSEQ_PANEL_BLON_ON                     = 0x00000001,
10285  } PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON;
10286  
10287  /*
10288   * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL enum
10289   */
10290  
10291  typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL {
10292  PWRSEQ_PANEL_BLON_POL_NON_INVERT         = 0x00000000,
10293  PWRSEQ_PANEL_BLON_POL_INVERT             = 0x00000001,
10294  } PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL;
10295  
10296  /*
10297   * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON enum
10298   */
10299  
10300  typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON {
10301  PWRSEQ_PANEL_DIGON_OFF                   = 0x00000000,
10302  PWRSEQ_PANEL_DIGON_ON                    = 0x00000001,
10303  } PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON;
10304  
10305  /*
10306   * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL enum
10307   */
10308  
10309  typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL {
10310  PWRSEQ_PANEL_DIGON_POL_NON_INVERT        = 0x00000000,
10311  PWRSEQ_PANEL_DIGON_POL_INVERT            = 0x00000001,
10312  } PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL;
10313  
10314  /*
10315   * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL enum
10316   */
10317  
10318  typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL {
10319  PWRSEQ_PANEL_SYNCEN_POL_NON_INVERT       = 0x00000000,
10320  PWRSEQ_PANEL_SYNCEN_POL_INVERT           = 0x00000001,
10321  } PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL;
10322  
10323  /*
10324   * PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE enum
10325   */
10326  
10327  typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE {
10328  PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_OFF = 0x00000000,
10329  PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_ON  = 0x00000001,
10330  } PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE;
10331  
10332  /*
10333   * PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN enum
10334   */
10335  
10336  typedef enum PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN {
10337  PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_BLON    = 0x00000000,
10338  PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_SEPARATE = 0x00000001,
10339  } PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN;
10340  
10341  /*******************************************************
10342   * AZCONTROLLER Enums
10343   *******************************************************/
10344  
10345  /*
10346   * AZ_CORB_SIZE enum
10347   */
10348  
10349  typedef enum AZ_CORB_SIZE {
10350  AZ_CORB_SIZE_2ENTRIES_RESERVED           = 0x00000000,
10351  AZ_CORB_SIZE_16ENTRIES_RESERVED          = 0x00000001,
10352  AZ_CORB_SIZE_256ENTRIES                  = 0x00000002,
10353  AZ_CORB_SIZE_RESERVED                    = 0x00000003,
10354  } AZ_CORB_SIZE;
10355  
10356  /*
10357   * AZ_GLOBAL_CAPABILITIES enum
10358   */
10359  
10360  typedef enum AZ_GLOBAL_CAPABILITIES {
10361  AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED = 0x00000000,
10362  AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED = 0x00000001,
10363  } AZ_GLOBAL_CAPABILITIES;
10364  
10365  /*
10366   * AZ_RIRB_SIZE enum
10367   */
10368  
10369  typedef enum AZ_RIRB_SIZE {
10370  AZ_RIRB_SIZE_2ENTRIES_RESERVED           = 0x00000000,
10371  AZ_RIRB_SIZE_16ENTRIES_RESERVED          = 0x00000001,
10372  AZ_RIRB_SIZE_256ENTRIES                  = 0x00000002,
10373  AZ_RIRB_SIZE_UNDEFINED                   = 0x00000003,
10374  } AZ_RIRB_SIZE;
10375  
10376  /*
10377   * AZ_RIRB_WRITE_POINTER_RESET enum
10378   */
10379  
10380  typedef enum AZ_RIRB_WRITE_POINTER_RESET {
10381  AZ_RIRB_WRITE_POINTER_NOT_RESET          = 0x00000000,
10382  AZ_RIRB_WRITE_POINTER_DO_RESET           = 0x00000001,
10383  } AZ_RIRB_WRITE_POINTER_RESET;
10384  
10385  /*
10386   * AZ_STATE_CHANGE_STATUS enum
10387   */
10388  
10389  typedef enum AZ_STATE_CHANGE_STATUS {
10390  AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT = 0x00000000,
10391  AZ_STATE_CHANGE_STATUS_CODEC_PRESENT     = 0x00000001,
10392  } AZ_STATE_CHANGE_STATUS;
10393  
10394  /*
10395   * CORB_READ_POINTER_RESET enum
10396   */
10397  
10398  typedef enum CORB_READ_POINTER_RESET {
10399  CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET = 0x00000000,
10400  CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET = 0x00000001,
10401  } CORB_READ_POINTER_RESET;
10402  
10403  /*
10404   * DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE enum
10405   */
10406  
10407  typedef enum DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE {
10408  DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE = 0x00000000,
10409  DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE = 0x00000001,
10410  } DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE;
10411  
10412  /*
10413   * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL enum
10414   */
10415  
10416  typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL {
10417  GENERIC_AZ_CONTROLLER_REGISTER_DISABLE   = 0x00000000,
10418  GENERIC_AZ_CONTROLLER_REGISTER_ENABLE    = 0x00000001,
10419  } GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL;
10420  
10421  /*
10422   * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED enum
10423   */
10424  
10425  typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED {
10426  GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED = 0x00000000,
10427  GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED = 0x00000001,
10428  } GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED;
10429  
10430  /*
10431   * GENERIC_AZ_CONTROLLER_REGISTER_STATUS enum
10432   */
10433  
10434  typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS {
10435  GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET = 0x00000000,
10436  GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET = 0x00000001,
10437  } GENERIC_AZ_CONTROLLER_REGISTER_STATUS;
10438  
10439  /*
10440   * GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED enum
10441   */
10442  
10443  typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED {
10444  GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED = 0x00000000,
10445  GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED = 0x00000001,
10446  } GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED;
10447  
10448  /*
10449   * GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE enum
10450   */
10451  
10452  typedef enum GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE {
10453  ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE   = 0x00000000,
10454  ACCEPT_UNSOLICITED_RESPONSE_ENABLE       = 0x00000001,
10455  } GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE;
10456  
10457  /*
10458   * GLOBAL_CONTROL_CONTROLLER_RESET enum
10459   */
10460  
10461  typedef enum GLOBAL_CONTROL_CONTROLLER_RESET {
10462  CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET  = 0x00000000,
10463  CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET = 0x00000001,
10464  } GLOBAL_CONTROL_CONTROLLER_RESET;
10465  
10466  /*
10467   * GLOBAL_CONTROL_FLUSH_CONTROL enum
10468   */
10469  
10470  typedef enum GLOBAL_CONTROL_FLUSH_CONTROL {
10471  FLUSH_CONTROL_FLUSH_NOT_STARTED          = 0x00000000,
10472  FLUSH_CONTROL_FLUSH_STARTED              = 0x00000001,
10473  } GLOBAL_CONTROL_FLUSH_CONTROL;
10474  
10475  /*
10476   * GLOBAL_STATUS_FLUSH_STATUS enum
10477   */
10478  
10479  typedef enum GLOBAL_STATUS_FLUSH_STATUS {
10480  GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED = 0x00000000,
10481  GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED   = 0x00000001,
10482  } GLOBAL_STATUS_FLUSH_STATUS;
10483  
10484  /*
10485   * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY enum
10486   */
10487  
10488  typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY {
10489  IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY = 0x00000000,
10490  IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY = 0x00000001,
10491  } IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY;
10492  
10493  /*
10494   * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID enum
10495   */
10496  
10497  typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID {
10498  IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID = 0x00000000,
10499  IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID = 0x00000001,
10500  } IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID;
10501  
10502  /*
10503   * RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL enum
10504   */
10505  
10506  typedef enum RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL {
10507  RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0x00000000,
10508  RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 0x00000001,
10509  } RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL;
10510  
10511  /*
10512   * RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL enum
10513   */
10514  
10515  typedef enum RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL {
10516  RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0x00000000,
10517  RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 0x00000001,
10518  } RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL;
10519  
10520  /*
10521   * STREAM_0_SYNCHRONIZATION enum
10522   */
10523  
10524  typedef enum STREAM_0_SYNCHRONIZATION {
10525  STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
10526  STREAM_0_SYNCHRONIZATION_STEAM_STOPPED   = 0x00000001,
10527  } STREAM_0_SYNCHRONIZATION;
10528  
10529  /*
10530   * STREAM_10_SYNCHRONIZATION enum
10531   */
10532  
10533  typedef enum STREAM_10_SYNCHRONIZATION {
10534  STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10535  STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10536  } STREAM_10_SYNCHRONIZATION;
10537  
10538  /*
10539   * STREAM_11_SYNCHRONIZATION enum
10540   */
10541  
10542  typedef enum STREAM_11_SYNCHRONIZATION {
10543  STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10544  STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10545  } STREAM_11_SYNCHRONIZATION;
10546  
10547  /*
10548   * STREAM_12_SYNCHRONIZATION enum
10549   */
10550  
10551  typedef enum STREAM_12_SYNCHRONIZATION {
10552  STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10553  STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10554  } STREAM_12_SYNCHRONIZATION;
10555  
10556  /*
10557   * STREAM_13_SYNCHRONIZATION enum
10558   */
10559  
10560  typedef enum STREAM_13_SYNCHRONIZATION {
10561  STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10562  STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10563  } STREAM_13_SYNCHRONIZATION;
10564  
10565  /*
10566   * STREAM_14_SYNCHRONIZATION enum
10567   */
10568  
10569  typedef enum STREAM_14_SYNCHRONIZATION {
10570  STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10571  STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10572  } STREAM_14_SYNCHRONIZATION;
10573  
10574  /*
10575   * STREAM_15_SYNCHRONIZATION enum
10576   */
10577  
10578  typedef enum STREAM_15_SYNCHRONIZATION {
10579  STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10580  STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10581  } STREAM_15_SYNCHRONIZATION;
10582  
10583  /*
10584   * STREAM_1_SYNCHRONIZATION enum
10585   */
10586  
10587  typedef enum STREAM_1_SYNCHRONIZATION {
10588  STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
10589  STREAM_1_SYNCHRONIZATION_STEAM_STOPPED   = 0x00000001,
10590  } STREAM_1_SYNCHRONIZATION;
10591  
10592  /*
10593   * STREAM_2_SYNCHRONIZATION enum
10594   */
10595  
10596  typedef enum STREAM_2_SYNCHRONIZATION {
10597  STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
10598  STREAM_2_SYNCHRONIZATION_STEAM_STOPPED   = 0x00000001,
10599  } STREAM_2_SYNCHRONIZATION;
10600  
10601  /*
10602   * STREAM_3_SYNCHRONIZATION enum
10603   */
10604  
10605  typedef enum STREAM_3_SYNCHRONIZATION {
10606  STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
10607  STREAM_3_SYNCHRONIZATION_STEAM_STOPPED   = 0x00000001,
10608  } STREAM_3_SYNCHRONIZATION;
10609  
10610  /*
10611   * STREAM_4_SYNCHRONIZATION enum
10612   */
10613  
10614  typedef enum STREAM_4_SYNCHRONIZATION {
10615  STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10616  STREAM_4_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10617  } STREAM_4_SYNCHRONIZATION;
10618  
10619  /*
10620   * STREAM_5_SYNCHRONIZATION enum
10621   */
10622  
10623  typedef enum STREAM_5_SYNCHRONIZATION {
10624  STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10625  STREAM_5_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10626  } STREAM_5_SYNCHRONIZATION;
10627  
10628  /*
10629   * STREAM_6_SYNCHRONIZATION enum
10630   */
10631  
10632  typedef enum STREAM_6_SYNCHRONIZATION {
10633  STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10634  STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10635  } STREAM_6_SYNCHRONIZATION;
10636  
10637  /*
10638   * STREAM_7_SYNCHRONIZATION enum
10639   */
10640  
10641  typedef enum STREAM_7_SYNCHRONIZATION {
10642  STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10643  STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10644  } STREAM_7_SYNCHRONIZATION;
10645  
10646  /*
10647   * STREAM_8_SYNCHRONIZATION enum
10648   */
10649  
10650  typedef enum STREAM_8_SYNCHRONIZATION {
10651  STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10652  STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10653  } STREAM_8_SYNCHRONIZATION;
10654  
10655  /*
10656   * STREAM_9_SYNCHRONIZATION enum
10657   */
10658  
10659  typedef enum STREAM_9_SYNCHRONIZATION {
10660  STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10661  STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10662  } STREAM_9_SYNCHRONIZATION;
10663  
10664  /*******************************************************
10665   * AZENDPOINT Enums
10666   *******************************************************/
10667  
10668  /*
10669   * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum
10670   */
10671  
10672  typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
10673  AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000,
10674  AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001,
10675  AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002,
10676  AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003,
10677  AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004,
10678  AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005,
10679  } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;
10680  
10681  /*
10682   * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum
10683   */
10684  
10685  typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
10686  AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000,
10687  AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001,
10688  AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002,
10689  AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003,
10690  AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004,
10691  AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005,
10692  AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006,
10693  AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007,
10694  AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 0x00000008,
10695  } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;
10696  
10697  /*
10698   * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum
10699   */
10700  
10701  typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
10702  AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000,
10703  AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001,
10704  AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002,
10705  AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003,
10706  AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004,
10707  AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005,
10708  AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006,
10709  AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007,
10710  } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;
10711  
10712  /*
10713   * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum
10714   */
10715  
10716  typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
10717  AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000,
10718  AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001,
10719  AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002,
10720  AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003,
10721  AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004,
10722  } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;
10723  
10724  /*
10725   * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum
10726   */
10727  
10728  typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
10729  AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000,
10730  AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001,
10731  } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;
10732  
10733  /*
10734   * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum
10735   */
10736  
10737  typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
10738  AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0x00000000,
10739  AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 0x00000001,
10740  } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;
10741  
10742  /*
10743   * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE enum
10744   */
10745  
10746  typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE {
10747  AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE = 0x00000000,
10748  AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE = 0x00000001,
10749  } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE;
10750  
10751  /*
10752   * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY enum
10753   */
10754  
10755  typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY {
10756  AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET = 0x00000000,
10757  AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET = 0x00000001,
10758  } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY;
10759  
10760  /*
10761   * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum
10762   */
10763  
10764  typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
10765  AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0x00000000,
10766  AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 0x00000001,
10767  } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;
10768  
10769  /*
10770   * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L enum
10771   */
10772  
10773  typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L {
10774  AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET = 0x00000000,
10775  AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET = 0x00000001,
10776  } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L;
10777  
10778  /*
10779   * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO enum
10780   */
10781  
10782  typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO {
10783  AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET = 0x00000000,
10784  AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET = 0x00000001,
10785  } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO;
10786  
10787  /*
10788   * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE enum
10789   */
10790  
10791  typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE {
10792  AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET = 0x00000000,
10793  AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET = 0x00000001,
10794  } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE;
10795  
10796  /*
10797   * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO enum
10798   */
10799  
10800  typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO {
10801  AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET = 0x00000000,
10802  AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET = 0x00000001,
10803  } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO;
10804  
10805  /*
10806   * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V enum
10807   */
10808  
10809  typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V {
10810  AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO = 0x00000000,
10811  AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE = 0x00000001,
10812  } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V;
10813  
10814  /*
10815   * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG enum
10816   */
10817  
10818  typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG {
10819  AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON = 0x00000000,
10820  AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON = 0x00000001,
10821  } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG;
10822  
10823  /*
10824   * AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE enum
10825   */
10826  
10827  typedef enum AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE {
10828  AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0 = 0x00000000,
10829  AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1 = 0x00000001,
10830  AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2 = 0x00000002,
10831  AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3 = 0x00000003,
10832  AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4 = 0x00000004,
10833  AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5 = 0x00000005,
10834  AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6 = 0x00000006,
10835  AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7 = 0x00000007,
10836  AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8 = 0x00000008,
10837  AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9 = 0x00000009,
10838  AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10 = 0x0000000a,
10839  AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11 = 0x0000000b,
10840  AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12 = 0x0000000c,
10841  AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13 = 0x0000000d,
10842  AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14 = 0x0000000e,
10843  AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15 = 0x0000000f,
10844  } AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE;
10845  
10846  /*
10847   * AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT enum
10848   */
10849  
10850  typedef enum AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT {
10851  AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED = 0x00000000,
10852  AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN = 0x00000001,
10853  } AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT;
10854  
10855  /*
10856   * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE enum
10857   */
10858  
10859  typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE {
10860  AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED = 0x00000000,
10861  AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED = 0x00000001,
10862  } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE;
10863  
10864  /*
10865   * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum
10866   */
10867  
10868  typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
10869  AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0x00000000,
10870  AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 0x00000001,
10871  } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;
10872  
10873  /*
10874   * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE enum
10875   */
10876  
10877  typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE {
10878  AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED = 0x00000000,
10879  AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED = 0x00000001,
10880  } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE;
10881  
10882  /*
10883   * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum
10884   */
10885  
10886  typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
10887  AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0x00000000,
10888  AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 0x00000001,
10889  } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;
10890  
10891  /*
10892   * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE enum
10893   */
10894  
10895  typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE {
10896  AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED = 0x00000000,
10897  AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED = 0x00000001,
10898  } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE;
10899  
10900  /*
10901   * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum
10902   */
10903  
10904  typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
10905  AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0x00000000,
10906  AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 0x00000001,
10907  } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;
10908  
10909  /*
10910   * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE enum
10911   */
10912  
10913  typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE {
10914  AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED = 0x00000000,
10915  AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED = 0x00000001,
10916  } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE;
10917  
10918  /*
10919   * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum
10920   */
10921  
10922  typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
10923  AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0x00000000,
10924  AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 0x00000001,
10925  } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;
10926  
10927  /*
10928   * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum
10929   */
10930  
10931  typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
10932  AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0x00000000,
10933  AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 0x00000001,
10934  } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;
10935  
10936  /*
10937   * AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum
10938   */
10939  
10940  typedef enum AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
10941  AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0x00000000,
10942  AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 0x00000001,
10943  } AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;
10944  
10945  /*
10946   * AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE enum
10947   */
10948  
10949  typedef enum AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE {
10950  AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF = 0x00000000,
10951  AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN = 0x00000001,
10952  } AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE;
10953  
10954  /*******************************************************
10955   * AZF0CONTROLLER Enums
10956   *******************************************************/
10957  
10958  /*
10959   * AZALIA_SOFT_RESET_REFCLK_SOFT_RESET enum
10960   */
10961  
10962  typedef enum AZALIA_SOFT_RESET_REFCLK_SOFT_RESET {
10963  AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET = 0x00000000,
10964  AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC = 0x00000001,
10965  } AZALIA_SOFT_RESET_REFCLK_SOFT_RESET;
10966  
10967  /*
10968   * MEM_PWR_DIS_CTRL enum
10969   */
10970  
10971  typedef enum MEM_PWR_DIS_CTRL {
10972  ENABLE_MEM_PWR_CTRL                      = 0x00000000,
10973  DISABLE_MEM_PWR_CTRL                     = 0x00000001,
10974  } MEM_PWR_DIS_CTRL;
10975  
10976  /*
10977   * MEM_PWR_FORCE_CTRL enum
10978   */
10979  
10980  typedef enum MEM_PWR_FORCE_CTRL {
10981  NO_FORCE_REQUEST                         = 0x00000000,
10982  FORCE_LIGHT_SLEEP_REQUEST                = 0x00000001,
10983  FORCE_DEEP_SLEEP_REQUEST                 = 0x00000002,
10984  FORCE_SHUT_DOWN_REQUEST                  = 0x00000003,
10985  } MEM_PWR_FORCE_CTRL;
10986  
10987  /*
10988   * MEM_PWR_FORCE_CTRL2 enum
10989   */
10990  
10991  typedef enum MEM_PWR_FORCE_CTRL2 {
10992  NO_FORCE_REQ                             = 0x00000000,
10993  FORCE_LIGHT_SLEEP_REQ                    = 0x00000001,
10994  } MEM_PWR_FORCE_CTRL2;
10995  
10996  /*
10997   * MEM_PWR_SEL_CTRL enum
10998   */
10999  
11000  typedef enum MEM_PWR_SEL_CTRL {
11001  DYNAMIC_SHUT_DOWN_ENABLE                 = 0x00000000,
11002  DYNAMIC_DEEP_SLEEP_ENABLE                = 0x00000001,
11003  DYNAMIC_LIGHT_SLEEP_ENABLE               = 0x00000002,
11004  } MEM_PWR_SEL_CTRL;
11005  
11006  /*
11007   * MEM_PWR_SEL_CTRL2 enum
11008   */
11009  
11010  typedef enum MEM_PWR_SEL_CTRL2 {
11011  DYNAMIC_DEEP_SLEEP_EN                    = 0x00000000,
11012  DYNAMIC_LIGHT_SLEEP_EN                   = 0x00000001,
11013  } MEM_PWR_SEL_CTRL2;
11014  
11015  /*******************************************************
11016   * AZF0ROOT Enums
11017   *******************************************************/
11018  
11019  /*
11020   * CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY enum
11021   */
11022  
11023  typedef enum CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY {
11024  CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL = 0x00000000,
11025  CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6 = 0x00000001,
11026  CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5 = 0x00000002,
11027  CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4 = 0x00000003,
11028  CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3 = 0x00000004,
11029  CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2 = 0x00000005,
11030  CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1 = 0x00000006,
11031  CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0 = 0x00000007,
11032  } CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY;
11033  
11034  /*
11035   * CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY enum
11036   */
11037  
11038  typedef enum CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY {
11039  CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL = 0x00000000,
11040  CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6 = 0x00000001,
11041  CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5 = 0x00000002,
11042  CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4 = 0x00000003,
11043  CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3 = 0x00000004,
11044  CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2 = 0x00000005,
11045  CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1 = 0x00000006,
11046  CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0 = 0x00000007,
11047  } CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY;
11048  
11049  /*******************************************************
11050   * AZINPUTENDPOINT Enums
11051   *******************************************************/
11052  
11053  /*
11054   * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum
11055   */
11056  
11057  typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
11058  AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000,
11059  AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001,
11060  AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002,
11061  AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003,
11062  AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004,
11063  AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005,
11064  } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;
11065  
11066  /*
11067   * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum
11068   */
11069  
11070  typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
11071  AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000,
11072  AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001,
11073  AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002,
11074  AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003,
11075  AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004,
11076  AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005,
11077  AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006,
11078  AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007,
11079  AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 0x00000008,
11080  } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;
11081  
11082  /*
11083   * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum
11084   */
11085  
11086  typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
11087  AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000,
11088  AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001,
11089  AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002,
11090  AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003,
11091  AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004,
11092  AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005,
11093  AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006,
11094  AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007,
11095  } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;
11096  
11097  /*
11098   * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum
11099   */
11100  
11101  typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
11102  AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000,
11103  AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001,
11104  AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002,
11105  AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003,
11106  AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004,
11107  } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;
11108  
11109  /*
11110   * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum
11111   */
11112  
11113  typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
11114  AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000,
11115  AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001,
11116  } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;
11117  
11118  /*
11119   * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum
11120   */
11121  
11122  typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
11123  AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0x00000000,
11124  AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 0x00000001,
11125  } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;
11126  
11127  /*
11128   * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum
11129   */
11130  
11131  typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
11132  AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0x00000000,
11133  AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 0x00000001,
11134  } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;
11135  
11136  /*
11137   * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE enum
11138   */
11139  
11140  typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE {
11141  AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED = 0x00000000,
11142  AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED = 0x00000001,
11143  } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE;
11144  
11145  /*
11146   * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum
11147   */
11148  
11149  typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
11150  AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0x00000000,
11151  AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 0x00000001,
11152  } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;
11153  
11154  /*
11155   * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE enum
11156   */
11157  
11158  typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE {
11159  AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED = 0x00000000,
11160  AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED = 0x00000001,
11161  } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE;
11162  
11163  /*
11164   * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum
11165   */
11166  
11167  typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
11168  AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0x00000000,
11169  AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 0x00000001,
11170  } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;
11171  
11172  /*
11173   * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE enum
11174   */
11175  
11176  typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE {
11177  AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED = 0x00000000,
11178  AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED = 0x00000001,
11179  } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE;
11180  
11181  /*
11182   * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum
11183   */
11184  
11185  typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
11186  AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0x00000000,
11187  AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 0x00000001,
11188  } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;
11189  
11190  /*
11191   * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE enum
11192   */
11193  
11194  typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE {
11195  AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED = 0x00000000,
11196  AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED = 0x00000001,
11197  } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE;
11198  
11199  /*
11200   * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum
11201   */
11202  
11203  typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
11204  AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0x00000000,
11205  AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 0x00000001,
11206  } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;
11207  
11208  /*
11209   * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum
11210   */
11211  
11212  typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
11213  AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0x00000000,
11214  AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 0x00000001,
11215  } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;
11216  
11217  /*
11218   * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE enum
11219   */
11220  
11221  typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE {
11222  AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF = 0x00000000,
11223  AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN = 0x00000001,
11224  } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE;
11225  
11226  /*******************************************************
11227   * AZROOT Enums
11228   *******************************************************/
11229  
11230  /*
11231   * AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET enum
11232   */
11233  
11234  typedef enum AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET {
11235  AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET = 0x00000000,
11236  AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET = 0x00000001,
11237  } AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET;
11238  
11239  /*******************************************************
11240   * AZF0STREAM Enums
11241   *******************************************************/
11242  
11243  /*
11244   * AZ_LATENCY_COUNTER_CONTROL enum
11245   */
11246  
11247  typedef enum AZ_LATENCY_COUNTER_CONTROL {
11248  AZ_LATENCY_COUNTER_NO_RESET              = 0x00000000,
11249  AZ_LATENCY_COUNTER_RESET_DONE            = 0x00000001,
11250  } AZ_LATENCY_COUNTER_CONTROL;
11251  
11252  /*******************************************************
11253   * AZSTREAM Enums
11254   *******************************************************/
11255  
11256  /*
11257   * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS enum
11258   */
11259  
11260  typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS {
11261  OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET = 0x00000000,
11262  OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET = 0x00000001,
11263  } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS;
11264  
11265  /*
11266   * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR enum
11267   */
11268  
11269  typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR {
11270  OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET = 0x00000000,
11271  OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET = 0x00000001,
11272  } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR;
11273  
11274  /*
11275   * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE enum
11276   */
11277  
11278  typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE {
11279  OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED = 0x00000000,
11280  OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED = 0x00000001,
11281  } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE;
11282  
11283  /*
11284   * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR enum
11285   */
11286  
11287  typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR {
11288  OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET = 0x00000000,
11289  OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET = 0x00000001,
11290  } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR;
11291  
11292  /*
11293   * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE enum
11294   */
11295  
11296  typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE {
11297  OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED = 0x00000000,
11298  OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED = 0x00000001,
11299  } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE;
11300  
11301  /*
11302   * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE enum
11303   */
11304  
11305  typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE {
11306  OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED = 0x00000000,
11307  OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED = 0x00000001,
11308  } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE;
11309  
11310  /*
11311   * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET enum
11312   */
11313  
11314  typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET {
11315  OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET = 0x00000000,
11316  OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET = 0x00000001,
11317  } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET;
11318  
11319  /*
11320   * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN enum
11321   */
11322  
11323  typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN {
11324  OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN = 0x00000000,
11325  OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN = 0x00000001,
11326  } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN;
11327  
11328  /*
11329   * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY enum
11330   */
11331  
11332  typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY {
11333  OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY = 0x00000000,
11334  OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY = 0x00000001,
11335  } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY;
11336  
11337  /*
11338   * OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE enum
11339   */
11340  
11341  typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE {
11342  OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000,
11343  OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001,
11344  OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002,
11345  OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003,
11346  OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004,
11347  OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005,
11348  } OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE;
11349  
11350  /*
11351   * OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS enum
11352   */
11353  
11354  typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS {
11355  OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000,
11356  OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001,
11357  OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002,
11358  OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003,
11359  OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004,
11360  OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005,
11361  OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006,
11362  OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007,
11363  OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED = 0x00000008,
11364  OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED = 0x00000009,
11365  OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED = 0x0000000a,
11366  OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED = 0x0000000b,
11367  OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED = 0x0000000c,
11368  OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED = 0x0000000d,
11369  OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED = 0x0000000e,
11370  OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED = 0x0000000f,
11371  } OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS;
11372  
11373  /*
11374   * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR enum
11375   */
11376  
11377  typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR {
11378  OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000,
11379  OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001,
11380  OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002,
11381  OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003,
11382  OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004,
11383  OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005,
11384  OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006,
11385  OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007,
11386  } OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR;
11387  
11388  /*
11389   * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE enum
11390   */
11391  
11392  typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE {
11393  OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000,
11394  OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001,
11395  OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002,
11396  OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003,
11397  OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004,
11398  } OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE;
11399  
11400  /*
11401   * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE enum
11402   */
11403  
11404  typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE {
11405  OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000,
11406  OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001,
11407  } OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE;
11408  
11409  /*******************************************************
11410   * AZF0ENDPOINT Enums
11411   *******************************************************/
11412  
11413  /*
11414   * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
11415   */
11416  
11417  typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
11418  AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000,
11419  AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 0x00000001,
11420  } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
11421  
11422  /*
11423   * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum
11424   */
11425  
11426  typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
11427  AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0x00000000,
11428  AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 0x00000001,
11429  } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;
11430  
11431  /*
11432   * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
11433   */
11434  
11435  typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
11436  AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000,
11437  AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001,
11438  } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
11439  
11440  /*
11441   * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
11442   */
11443  
11444  typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
11445  AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0x00000000,
11446  AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 0x00000001,
11447  } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
11448  
11449  /*
11450   * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum
11451   */
11452  
11453  typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
11454  AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0x00000000,
11455  AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE = 0x00000001,
11456  } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;
11457  
11458  /*
11459   * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
11460   */
11461  
11462  typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
11463  AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0x00000000,
11464  AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001,
11465  } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
11466  
11467  /*
11468   * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
11469   */
11470  
11471  typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
11472  AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0x00000000,
11473  AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 0x00000001,
11474  } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
11475  
11476  /*
11477   * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
11478   */
11479  
11480  typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
11481  AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000,
11482  AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001,
11483  } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
11484  
11485  /*
11486   * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
11487   */
11488  
11489  typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
11490  AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000,
11491  AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001,
11492  } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
11493  
11494  /*
11495   * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
11496   */
11497  
11498  typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
11499  AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0x00000000,
11500  AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 0x00000001,
11501  } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
11502  
11503  /*
11504   * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
11505   */
11506  
11507  typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
11508  AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0x00000000,
11509  AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001,
11510  } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
11511  
11512  /*
11513   * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
11514   */
11515  
11516  typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
11517  AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000,
11518  AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001,
11519  AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002,
11520  AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003,
11521  AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004,
11522  AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005,
11523  AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006,
11524  AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007,
11525  AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 0x00000008,
11526  AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009,
11527  } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
11528  
11529  /*
11530   * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
11531   */
11532  
11533  typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
11534  AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000,
11535  AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001,
11536  } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
11537  
11538  /*
11539   * AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum
11540   */
11541  
11542  typedef enum AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
11543  AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0x00000000,
11544  AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 0x00000001,
11545  } AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;
11546  
11547  /*
11548   * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum
11549   */
11550  
11551  typedef enum AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
11552  AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY = 0x00000000,
11553  AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY = 0x00000001,
11554  } AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;
11555  
11556  /*
11557   * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
11558   */
11559  
11560  typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
11561  AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000,
11562  AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 0x00000001,
11563  } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
11564  
11565  /*
11566   * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
11567   */
11568  
11569  typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
11570  AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000,
11571  AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001,
11572  } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
11573  
11574  /*
11575   * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
11576   */
11577  
11578  typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
11579  AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0x00000000,
11580  AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 0x00000001,
11581  } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
11582  
11583  /*
11584   * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
11585   */
11586  
11587  typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
11588  AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT = 0x00000000,
11589  AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001,
11590  } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
11591  
11592  /*
11593   * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
11594   */
11595  
11596  typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
11597  AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0x00000000,
11598  AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 0x00000001,
11599  } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
11600  
11601  /*
11602   * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
11603   */
11604  
11605  typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
11606  AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000,
11607  AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001,
11608  } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
11609  
11610  /*
11611   * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
11612   */
11613  
11614  typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
11615  AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000,
11616  AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001,
11617  } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
11618  
11619  /*
11620   * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
11621   */
11622  
11623  typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
11624  AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0x00000000,
11625  AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 0x00000001,
11626  } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
11627  
11628  /*
11629   * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
11630   */
11631  
11632  typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
11633  AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0x00000000,
11634  AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001,
11635  } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
11636  
11637  /*
11638   * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
11639   */
11640  
11641  typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
11642  AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000,
11643  AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001,
11644  AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002,
11645  AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003,
11646  AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004,
11647  AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005,
11648  AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006,
11649  AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007,
11650  AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 0x00000008,
11651  AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009,
11652  } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
11653  
11654  /*
11655   * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
11656   */
11657  
11658  typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
11659  AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000,
11660  AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001,
11661  } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
11662  
11663  /*
11664   * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum
11665   */
11666  
11667  typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
11668  AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED = 0x00000000,
11669  AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 0x00000001,
11670  } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;
11671  
11672  /*
11673   * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum
11674   */
11675  
11676  typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
11677  AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN = 0x00000000,
11678  AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN = 0x00000001,
11679  } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;
11680  
11681  /*
11682   * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum
11683   */
11684  
11685  typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
11686  AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0x00000000,
11687  AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 0x00000001,
11688  } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;
11689  
11690  /*
11691   * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum
11692   */
11693  
11694  typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
11695  AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0x00000000,
11696  AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 0x00000001,
11697  } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;
11698  
11699  /*
11700   * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum
11701   */
11702  
11703  typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
11704  AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0x00000000,
11705  AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 0x00000001,
11706  } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;
11707  
11708  /*
11709   * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum
11710   */
11711  
11712  typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
11713  AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY = 0x00000000,
11714  AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY = 0x00000001,
11715  } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;
11716  
11717  /*
11718   * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum
11719   */
11720  
11721  typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
11722  AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0x00000000,
11723  AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 0x00000001,
11724  } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;
11725  
11726  /*
11727   * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum
11728   */
11729  
11730  typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
11731  AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000000,
11732  AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000001,
11733  } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;
11734  
11735  /*******************************************************
11736   * AZF0INPUTENDPOINT Enums
11737   *******************************************************/
11738  
11739  /*
11740   * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
11741   */
11742  
11743  typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
11744  AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000,
11745  AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER = 0x00000001,
11746  } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
11747  
11748  /*
11749   * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum
11750   */
11751  
11752  typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
11753  AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0x00000000,
11754  AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 0x00000001,
11755  } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;
11756  
11757  /*
11758   * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
11759   */
11760  
11761  typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
11762  AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000,
11763  AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001,
11764  } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
11765  
11766  /*
11767   * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
11768   */
11769  
11770  typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
11771  AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG = 0x00000000,
11772  AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL = 0x00000001,
11773  } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
11774  
11775  /*
11776   * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum
11777   */
11778  
11779  typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
11780  AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0x00000000,
11781  AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE = 0x00000001,
11782  } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;
11783  
11784  /*
11785   * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
11786   */
11787  
11788  typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
11789  AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0x00000000,
11790  AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001,
11791  } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
11792  
11793  /*
11794   * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
11795   */
11796  
11797  typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
11798  AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0x00000000,
11799  AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 0x00000001,
11800  } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
11801  
11802  /*
11803   * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
11804   */
11805  
11806  typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
11807  AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000,
11808  AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001,
11809  } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
11810  
11811  /*
11812   * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
11813   */
11814  
11815  typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
11816  AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000,
11817  AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001,
11818  } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
11819  
11820  /*
11821   * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
11822   */
11823  
11824  typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
11825  AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES = 0x00000000,
11826  AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES = 0x00000001,
11827  } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
11828  
11829  /*
11830   * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
11831   */
11832  
11833  typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
11834  AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING = 0x00000000,
11835  AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001,
11836  } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
11837  
11838  /*
11839   * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
11840   */
11841  
11842  typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
11843  AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000,
11844  AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001,
11845  AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002,
11846  AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003,
11847  AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004,
11848  AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005,
11849  AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006,
11850  AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007,
11851  AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 0x00000008,
11852  AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009,
11853  } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
11854  
11855  /*
11856   * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
11857   */
11858  
11859  typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
11860  AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000,
11861  AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001,
11862  } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
11863  
11864  /*
11865   * AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum
11866   */
11867  
11868  typedef enum AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
11869  AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY = 0x00000000,
11870  AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY = 0x00000001,
11871  } AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;
11872  
11873  /*
11874   * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
11875   */
11876  
11877  typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
11878  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000,
11879  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 0x00000001,
11880  } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
11881  
11882  /*
11883   * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
11884   */
11885  
11886  typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
11887  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000,
11888  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001,
11889  } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
11890  
11891  /*
11892   * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
11893   */
11894  
11895  typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
11896  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0x00000000,
11897  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 0x00000001,
11898  } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
11899  
11900  /*
11901   * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
11902   */
11903  
11904  typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
11905  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0x00000000,
11906  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001,
11907  } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
11908  
11909  /*
11910   * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
11911   */
11912  
11913  typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
11914  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP = 0x00000000,
11915  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP = 0x00000001,
11916  } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
11917  
11918  /*
11919   * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
11920   */
11921  
11922  typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
11923  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000,
11924  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001,
11925  } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
11926  
11927  /*
11928   * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
11929   */
11930  
11931  typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
11932  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000,
11933  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001,
11934  } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
11935  
11936  /*
11937   * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
11938   */
11939  
11940  typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
11941  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES = 0x00000000,
11942  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES = 0x00000001,
11943  } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
11944  
11945  /*
11946   * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
11947   */
11948  
11949  typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
11950  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0x00000000,
11951  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001,
11952  } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
11953  
11954  /*
11955   * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
11956   */
11957  
11958  typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
11959  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000,
11960  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001,
11961  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002,
11962  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003,
11963  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004,
11964  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005,
11965  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006,
11966  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007,
11967  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 0x00000008,
11968  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009,
11969  } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
11970  
11971  /*
11972   * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
11973   */
11974  
11975  typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
11976  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000,
11977  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001,
11978  } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
11979  
11980  /*
11981   * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum
11982   */
11983  
11984  typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
11985  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED = 0x00000000,
11986  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 0x00000001,
11987  } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;
11988  
11989  /*
11990   * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP enum
11991   */
11992  
11993  typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP {
11994  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED = 0x00000000,
11995  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED = 0x00000001,
11996  } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP;
11997  
11998  /*
11999   * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum
12000   */
12001  
12002  typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
12003  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN = 0x00000000,
12004  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN = 0x00000001,
12005  } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;
12006  
12007  /*
12008   * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI enum
12009   */
12010  
12011  typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI {
12012  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED = 0x00000000,
12013  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED = 0x00000001,
12014  } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI;
12015  
12016  /*
12017   * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum
12018   */
12019  
12020  typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
12021  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0x00000000,
12022  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 0x00000001,
12023  } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;
12024  
12025  /*
12026   * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum
12027   */
12028  
12029  typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
12030  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0x00000000,
12031  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 0x00000001,
12032  } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;
12033  
12034  /*
12035   * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum
12036   */
12037  
12038  typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
12039  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0x00000000,
12040  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 0x00000001,
12041  } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;
12042  
12043  /*
12044   * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum
12045   */
12046  
12047  typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
12048  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY = 0x00000000,
12049  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY = 0x00000001,
12050  } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;
12051  
12052  /*
12053   * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum
12054   */
12055  
12056  typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
12057  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0x00000000,
12058  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 0x00000001,
12059  } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;
12060  
12061  /*
12062   * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum
12063   */
12064  
12065  typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
12066  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000000,
12067  AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000001,
12068  } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;
12069  
12070  /*******************************************************
12071   * DSCC Enums
12072   *******************************************************/
12073  
12074  /*
12075   * DSCC_BITS_PER_COMPONENT_ENUM enum
12076   */
12077  
12078  typedef enum DSCC_BITS_PER_COMPONENT_ENUM {
12079  DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 0x00000008,
12080  DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 0x0000000a,
12081  DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 0x0000000c,
12082  } DSCC_BITS_PER_COMPONENT_ENUM;
12083  
12084  /*
12085   * DSCC_DSC_VERSION_MAJOR_ENUM enum
12086   */
12087  
12088  typedef enum DSCC_DSC_VERSION_MAJOR_ENUM {
12089  DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION = 0x00000001,
12090  } DSCC_DSC_VERSION_MAJOR_ENUM;
12091  
12092  /*
12093   * DSCC_DSC_VERSION_MINOR_ENUM enum
12094   */
12095  
12096  typedef enum DSCC_DSC_VERSION_MINOR_ENUM {
12097  DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION = 0x00000001,
12098  DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION = 0x00000002,
12099  } DSCC_DSC_VERSION_MINOR_ENUM;
12100  
12101  /*
12102   * DSCC_ENABLE_ENUM enum
12103   */
12104  
12105  typedef enum DSCC_ENABLE_ENUM {
12106  DSCC_ENABLE_ENUM_DISABLED                = 0x00000000,
12107  DSCC_ENABLE_ENUM_ENABLED                 = 0x00000001,
12108  } DSCC_ENABLE_ENUM;
12109  
12110  /*
12111   * DSCC_ICH_RESET_ENUM enum
12112   */
12113  
12114  typedef enum DSCC_ICH_RESET_ENUM {
12115  DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET     = 0x00000001,
12116  DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET     = 0x00000002,
12117  DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET     = 0x00000004,
12118  DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET     = 0x00000008,
12119  } DSCC_ICH_RESET_ENUM;
12120  
12121  /*
12122   * DSCC_LINEBUF_DEPTH_ENUM enum
12123   */
12124  
12125  typedef enum DSCC_LINEBUF_DEPTH_ENUM {
12126  DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT = 0x00000008,
12127  DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT = 0x00000009,
12128  DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT = 0x0000000a,
12129  DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT = 0x0000000b,
12130  DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT = 0x0000000c,
12131  DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT = 0x0000000d,
12132  } DSCC_LINEBUF_DEPTH_ENUM;
12133  
12134  /*
12135   * DSCC_MEM_PWR_DIS_ENUM enum
12136   */
12137  
12138  typedef enum DSCC_MEM_PWR_DIS_ENUM {
12139  DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN         = 0x00000000,
12140  DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS        = 0x00000001,
12141  } DSCC_MEM_PWR_DIS_ENUM;
12142  
12143  /*
12144   * DSCC_MEM_PWR_FORCE_ENUM enum
12145   */
12146  
12147  typedef enum DSCC_MEM_PWR_FORCE_ENUM {
12148  DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST = 0x00000000,
12149  DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
12150  DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
12151  DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST = 0x00000003,
12152  } DSCC_MEM_PWR_FORCE_ENUM;
12153  
12154  /*
12155   * POWER_STATE_ENUM enum
12156   */
12157  
12158  typedef enum POWER_STATE_ENUM {
12159  POWER_STATE_ENUM_ON                      = 0x00000000,
12160  POWER_STATE_ENUM_LS                      = 0x00000001,
12161  POWER_STATE_ENUM_DS                      = 0x00000002,
12162  POWER_STATE_ENUM_SD                      = 0x00000003,
12163  } POWER_STATE_ENUM;
12164  
12165  /*******************************************************
12166   * DSCCIF Enums
12167   *******************************************************/
12168  
12169  /*
12170   * DSCCIF_BITS_PER_COMPONENT_ENUM enum
12171   */
12172  
12173  typedef enum DSCCIF_BITS_PER_COMPONENT_ENUM {
12174  DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 0x00000008,
12175  DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 0x0000000a,
12176  DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 0x0000000c,
12177  } DSCCIF_BITS_PER_COMPONENT_ENUM;
12178  
12179  /*
12180   * DSCCIF_ENABLE_ENUM enum
12181   */
12182  
12183  typedef enum DSCCIF_ENABLE_ENUM {
12184  DSCCIF_ENABLE_ENUM_DISABLED              = 0x00000000,
12185  DSCCIF_ENABLE_ENUM_ENABLED               = 0x00000001,
12186  } DSCCIF_ENABLE_ENUM;
12187  
12188  /*
12189   * DSCCIF_INPUT_PIXEL_FORMAT_ENUM enum
12190   */
12191  
12192  typedef enum DSCCIF_INPUT_PIXEL_FORMAT_ENUM {
12193  DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB       = 0x00000000,
12194  DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444 = 0x00000001,
12195  DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422 = 0x00000002,
12196  DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422 = 0x00000003,
12197  DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420 = 0x00000004,
12198  } DSCCIF_INPUT_PIXEL_FORMAT_ENUM;
12199  
12200  /*******************************************************
12201   * DSC_TOP Enums
12202   *******************************************************/
12203  
12204  /*
12205   * CLOCK_GATING_DISABLE_ENUM enum
12206   */
12207  
12208  typedef enum CLOCK_GATING_DISABLE_ENUM {
12209  CLOCK_GATING_DISABLE_ENUM_ENABLED        = 0x00000000,
12210  CLOCK_GATING_DISABLE_ENUM_DISABLED       = 0x00000001,
12211  } CLOCK_GATING_DISABLE_ENUM;
12212  
12213  /*
12214   * ENABLE_ENUM enum
12215   */
12216  
12217  typedef enum ENABLE_ENUM {
12218  ENABLE_ENUM_DISABLED                     = 0x00000000,
12219  ENABLE_ENUM_ENABLED                      = 0x00000001,
12220  } ENABLE_ENUM;
12221  
12222  /*
12223   * TEST_CLOCK_MUX_SELECT_ENUM enum
12224   */
12225  
12226  typedef enum TEST_CLOCK_MUX_SELECT_ENUM {
12227  TEST_CLOCK_MUX_SELECT_DISPCLK_P          = 0x00000000,
12228  TEST_CLOCK_MUX_SELECT_DISPCLK_G          = 0x00000001,
12229  TEST_CLOCK_MUX_SELECT_DISPCLK_R          = 0x00000002,
12230  TEST_CLOCK_MUX_SELECT_DSCCLK_P           = 0x00000003,
12231  TEST_CLOCK_MUX_SELECT_DSCCLK_G           = 0x00000004,
12232  TEST_CLOCK_MUX_SELECT_DSCCLK_R           = 0x00000005,
12233  } TEST_CLOCK_MUX_SELECT_ENUM;
12234  
12235  /*******************************************************
12236   * DWB_TOP Enums
12237   *******************************************************/
12238  
12239  /*
12240   * DWB_CRC_CONT_EN_ENUM enum
12241   */
12242  
12243  typedef enum DWB_CRC_CONT_EN_ENUM {
12244  DWB_CRC_CONT_EN_ONE_SHOT                 = 0x00000000,
12245  DWB_CRC_CONT_EN_CONT                     = 0x00000001,
12246  } DWB_CRC_CONT_EN_ENUM;
12247  
12248  /*
12249   * DWB_CRC_SRC_SEL_ENUM enum
12250   */
12251  
12252  typedef enum DWB_CRC_SRC_SEL_ENUM {
12253  DWB_CRC_SRC_SEL_DWB_IN                   = 0x00000000,
12254  DWB_CRC_SRC_SEL_OGAM_OUT                 = 0x00000001,
12255  DWB_CRC_SRC_SEL_DWB_OUT                  = 0x00000002,
12256  } DWB_CRC_SRC_SEL_ENUM;
12257  
12258  /*
12259   * DWB_DATA_OVERFLOW_INT_TYPE_ENUM enum
12260   */
12261  
12262  typedef enum DWB_DATA_OVERFLOW_INT_TYPE_ENUM {
12263  DWB_DATA_OVERFLOW_INT_TYPE_0             = 0x00000000,
12264  DWB_DATA_OVERFLOW_INT_TYPE_1             = 0x00000001,
12265  } DWB_DATA_OVERFLOW_INT_TYPE_ENUM;
12266  
12267  /*
12268   * DWB_DATA_OVERFLOW_TYPE_ENUM enum
12269   */
12270  
12271  typedef enum DWB_DATA_OVERFLOW_TYPE_ENUM {
12272  DWB_DATA_OVERFLOW_TYPE_NO_OVERFLOW       = 0x00000000,
12273  DWB_DATA_OVERFLOW_TYPE_BUFFER            = 0x00000001,
12274  DWB_DATA_OVERFLOW_TYPE_VUPDATE           = 0x00000002,
12275  DWB_DATA_OVERFLOW_TYPE_VREADY            = 0x00000003,
12276  } DWB_DATA_OVERFLOW_TYPE_ENUM;
12277  
12278  /*
12279   * DWB_DEBUG_SEL_ENUM enum
12280   */
12281  
12282  typedef enum DWB_DEBUG_SEL_ENUM {
12283  DWB_DEBUG_SEL_FC                         = 0x00000000,
12284  DWB_DEBUG_SEL_RESERVED                   = 0x00000001,
12285  DWB_DEBUG_SEL_DWBCP                      = 0x00000002,
12286  DWB_DEBUG_SEL_PERFMON                    = 0x00000003,
12287  } DWB_DEBUG_SEL_ENUM;
12288  
12289  /*
12290   * DWB_MEM_PWR_FORCE_ENUM enum
12291   */
12292  
12293  typedef enum DWB_MEM_PWR_FORCE_ENUM {
12294  DWB_MEM_PWR_FORCE_DIS                    = 0x00000000,
12295  DWB_MEM_PWR_FORCE_LS                     = 0x00000001,
12296  DWB_MEM_PWR_FORCE_DS                     = 0x00000002,
12297  DWB_MEM_PWR_FORCE_SD                     = 0x00000003,
12298  } DWB_MEM_PWR_FORCE_ENUM;
12299  
12300  /*
12301   * DWB_MEM_PWR_STATE_ENUM enum
12302   */
12303  
12304  typedef enum DWB_MEM_PWR_STATE_ENUM {
12305  DWB_MEM_PWR_STATE_ON                     = 0x00000000,
12306  DWB_MEM_PWR_STATE_LS                     = 0x00000001,
12307  DWB_MEM_PWR_STATE_DS                     = 0x00000002,
12308  DWB_MEM_PWR_STATE_SD                     = 0x00000003,
12309  } DWB_MEM_PWR_STATE_ENUM;
12310  
12311  /*
12312   * DWB_TEST_CLK_SEL_ENUM enum
12313   */
12314  
12315  typedef enum DWB_TEST_CLK_SEL_ENUM {
12316  DWB_TEST_CLK_SEL_R                       = 0x00000000,
12317  DWB_TEST_CLK_SEL_G                       = 0x00000001,
12318  DWB_TEST_CLK_SEL_P                       = 0x00000002,
12319  } DWB_TEST_CLK_SEL_ENUM;
12320  
12321  /*
12322   * FC_EYE_SELECTION_ENUM enum
12323   */
12324  
12325  typedef enum FC_EYE_SELECTION_ENUM {
12326  FC_EYE_SELECTION_STEREO_DIS              = 0x00000000,
12327  FC_EYE_SELECTION_LEFT_EYE                = 0x00000001,
12328  FC_EYE_SELECTION_RIGHT_EYE               = 0x00000002,
12329  } FC_EYE_SELECTION_ENUM;
12330  
12331  /*
12332   * FC_FRAME_CAPTURE_RATE_ENUM enum
12333   */
12334  
12335  typedef enum FC_FRAME_CAPTURE_RATE_ENUM {
12336  FC_FRAME_CAPTURE_RATE_FULL               = 0x00000000,
12337  FC_FRAME_CAPTURE_RATE_HALF               = 0x00000001,
12338  FC_FRAME_CAPTURE_RATE_THIRD              = 0x00000002,
12339  FC_FRAME_CAPTURE_RATE_QUARTER            = 0x00000003,
12340  } FC_FRAME_CAPTURE_RATE_ENUM;
12341  
12342  /*
12343   * FC_STEREO_EYE_POLARITY_ENUM enum
12344   */
12345  
12346  typedef enum FC_STEREO_EYE_POLARITY_ENUM {
12347  FC_STEREO_EYE_POLARITY_LEFT              = 0x00000000,
12348  FC_STEREO_EYE_POLARITY_RIGHT             = 0x00000001,
12349  } FC_STEREO_EYE_POLARITY_ENUM;
12350  
12351  /*******************************************************
12352   * DWBCP Enums
12353   *******************************************************/
12354  
12355  /*
12356   * DWB_GAMUT_REMAP_COEF_FORMAT_ENUM enum
12357   */
12358  
12359  typedef enum DWB_GAMUT_REMAP_COEF_FORMAT_ENUM {
12360  DWB_GAMUT_REMAP_COEF_FORMAT_S2_13        = 0x00000000,
12361  DWB_GAMUT_REMAP_COEF_FORMAT_S3_12        = 0x00000001,
12362  } DWB_GAMUT_REMAP_COEF_FORMAT_ENUM;
12363  
12364  /*
12365   * DWB_GAMUT_REMAP_MODE_ENUM enum
12366   */
12367  
12368  typedef enum DWB_GAMUT_REMAP_MODE_ENUM {
12369  DWB_GAMUT_REMAP_MODE_BYPASS              = 0x00000000,
12370  DWB_GAMUT_REMAP_MODE_COEF_A              = 0x00000001,
12371  DWB_GAMUT_REMAP_MODE_COEF_B              = 0x00000002,
12372  DWB_GAMUT_REMAP_MODE_RESERVED            = 0x00000003,
12373  } DWB_GAMUT_REMAP_MODE_ENUM;
12374  
12375  /*
12376   * DWB_LUT_NUM_SEG enum
12377   */
12378  
12379  typedef enum DWB_LUT_NUM_SEG {
12380  DWB_SEGMENTS_1                           = 0x00000000,
12381  DWB_SEGMENTS_2                           = 0x00000001,
12382  DWB_SEGMENTS_4                           = 0x00000002,
12383  DWB_SEGMENTS_8                           = 0x00000003,
12384  DWB_SEGMENTS_16                          = 0x00000004,
12385  DWB_SEGMENTS_32                          = 0x00000005,
12386  DWB_SEGMENTS_64                          = 0x00000006,
12387  DWB_SEGMENTS_128                         = 0x00000007,
12388  } DWB_LUT_NUM_SEG;
12389  
12390  /*
12391   * DWB_OGAM_LUT_CONFIG_MODE_ENUM enum
12392   */
12393  
12394  typedef enum DWB_OGAM_LUT_CONFIG_MODE_ENUM {
12395  DWB_OGAM_LUT_CONFIG_MODE_DIFF            = 0x00000000,
12396  DWB_OGAM_LUT_CONFIG_MODE_SAME            = 0x00000001,
12397  } DWB_OGAM_LUT_CONFIG_MODE_ENUM;
12398  
12399  /*
12400   * DWB_OGAM_LUT_HOST_SEL_ENUM enum
12401   */
12402  
12403  typedef enum DWB_OGAM_LUT_HOST_SEL_ENUM {
12404  DWB_OGAM_LUT_HOST_SEL_RAMA               = 0x00000000,
12405  DWB_OGAM_LUT_HOST_SEL_RAMB               = 0x00000001,
12406  } DWB_OGAM_LUT_HOST_SEL_ENUM;
12407  
12408  /*
12409   * DWB_OGAM_LUT_READ_COLOR_SEL_ENUM enum
12410   */
12411  
12412  typedef enum DWB_OGAM_LUT_READ_COLOR_SEL_ENUM {
12413  DWB_OGAM_LUT_READ_COLOR_SEL_B            = 0x00000000,
12414  DWB_OGAM_LUT_READ_COLOR_SEL_G            = 0x00000001,
12415  DWB_OGAM_LUT_READ_COLOR_SEL_R            = 0x00000002,
12416  DWB_OGAM_LUT_READ_COLOR_SEL_RESERVED     = 0x00000003,
12417  } DWB_OGAM_LUT_READ_COLOR_SEL_ENUM;
12418  
12419  /*
12420   * DWB_OGAM_LUT_READ_DBG_ENUM enum
12421   */
12422  
12423  typedef enum DWB_OGAM_LUT_READ_DBG_ENUM {
12424  DWB_OGAM_LUT_READ_DBG_DISABLE            = 0x00000000,
12425  DWB_OGAM_LUT_READ_DBG_ENABLE             = 0x00000001,
12426  } DWB_OGAM_LUT_READ_DBG_ENUM;
12427  
12428  /*
12429   * DWB_OGAM_MODE_ENUM enum
12430   */
12431  
12432  typedef enum DWB_OGAM_MODE_ENUM {
12433  DWB_OGAM_MODE_BYPASS                     = 0x00000000,
12434  DWB_OGAM_MODE_RESERVED                   = 0x00000001,
12435  DWB_OGAM_MODE_RAM_LUT_ENABLED            = 0x00000002,
12436  } DWB_OGAM_MODE_ENUM;
12437  
12438  /*
12439   * DWB_OGAM_PWL_DISABLE_ENUM enum
12440   */
12441  
12442  typedef enum DWB_OGAM_PWL_DISABLE_ENUM {
12443  DWB_OGAM_PWL_DISABLE_FALSE               = 0x00000000,
12444  DWB_OGAM_PWL_DISABLE_TRUE                = 0x00000001,
12445  } DWB_OGAM_PWL_DISABLE_ENUM;
12446  
12447  /*
12448   * DWB_OGAM_SELECT_ENUM enum
12449   */
12450  
12451  typedef enum DWB_OGAM_SELECT_ENUM {
12452  DWB_OGAM_SELECT_A                        = 0x00000000,
12453  DWB_OGAM_SELECT_B                        = 0x00000001,
12454  } DWB_OGAM_SELECT_ENUM;
12455  
12456  /*******************************************************
12457   * RDPCSPIPE Enums
12458   *******************************************************/
12459  
12460  /*
12461   * RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN enum
12462   */
12463  
12464  typedef enum RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN {
12465  RDPCSPIPE_EXT_PCLK_EN_DISABLE            = 0x00000000,
12466  RDPCSPIPE_EXT_PCLK_EN_ENABLE             = 0x00000001,
12467  } RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN;
12468  
12469  /*
12470   * RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN enum
12471   */
12472  
12473  typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN {
12474  RDPCSPIPE_APBCLK_DISABLE                 = 0x00000000,
12475  RDPCSPIPE_APBCLK_ENABLE                  = 0x00000001,
12476  } RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN;
12477  
12478  /*
12479   * RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON enum
12480   */
12481  
12482  typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON {
12483  RDPCS_PIPE_CLK_CLOCK_OFF                 = 0x00000000,
12484  RDPCS_PIPE_CLK_CLOCK_ON                  = 0x00000001,
12485  } RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON;
12486  
12487  /*
12488   * RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN enum
12489   */
12490  
12491  typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN {
12492  RDPCS_PIPE_CLK_DISABLE                   = 0x00000000,
12493  RDPCS_PIPE_CLK_ENABLE                    = 0x00000001,
12494  } RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN;
12495  
12496  /*
12497   * RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS enum
12498   */
12499  
12500  typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS {
12501  RDPCS_PIPE_CLK_GATE_ENABLE               = 0x00000000,
12502  RDPCS_PIPE_CLK_GATE_DISABLE              = 0x00000001,
12503  } RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS;
12504  
12505  /*
12506   * RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON enum
12507   */
12508  
12509  typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON {
12510  RDPCS_PIPE_PHYD32CLK_CLOCK_OFF           = 0x00000000,
12511  RDPCS_PIPE_PHYD32CLK_CLOCK_ON            = 0x00000001,
12512  } RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON;
12513  
12514  /*
12515   * RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON enum
12516   */
12517  
12518  typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON {
12519  RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_OFF       = 0x00000000,
12520  RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_ON        = 0x00000001,
12521  } RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON;
12522  
12523  /*
12524   * RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN enum
12525   */
12526  
12527  typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN {
12528  RDPCSPIPE_SRAMCLK_DISABLE                = 0x00000000,
12529  RDPCSPIPE_SRAMCLK_ENABLE                 = 0x00000001,
12530  } RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN;
12531  
12532  /*
12533   * RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS enum
12534   */
12535  
12536  typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS {
12537  RDPCSPIPE_SRAMCLK_GATE_ENABLE            = 0x00000000,
12538  RDPCSPIPE_SRAMCLK_GATE_DISABLE           = 0x00000001,
12539  } RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS;
12540  
12541  /*
12542   * RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS enum
12543   */
12544  
12545  typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS {
12546  RDPCSPIPE_SRAMCLK_NOT_PASS               = 0x00000000,
12547  RDPCSPIPE_SRAMCLK_PASS                   = 0x00000001,
12548  } RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS;
12549  
12550  /*
12551   * RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN enum
12552   */
12553  
12554  typedef enum RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN {
12555  RDPCS_PIPE_FIFO_DISABLE                  = 0x00000000,
12556  RDPCS_PIPE_FIFO_ENABLE                   = 0x00000001,
12557  } RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN;
12558  
12559  /*
12560   * RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN enum
12561   */
12562  
12563  typedef enum RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN {
12564  RDPCS_PIPE_FIFO_LANE_DISABLE             = 0x00000000,
12565  RDPCS_PIPE_FIFO_LANE_ENABLE              = 0x00000001,
12566  } RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN;
12567  
12568  /*
12569   * RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET enum
12570   */
12571  
12572  typedef enum RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET {
12573  RDPCS_PIPE_SOFT_RESET_DISABLE            = 0x00000000,
12574  RDPCS_PIPE_SOFT_RESET_ENABLE             = 0x00000001,
12575  } RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET;
12576  
12577  /*
12578   * RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET enum
12579   */
12580  
12581  typedef enum RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET {
12582  RDPCSPIPE_SRAM_SRAM_RESET_DISABLE        = 0x00000000,
12583  RDPCSPIPE_SRAM_SRAM_RESET_ENABLE         = 0x00000001,
12584  } RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET;
12585  
12586  /*
12587   * RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK enum
12588   */
12589  
12590  typedef enum RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK {
12591  RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_DISABLE = 0x00000000,
12592  RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_ENABLE = 0x00000001,
12593  } RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK;
12594  
12595  /*
12596   * RDPCSPIPE_DBG_OCLA_SEL enum
12597   */
12598  
12599  typedef enum RDPCSPIPE_DBG_OCLA_SEL {
12600  RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_7_0       = 0x00000000,
12601  RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_15_8      = 0x00000001,
12602  RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_23_16     = 0x00000002,
12603  RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_31_24     = 0x00000003,
12604  RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_39_32     = 0x00000004,
12605  RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_47_40     = 0x00000005,
12606  RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_55_48     = 0x00000006,
12607  RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_63_56     = 0x00000007,
12608  } RDPCSPIPE_DBG_OCLA_SEL;
12609  
12610  /*
12611   * RDPCSPIPE_ENC_TYPE enum
12612   */
12613  
12614  typedef enum RDPCSPIPE_ENC_TYPE {
12615  HDMI_TMDS_OR_DP_8B10B                    = 0x00000000,
12616  HDMI_FRL                                 = 0x00000001,
12617  DP_128B132B                              = 0x00000002,
12618  } RDPCSPIPE_ENC_TYPE;
12619  
12620  /*
12621   * RDPCSPIPE_FIFO_EMPTY enum
12622   */
12623  
12624  typedef enum RDPCSPIPE_FIFO_EMPTY {
12625  RDPCSPIPE_FIFO_NOT_EMPTY                 = 0x00000000,
12626  RDPCSPIPE_FIFO_IS_EMPTY                  = 0x00000001,
12627  } RDPCSPIPE_FIFO_EMPTY;
12628  
12629  /*
12630   * RDPCSPIPE_FIFO_FULL enum
12631   */
12632  
12633  typedef enum RDPCSPIPE_FIFO_FULL {
12634  RDPCSPIPE_FIFO_NOT_FULL                  = 0x00000000,
12635  RDPCSPIPE_FIFO_IS_FULL                   = 0x00000001,
12636  } RDPCSPIPE_FIFO_FULL;
12637  
12638  /*
12639   * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK enum
12640   */
12641  
12642  typedef enum RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK {
12643  RDPCSPIPE_APB_PSLVERR_MASK_DISABLE       = 0x00000000,
12644  RDPCSPIPE_APB_PSLVERR_MASK_ENABLE        = 0x00000001,
12645  } RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK;
12646  
12647  /*
12648   * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE enum
12649   */
12650  
12651  typedef enum RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE {
12652  RDPCSPIPE_DPALT_4LANE_TOGGLE_2LANE       = 0x00000000,
12653  RDPCSPIPE_DPALT_4LANE_TOGGLE_4LANE       = 0x00000001,
12654  } RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE;
12655  
12656  /*
12657   * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK enum
12658   */
12659  
12660  typedef enum RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK {
12661  RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_DISABLE = 0x00000000,
12662  RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_ENABLE = 0x00000001,
12663  } RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK;
12664  
12665  /*
12666   * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE enum
12667   */
12668  
12669  typedef enum RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE {
12670  RDPCSPIPE_DPALT_DISABLE_TOGGLE_ENABLE    = 0x00000000,
12671  RDPCSPIPE_DPALT_DISABLE_TOGGLE_DISABLE   = 0x00000001,
12672  } RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE;
12673  
12674  /*
12675   * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK enum
12676   */
12677  
12678  typedef enum RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK {
12679  RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_DISABLE = 0x00000000,
12680  RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_ENABLE = 0x00000001,
12681  } RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK;
12682  
12683  /*
12684   * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK enum
12685   */
12686  
12687  typedef enum RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK {
12688  RDPCSPIPE_PIPE_FIFO_ERROR_MASK_DISABLE   = 0x00000000,
12689  RDPCSPIPE_PIPE_FIFO_ERROR_MASK_ENABLE    = 0x00000001,
12690  } RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK;
12691  
12692  /*
12693   * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK enum
12694   */
12695  
12696  typedef enum RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK {
12697  RDPCSPIPE_REG_FIFO_ERROR_MASK_DISABLE    = 0x00000000,
12698  RDPCSPIPE_REG_FIFO_ERROR_MASK_ENABLE     = 0x00000001,
12699  } RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK;
12700  
12701  /*
12702   * RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK enum
12703   */
12704  
12705  typedef enum RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK {
12706  RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_DISABLE = 0x00000000,
12707  RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_ENABLE = 0x00000001,
12708  } RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK;
12709  
12710  /*
12711   * RDPCSPIPE_PACK_MODE enum
12712   */
12713  
12714  typedef enum RDPCSPIPE_PACK_MODE {
12715  TIGHT_PACK                               = 0x00000000,
12716  LOOSE_PACK                               = 0x00000001,
12717  } RDPCSPIPE_PACK_MODE;
12718  
12719  /*
12720   * RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL enum
12721   */
12722  
12723  typedef enum RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL {
12724  RDPCSPIPE_PHY_CR_MUX_SEL_FOR_USB         = 0x00000000,
12725  RDPCSPIPE_PHY_CR_MUX_SEL_FOR_DC          = 0x00000001,
12726  } RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL;
12727  
12728  /*
12729   * RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL enum
12730   */
12731  
12732  typedef enum RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL {
12733  RDPCSPIPE_PHY_CR_PARA_SEL_JTAG           = 0x00000000,
12734  RDPCSPIPE_PHY_CR_PARA_SEL_CR             = 0x00000001,
12735  } RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL;
12736  
12737  /*
12738   * RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE enum
12739   */
12740  
12741  typedef enum RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE {
12742  RDPCSPIPE_PHY_REF_RANGE_0                = 0x00000000,
12743  RDPCSPIPE_PHY_REF_RANGE_1                = 0x00000001,
12744  RDPCSPIPE_PHY_REF_RANGE_2                = 0x00000002,
12745  RDPCSPIPE_PHY_REF_RANGE_3                = 0x00000003,
12746  RDPCSPIPE_PHY_REF_RANGE_4                = 0x00000004,
12747  RDPCSPIPE_PHY_REF_RANGE_5                = 0x00000005,
12748  RDPCSPIPE_PHY_REF_RANGE_6                = 0x00000006,
12749  RDPCSPIPE_PHY_REF_RANGE_7                = 0x00000007,
12750  } RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE;
12751  
12752  /*
12753   * RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE enum
12754   */
12755  
12756  typedef enum RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE {
12757  RDPCSPIPE_SRAM_EXT_LD_NOT_DONE           = 0x00000000,
12758  RDPCSPIPE_SRAM_EXT_LD_DONE               = 0x00000001,
12759  } RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE;
12760  
12761  /*
12762   * RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE enum
12763   */
12764  
12765  typedef enum RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE {
12766  RDPCSPIPE_SRAM_INIT_NOT_DONE             = 0x00000000,
12767  RDPCSPIPE_SRAM_INIT_DONE                 = 0x00000001,
12768  } RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE;
12769  
12770  /*
12771   * RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV enum
12772   */
12773  
12774  typedef enum RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV {
12775  RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV1      = 0x00000000,
12776  RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV2      = 0x00000001,
12777  RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV3      = 0x00000002,
12778  RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV8      = 0x00000003,
12779  RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV16     = 0x00000004,
12780  } RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV;
12781  
12782  /*
12783   * RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV enum
12784   */
12785  
12786  typedef enum RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV {
12787  RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0 = 0x00000000,
12788  RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1 = 0x00000001,
12789  RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2 = 0x00000002,
12790  RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3 = 0x00000003,
12791  } RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV;
12792  
12793  /*
12794   * RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV enum
12795   */
12796  
12797  typedef enum RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV {
12798  RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV        = 0x00000000,
12799  RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV2       = 0x00000001,
12800  RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV4       = 0x00000002,
12801  RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV8       = 0x00000003,
12802  RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV3       = 0x00000004,
12803  RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV5       = 0x00000005,
12804  RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV6       = 0x00000006,
12805  RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV10      = 0x00000007,
12806  } RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV;
12807  
12808  /*
12809   * RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL enum
12810   */
12811  
12812  typedef enum RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL {
12813  RDPCSPIPE_PHY_DP_TX_TERM_CTRL_54         = 0x00000000,
12814  RDPCSPIPE_PHY_DP_TX_TERM_CTRL_52         = 0x00000001,
12815  RDPCSPIPE_PHY_DP_TX_TERM_CTRL_50         = 0x00000002,
12816  RDPCSPIPE_PHY_DP_TX_TERM_CTRL_48         = 0x00000003,
12817  RDPCSPIPE_PHY_DP_TX_TERM_CTRL_46         = 0x00000004,
12818  RDPCSPIPE_PHY_DP_TX_TERM_CTRL_44         = 0x00000005,
12819  RDPCSPIPE_PHY_DP_TX_TERM_CTRL_42         = 0x00000006,
12820  RDPCSPIPE_PHY_DP_TX_TERM_CTRL_40         = 0x00000007,
12821  } RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL;
12822  
12823  /*
12824   * RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT enum
12825   */
12826  
12827  typedef enum RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT {
12828  RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_NO_DETECT = 0x00000000,
12829  RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_DETECT  = 0x00000001,
12830  } RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT;
12831  
12832  /*
12833   * RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE enum
12834   */
12835  
12836  typedef enum RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE {
12837  RDPCSPIPE_PHY_DP_TX_RATE                 = 0x00000000,
12838  RDPCSPIPE_PHY_DP_TX_RATE_DIV2            = 0x00000001,
12839  RDPCSPIPE_PHY_DP_TX_RATE_DIV4            = 0x00000002,
12840  } RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE;
12841  
12842  /*
12843   * RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH enum
12844   */
12845  
12846  typedef enum RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH {
12847  RDPCSPIPE_PHY_DP_TX_WIDTH_8              = 0x00000000,
12848  RDPCSPIPE_PHY_DP_TX_WIDTH_10             = 0x00000001,
12849  RDPCSPIPE_PHY_DP_TX_WIDTH_16             = 0x00000002,
12850  RDPCSPIPE_PHY_DP_TX_WIDTH_20             = 0x00000003,
12851  } RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH;
12852  
12853  /*
12854   * RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE enum
12855   */
12856  
12857  typedef enum RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE {
12858  RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_UP     = 0x00000000,
12859  RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD         = 0x00000001,
12860  RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD_OFF     = 0x00000002,
12861  RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_DOWN   = 0x00000003,
12862  } RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE;
12863  
12864  /*
12865   * RDPCSPIPE_PHY_IF_WIDTH enum
12866   */
12867  
12868  typedef enum RDPCSPIPE_PHY_IF_WIDTH {
12869  PHY_IF_WIDTH_10BIT                       = 0x00000000,
12870  PHY_IF_WIDTH_20BIT                       = 0x00000001,
12871  PHY_IF_WIDTH_40BIT                       = 0x00000002,
12872  PHY_IF_WIDTH_80BIT                       = 0x00000003,
12873  } RDPCSPIPE_PHY_IF_WIDTH;
12874  
12875  /*
12876   * RDPCSPIPE_PHY_RATE enum
12877   */
12878  
12879  typedef enum RDPCSPIPE_PHY_RATE {
12880  PHY_DP_RATE_1P62                         = 0x00000000,
12881  PHY_DP_RATE_2P7                          = 0x00000001,
12882  PHY_DP_RATE_5P4                          = 0x00000002,
12883  PHY_DP_RATE_8P1                          = 0x00000003,
12884  PHY_DP_RATE_2P16                         = 0x00000004,
12885  PHY_DP_RATE_2P43                         = 0x00000005,
12886  PHY_DP_RATE_3P24                         = 0x00000006,
12887  PHY_DP_RATE_4P32                         = 0x00000007,
12888  PHY_DP_RATE_10P                          = 0x00000008,
12889  PHY_DP_RATE_13P5                         = 0x00000009,
12890  PHY_DP_RATE_20P                          = 0x0000000a,
12891  PHY_CUSTOM_RATE                          = 0x0000000f,
12892  } RDPCSPIPE_PHY_RATE;
12893  
12894  /*
12895   * RDPCSPIPE_PHY_REF_ALT_CLK_EN enum
12896   */
12897  
12898  typedef enum RDPCSPIPE_PHY_REF_ALT_CLK_EN {
12899  RDPCSPIPE_PHY_REF_ALT_CLK_DISABLE        = 0x00000000,
12900  RDPCSPIPE_PHY_REF_ALT_CLK_ENABLE         = 0x00000001,
12901  } RDPCSPIPE_PHY_REF_ALT_CLK_EN;
12902  
12903  /*
12904   * RDPCSPIPE_TEST_CLK_SEL enum
12905   */
12906  
12907  typedef enum RDPCSPIPE_TEST_CLK_SEL {
12908  RDPCSPIPE_TEST_CLK_SEL_NONE              = 0x00000000,
12909  RDPCSPIPE_TEST_CLK_SEL_CFGCLK            = 0x00000001,
12910  RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS = 0x00000002,
12911  RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS = 0x00000003,
12912  RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4 = 0x00000004,
12913  RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4 = 0x00000005,
12914  RDPCSPIPE_TEST_CLK_SEL_SRAMCLK           = 0x00000006,
12915  RDPCSPIPE_TEST_CLK_SEL_EXT_CR_CLK        = 0x00000007,
12916  RDPCSPIPE_TEST_CLK_SEL_DP_TX0_WORD_CLK   = 0x00000008,
12917  RDPCSPIPE_TEST_CLK_SEL_DP_TX1_WORD_CLK   = 0x00000009,
12918  RDPCSPIPE_TEST_CLK_SEL_DP_TX2_WORD_CLK   = 0x0000000a,
12919  RDPCSPIPE_TEST_CLK_SEL_DP_TX3_WORD_CLK   = 0x0000000b,
12920  RDPCSPIPE_TEST_CLK_SEL_DP_MPLLB_DIV_CLK  = 0x0000000c,
12921  RDPCSPIPE_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK = 0x0000000d,
12922  RDPCSPIPE_TEST_CLK_SEL_PHY_REF_DIG_CLK   = 0x0000000e,
12923  RDPCSPIPE_TEST_CLK_SEL_REF_DIG_FR_clk    = 0x0000000f,
12924  RDPCSPIPE_TEST_CLK_SEL_dtb_out0          = 0x00000010,
12925  RDPCSPIPE_TEST_CLK_SEL_dtb_out1          = 0x00000011,
12926  } RDPCSPIPE_TEST_CLK_SEL;
12927  
12928  /*
12929   * RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB enum
12930   */
12931  
12932  typedef enum RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB {
12933  RDPCSPIPE_LANE_PACK_FROM_MSB_DISABLE     = 0x00000000,
12934  RDPCSPIPE_LANE_PACK_FROM_MSB_ENABLE      = 0x00000001,
12935  } RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB;
12936  
12937  /*
12938   * RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE enum
12939   */
12940  
12941  typedef enum RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE {
12942  RDPCSPIPE_MEM_PWR_NO_FORCE               = 0x00000000,
12943  RDPCSPIPE_MEM_PWR_LIGHT_SLEEP            = 0x00000001,
12944  RDPCSPIPE_MEM_PWR_DEEP_SLEEP             = 0x00000002,
12945  RDPCSPIPE_MEM_PWR_SHUT_DOWN              = 0x00000003,
12946  } RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE;
12947  
12948  /*
12949   * RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE enum
12950   */
12951  
12952  typedef enum RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE {
12953  RDPCSPIPE_MEM_PWR_PWR_STATE_ON           = 0x00000000,
12954  RDPCSPIPE_MEM_PWR_PWR_STATE_LIGHT_SLEEP  = 0x00000001,
12955  RDPCSPIPE_MEM_PWR_PWR_STATE_DEEP_SLEEP   = 0x00000002,
12956  RDPCSPIPE_MEM_PWR_PWR_STATE_SHUT_DOWN    = 0x00000003,
12957  } RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE;
12958  
12959  /*
12960   * RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK enum
12961   */
12962  
12963  typedef enum RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK {
12964  RDPCSPIPE_LANE_BIT_ORDER_REVERSE_DISABLE = 0x00000000,
12965  RDPCSPIPE_LANE_BIT_ORDER_REVERSE_ENABLE  = 0x00000001,
12966  } RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK;
12967  
12968  /*******************************************************
12969   * GDS Enums
12970   *******************************************************/
12971  
12972  /*
12973   * GDS_PERFCOUNT_SELECT enum
12974   */
12975  
12976  typedef enum GDS_PERFCOUNT_SELECT {
12977  GDS_PERF_SEL_WR_COMP                     = 0x00000000,
12978  GDS_PERF_SEL_WBUF_WR                     = 0x00000001,
12979  GDS_PERF_SEL_SE0_NORET                   = 0x00000002,
12980  GDS_PERF_SEL_SE0_RET                     = 0x00000003,
12981  GDS_PERF_SEL_SE0_ORD_CNT                 = 0x00000004,
12982  GDS_PERF_SEL_SE0_2COMP_REQ               = 0x00000005,
12983  GDS_PERF_SEL_SE0_ORD_WAVE_VALID          = 0x00000006,
12984  GDS_PERF_SEL_SE0_GDS_STALL_BY_ORD        = 0x00000007,
12985  GDS_PERF_SEL_SE0_GDS_WR_OP               = 0x00000008,
12986  GDS_PERF_SEL_SE0_GDS_RD_OP               = 0x00000009,
12987  GDS_PERF_SEL_SE0_GDS_ATOM_OP             = 0x0000000a,
12988  GDS_PERF_SEL_SE0_GDS_REL_OP              = 0x0000000b,
12989  GDS_PERF_SEL_SE0_GDS_CMPXCH_OP           = 0x0000000c,
12990  GDS_PERF_SEL_SE0_GDS_BYTE_OP             = 0x0000000d,
12991  GDS_PERF_SEL_SE0_GDS_SHORT_OP            = 0x0000000e,
12992  GDS_PERF_SEL_SE1_NORET                   = 0x0000000f,
12993  GDS_PERF_SEL_SE1_RET                     = 0x00000010,
12994  GDS_PERF_SEL_SE1_ORD_CNT                 = 0x00000011,
12995  GDS_PERF_SEL_SE1_2COMP_REQ               = 0x00000012,
12996  GDS_PERF_SEL_SE1_ORD_WAVE_VALID          = 0x00000013,
12997  GDS_PERF_SEL_SE1_GDS_STALL_BY_ORD        = 0x00000014,
12998  GDS_PERF_SEL_SE1_GDS_WR_OP               = 0x00000015,
12999  GDS_PERF_SEL_SE1_GDS_RD_OP               = 0x00000016,
13000  GDS_PERF_SEL_SE1_GDS_ATOM_OP             = 0x00000017,
13001  GDS_PERF_SEL_SE1_GDS_REL_OP              = 0x00000018,
13002  GDS_PERF_SEL_SE1_GDS_CMPXCH_OP           = 0x00000019,
13003  GDS_PERF_SEL_SE1_GDS_BYTE_OP             = 0x0000001a,
13004  GDS_PERF_SEL_SE1_GDS_SHORT_OP            = 0x0000001b,
13005  GDS_PERF_SEL_SE2_NORET                   = 0x0000001c,
13006  GDS_PERF_SEL_SE2_RET                     = 0x0000001d,
13007  GDS_PERF_SEL_SE2_ORD_CNT                 = 0x0000001e,
13008  GDS_PERF_SEL_SE2_2COMP_REQ               = 0x0000001f,
13009  GDS_PERF_SEL_SE2_ORD_WAVE_VALID          = 0x00000020,
13010  GDS_PERF_SEL_SE2_GDS_STALL_BY_ORD        = 0x00000021,
13011  GDS_PERF_SEL_SE2_GDS_WR_OP               = 0x00000022,
13012  GDS_PERF_SEL_SE2_GDS_RD_OP               = 0x00000023,
13013  GDS_PERF_SEL_SE2_GDS_ATOM_OP             = 0x00000024,
13014  GDS_PERF_SEL_SE2_GDS_REL_OP              = 0x00000025,
13015  GDS_PERF_SEL_SE2_GDS_CMPXCH_OP           = 0x00000026,
13016  GDS_PERF_SEL_SE2_GDS_BYTE_OP             = 0x00000027,
13017  GDS_PERF_SEL_SE2_GDS_SHORT_OP            = 0x00000028,
13018  GDS_PERF_SEL_SE3_NORET                   = 0x00000029,
13019  GDS_PERF_SEL_SE3_RET                     = 0x0000002a,
13020  GDS_PERF_SEL_SE3_ORD_CNT                 = 0x0000002b,
13021  GDS_PERF_SEL_SE3_2COMP_REQ               = 0x0000002c,
13022  GDS_PERF_SEL_SE3_ORD_WAVE_VALID          = 0x0000002d,
13023  GDS_PERF_SEL_SE3_GDS_STALL_BY_ORD        = 0x0000002e,
13024  GDS_PERF_SEL_SE3_GDS_WR_OP               = 0x0000002f,
13025  GDS_PERF_SEL_SE3_GDS_RD_OP               = 0x00000030,
13026  GDS_PERF_SEL_SE3_GDS_ATOM_OP             = 0x00000031,
13027  GDS_PERF_SEL_SE3_GDS_REL_OP              = 0x00000032,
13028  GDS_PERF_SEL_SE3_GDS_CMPXCH_OP           = 0x00000033,
13029  GDS_PERF_SEL_SE3_GDS_BYTE_OP             = 0x00000034,
13030  GDS_PERF_SEL_SE3_GDS_SHORT_OP            = 0x00000035,
13031  GDS_PERF_SEL_SE4_NORET                   = 0x00000036,
13032  GDS_PERF_SEL_SE4_RET                     = 0x00000037,
13033  GDS_PERF_SEL_SE4_ORD_CNT                 = 0x00000038,
13034  GDS_PERF_SEL_SE4_2COMP_REQ               = 0x00000039,
13035  GDS_PERF_SEL_SE4_ORD_WAVE_VALID          = 0x0000003a,
13036  GDS_PERF_SEL_SE4_GDS_STALL_BY_ORD        = 0x0000003b,
13037  GDS_PERF_SEL_SE4_GDS_WR_OP               = 0x0000003c,
13038  GDS_PERF_SEL_SE4_GDS_RD_OP               = 0x0000003d,
13039  GDS_PERF_SEL_SE4_GDS_ATOM_OP             = 0x0000003e,
13040  GDS_PERF_SEL_SE4_GDS_REL_OP              = 0x0000003f,
13041  GDS_PERF_SEL_SE4_GDS_CMPXCH_OP           = 0x00000040,
13042  GDS_PERF_SEL_SE4_GDS_BYTE_OP             = 0x00000041,
13043  GDS_PERF_SEL_SE4_GDS_SHORT_OP            = 0x00000042,
13044  GDS_PERF_SEL_SE5_NORET                   = 0x00000043,
13045  GDS_PERF_SEL_SE5_RET                     = 0x00000044,
13046  GDS_PERF_SEL_SE5_ORD_CNT                 = 0x00000045,
13047  GDS_PERF_SEL_SE5_2COMP_REQ               = 0x00000046,
13048  GDS_PERF_SEL_SE5_ORD_WAVE_VALID          = 0x00000047,
13049  GDS_PERF_SEL_SE5_GDS_STALL_BY_ORD        = 0x00000048,
13050  GDS_PERF_SEL_SE5_GDS_WR_OP               = 0x00000049,
13051  GDS_PERF_SEL_SE5_GDS_RD_OP               = 0x0000004a,
13052  GDS_PERF_SEL_SE5_GDS_ATOM_OP             = 0x0000004b,
13053  GDS_PERF_SEL_SE5_GDS_REL_OP              = 0x0000004c,
13054  GDS_PERF_SEL_SE5_GDS_CMPXCH_OP           = 0x0000004d,
13055  GDS_PERF_SEL_SE5_GDS_BYTE_OP             = 0x0000004e,
13056  GDS_PERF_SEL_SE5_GDS_SHORT_OP            = 0x0000004f,
13057  GDS_PERF_SEL_SE6_NORET                   = 0x00000050,
13058  GDS_PERF_SEL_SE6_RET                     = 0x00000051,
13059  GDS_PERF_SEL_SE6_ORD_CNT                 = 0x00000052,
13060  GDS_PERF_SEL_SE6_2COMP_REQ               = 0x00000053,
13061  GDS_PERF_SEL_SE6_ORD_WAVE_VALID          = 0x00000054,
13062  GDS_PERF_SEL_SE6_GDS_STALL_BY_ORD        = 0x00000055,
13063  GDS_PERF_SEL_SE6_GDS_WR_OP               = 0x00000056,
13064  GDS_PERF_SEL_SE6_GDS_RD_OP               = 0x00000057,
13065  GDS_PERF_SEL_SE6_GDS_ATOM_OP             = 0x00000058,
13066  GDS_PERF_SEL_SE6_GDS_REL_OP              = 0x00000059,
13067  GDS_PERF_SEL_SE6_GDS_CMPXCH_OP           = 0x0000005a,
13068  GDS_PERF_SEL_SE6_GDS_BYTE_OP             = 0x0000005b,
13069  GDS_PERF_SEL_SE6_GDS_SHORT_OP            = 0x0000005c,
13070  GDS_PERF_SEL_SE7_NORET                   = 0x0000005d,
13071  GDS_PERF_SEL_SE7_RET                     = 0x0000005e,
13072  GDS_PERF_SEL_SE7_ORD_CNT                 = 0x0000005f,
13073  GDS_PERF_SEL_SE7_2COMP_REQ               = 0x00000060,
13074  GDS_PERF_SEL_SE7_ORD_WAVE_VALID          = 0x00000061,
13075  GDS_PERF_SEL_SE7_GDS_STALL_BY_ORD        = 0x00000062,
13076  GDS_PERF_SEL_SE7_GDS_WR_OP               = 0x00000063,
13077  GDS_PERF_SEL_SE7_GDS_RD_OP               = 0x00000064,
13078  GDS_PERF_SEL_SE7_GDS_ATOM_OP             = 0x00000065,
13079  GDS_PERF_SEL_SE7_GDS_REL_OP              = 0x00000066,
13080  GDS_PERF_SEL_SE7_GDS_CMPXCH_OP           = 0x00000067,
13081  GDS_PERF_SEL_SE7_GDS_BYTE_OP             = 0x00000068,
13082  GDS_PERF_SEL_SE7_GDS_SHORT_OP            = 0x00000069,
13083  GDS_PERF_SEL_GWS_RELEASED                = 0x0000006a,
13084  GDS_PERF_SEL_GWS_BYPASS                  = 0x0000006b,
13085  } GDS_PERFCOUNT_SELECT;
13086  
13087  /*******************************************************
13088   * CB Enums
13089   *******************************************************/
13090  
13091  /*
13092   * BlendOp enum
13093   */
13094  
13095  typedef enum BlendOp {
13096  BLEND_ZERO                               = 0x00000000,
13097  BLEND_ONE                                = 0x00000001,
13098  BLEND_SRC_COLOR                          = 0x00000002,
13099  BLEND_ONE_MINUS_SRC_COLOR                = 0x00000003,
13100  BLEND_SRC_ALPHA                          = 0x00000004,
13101  BLEND_ONE_MINUS_SRC_ALPHA                = 0x00000005,
13102  BLEND_DST_ALPHA                          = 0x00000006,
13103  BLEND_ONE_MINUS_DST_ALPHA                = 0x00000007,
13104  BLEND_DST_COLOR                          = 0x00000008,
13105  BLEND_ONE_MINUS_DST_COLOR                = 0x00000009,
13106  BLEND_SRC_ALPHA_SATURATE                 = 0x0000000a,
13107  BLEND_CONSTANT_COLOR                     = 0x0000000b,
13108  BLEND_ONE_MINUS_CONSTANT_COLOR           = 0x0000000c,
13109  BLEND_SRC1_COLOR                         = 0x0000000d,
13110  BLEND_INV_SRC1_COLOR                     = 0x0000000e,
13111  BLEND_SRC1_ALPHA                         = 0x0000000f,
13112  BLEND_INV_SRC1_ALPHA                     = 0x00000010,
13113  BLEND_CONSTANT_ALPHA                     = 0x00000011,
13114  BLEND_ONE_MINUS_CONSTANT_ALPHA           = 0x00000012,
13115  } BlendOp;
13116  
13117  /*
13118   * BlendOpt enum
13119   */
13120  
13121  typedef enum BlendOpt {
13122  FORCE_OPT_AUTO                           = 0x00000000,
13123  FORCE_OPT_DISABLE                        = 0x00000001,
13124  FORCE_OPT_ENABLE_IF_SRC_A_0              = 0x00000002,
13125  FORCE_OPT_ENABLE_IF_SRC_RGB_0            = 0x00000003,
13126  FORCE_OPT_ENABLE_IF_SRC_ARGB_0           = 0x00000004,
13127  FORCE_OPT_ENABLE_IF_SRC_A_1              = 0x00000005,
13128  FORCE_OPT_ENABLE_IF_SRC_RGB_1            = 0x00000006,
13129  FORCE_OPT_ENABLE_IF_SRC_ARGB_1           = 0x00000007,
13130  } BlendOpt;
13131  
13132  /*
13133   * CBMode enum
13134   */
13135  
13136  typedef enum CBMode {
13137  CB_DISABLE                               = 0x00000000,
13138  CB_NORMAL                                = 0x00000001,
13139  CB_ELIMINATE_FAST_CLEAR                  = 0x00000002,
13140  CB_DCC_DECOMPRESS                        = 0x00000003,
13141  CB_RESERVED                              = 0x00000004,
13142  } CBMode;
13143  
13144  /*
13145   * CBPerfClearFilterSel enum
13146   */
13147  
13148  typedef enum CBPerfClearFilterSel {
13149  CB_PERF_CLEAR_FILTER_SEL_NONCLEAR        = 0x00000000,
13150  CB_PERF_CLEAR_FILTER_SEL_CLEAR           = 0x00000001,
13151  } CBPerfClearFilterSel;
13152  
13153  /*
13154   * CBPerfOpFilterSel enum
13155   */
13156  
13157  typedef enum CBPerfOpFilterSel {
13158  CB_PERF_OP_FILTER_SEL_WRITE_ONLY         = 0x00000000,
13159  CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION  = 0x00000001,
13160  CB_PERF_OP_FILTER_SEL_RESOLVE            = 0x00000002,
13161  CB_PERF_OP_FILTER_SEL_DECOMPRESS         = 0x00000003,
13162  CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS   = 0x00000004,
13163  CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 0x00000005,
13164  } CBPerfOpFilterSel;
13165  
13166  /*
13167   * CBPerfSel enum
13168   */
13169  
13170  typedef enum CBPerfSel {
13171  CB_PERF_SEL_NONE                         = 0x00000000,
13172  CB_PERF_SEL_DRAWN_PIXEL                  = 0x00000001,
13173  CB_PERF_SEL_DRAWN_QUAD                   = 0x00000002,
13174  CB_PERF_SEL_DRAWN_QUAD_FRAGMENT          = 0x00000003,
13175  CB_PERF_SEL_DRAWN_TILE                   = 0x00000004,
13176  CB_PERF_SEL_FILTER_DRAWN_PIXEL           = 0x00000005,
13177  CB_PERF_SEL_FILTER_DRAWN_QUAD            = 0x00000006,
13178  CB_PERF_SEL_FILTER_DRAWN_QUAD_FRAGMENT   = 0x00000007,
13179  CB_PERF_SEL_FILTER_DRAWN_TILE            = 0x00000008,
13180  CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_IN     = 0x00000009,
13181  CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_OUT    = 0x0000000a,
13182  CB_PERF_SEL_CC_DCC_COMPRESS_TID_IN       = 0x0000000b,
13183  CB_PERF_SEL_CC_DCC_COMPRESS_TID_OUT      = 0x0000000c,
13184  CB_PERF_SEL_CC_MC_WRITE_REQUEST          = 0x0000000d,
13185  CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x0000000e,
13186  CB_PERF_SEL_CC_MC_READ_REQUEST           = 0x0000000f,
13187  CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT = 0x00000010,
13188  CB_PERF_SEL_DB_CB_EXPORT_VALID_READY     = 0x00000011,
13189  CB_PERF_SEL_DB_CB_EXPORT_VALID_READYB    = 0x00000012,
13190  CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READY    = 0x00000013,
13191  CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READYB   = 0x00000014,
13192  CB_PERF_SEL_RESERVED_21                  = 0x00000015,
13193  CB_PERF_SEL_RESERVED_22                  = 0x00000016,
13194  CB_PERF_SEL_RESERVED_23                  = 0x00000017,
13195  CB_PERF_SEL_RESERVED_24                  = 0x00000018,
13196  CB_PERF_SEL_RESERVED_25                  = 0x00000019,
13197  CB_PERF_SEL_RESERVED_26                  = 0x0000001a,
13198  CB_PERF_SEL_RESERVED_27                  = 0x0000001b,
13199  CB_PERF_SEL_RESERVED_28                  = 0x0000001c,
13200  CB_PERF_SEL_RESERVED_29                  = 0x0000001d,
13201  CB_PERF_SEL_CB_RMI_WRREQ_VALID_READY     = 0x0000001e,
13202  CB_PERF_SEL_CB_RMI_WRREQ_VALID_READYB    = 0x0000001f,
13203  CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READY    = 0x00000020,
13204  CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READYB   = 0x00000021,
13205  CB_PERF_SEL_CB_RMI_RDREQ_VALID_READY     = 0x00000022,
13206  CB_PERF_SEL_CB_RMI_RDREQ_VALID_READYB    = 0x00000023,
13207  CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READY    = 0x00000024,
13208  CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READYB   = 0x00000025,
13209  CB_PERF_SEL_RESERVED_38                  = 0x00000026,
13210  CB_PERF_SEL_RESERVED_39                  = 0x00000027,
13211  CB_PERF_SEL_RESERVED_40                  = 0x00000028,
13212  CB_PERF_SEL_RESERVED_41                  = 0x00000029,
13213  CB_PERF_SEL_RESERVED_42                  = 0x0000002a,
13214  CB_PERF_SEL_RESERVED_43                  = 0x0000002b,
13215  CB_PERF_SEL_RESERVED_44                  = 0x0000002c,
13216  CB_PERF_SEL_RESERVED_45                  = 0x0000002d,
13217  CB_PERF_SEL_RESERVED_46                  = 0x0000002e,
13218  CB_PERF_SEL_RESERVED_47                  = 0x0000002f,
13219  CB_PERF_SEL_RESERVED_48                  = 0x00000030,
13220  CB_PERF_SEL_RESERVED_49                  = 0x00000031,
13221  CB_PERF_SEL_STATIC_CLOCK_EN              = 0x00000032,
13222  CB_PERF_SEL_PERFMON_CLOCK_EN             = 0x00000033,
13223  CB_PERF_SEL_BLEND_CLOCK_EN               = 0x00000034,
13224  CB_PERF_SEL_COLOR_STORE_CLOCK_EN         = 0x00000035,
13225  CB_PERF_SEL_BACKEND_READ_CLOCK_EN        = 0x00000036,
13226  CB_PERF_SEL_GRBM_CLOCK_EN                = 0x00000037,
13227  CB_PERF_SEL_MEMARB_CLOCK_EN              = 0x00000038,
13228  CB_PERF_SEL_BACKEND_EVICT_PIPE_CLOCK_EN  = 0x00000039,
13229  CB_PERF_SEL_BACKEND_FRAGOP_CLOCK_EN      = 0x0000003a,
13230  CB_PERF_SEL_BACKEND_SRC_FIFO_CLOCK_EN    = 0x0000003b,
13231  CB_PERF_SEL_BACKEND_CACHE_CTL_CLOCK_EN   = 0x0000003c,
13232  CB_PERF_SEL_FRONTEND_INPUT_CLOCK_EN      = 0x0000003d,
13233  CB_PERF_SEL_FRONTEND_ADDR_CLOCK_EN       = 0x0000003e,
13234  CB_PERF_SEL_FRONTEND_FDCC_CLOCK_EN       = 0x0000003f,
13235  CB_PERF_SEL_FRONTEND_SAMPLE_MASK_TRACKER_CLOCK_EN = 0x00000040,
13236  CB_PERF_SEL_RESERVED_65                  = 0x00000041,
13237  CB_PERF_SEL_RESERVED_66                  = 0x00000042,
13238  CB_PERF_SEL_RESERVED_67                  = 0x00000043,
13239  CB_PERF_SEL_RESERVED_68                  = 0x00000044,
13240  CB_PERF_SEL_RESERVED_69                  = 0x00000045,
13241  CB_PERF_SEL_RESERVED_70                  = 0x00000046,
13242  CB_PERF_SEL_RESERVED_71                  = 0x00000047,
13243  CB_PERF_SEL_RESERVED_72                  = 0x00000048,
13244  CB_PERF_SEL_RESERVED_73                  = 0x00000049,
13245  CB_PERF_SEL_RESERVED_74                  = 0x0000004a,
13246  CB_PERF_SEL_RESERVED_75                  = 0x0000004b,
13247  CB_PERF_SEL_RESERVED_76                  = 0x0000004c,
13248  CB_PERF_SEL_RESERVED_77                  = 0x0000004d,
13249  CB_PERF_SEL_RESERVED_78                  = 0x0000004e,
13250  CB_PERF_SEL_RESERVED_79                  = 0x0000004f,
13251  CB_PERF_SEL_RESERVED_80                  = 0x00000050,
13252  CB_PERF_SEL_RESERVED_81                  = 0x00000051,
13253  CB_PERF_SEL_RESERVED_82                  = 0x00000052,
13254  CB_PERF_SEL_RESERVED_83                  = 0x00000053,
13255  CB_PERF_SEL_RESERVED_84                  = 0x00000054,
13256  CB_PERF_SEL_RESERVED_85                  = 0x00000055,
13257  CB_PERF_SEL_RESERVED_86                  = 0x00000056,
13258  CB_PERF_SEL_RESERVED_87                  = 0x00000057,
13259  CB_PERF_SEL_RESERVED_88                  = 0x00000058,
13260  CB_PERF_SEL_RESERVED_89                  = 0x00000059,
13261  CB_PERF_SEL_RESERVED_90                  = 0x0000005a,
13262  CB_PERF_SEL_RESERVED_91                  = 0x0000005b,
13263  CB_PERF_SEL_RESERVED_92                  = 0x0000005c,
13264  CB_PERF_SEL_RESERVED_93                  = 0x0000005d,
13265  CB_PERF_SEL_RESERVED_94                  = 0x0000005e,
13266  CB_PERF_SEL_RESERVED_95                  = 0x0000005f,
13267  CB_PERF_SEL_RESERVED_96                  = 0x00000060,
13268  CB_PERF_SEL_RESERVED_97                  = 0x00000061,
13269  CB_PERF_SEL_RESERVED_98                  = 0x00000062,
13270  CB_PERF_SEL_RESERVED_99                  = 0x00000063,
13271  CB_PERF_SEL_CC_TAG_HIT                   = 0x00000064,
13272  CB_PERF_SEL_CC_CACHE_TAG_MISS            = 0x00000065,
13273  CB_PERF_SEL_CC_CACHE_SECTOR_MISS         = 0x00000066,
13274  CB_PERF_SEL_CC_CACHE_SECTOR_HIT          = 0x00000067,
13275  CB_PERF_SEL_CC_CACHE_REEVICTION_STALL    = 0x00000068,
13276  CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x00000069,
13277  CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x0000006a,
13278  CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x0000006b,
13279  CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL   = 0x0000006c,
13280  CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL  = 0x0000006d,
13281  CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL    = 0x0000006e,
13282  CB_PERF_SEL_CC_CACHE_STALL               = 0x0000006f,
13283  CB_PERF_SEL_CC_CACHE_FLUSH               = 0x00000070,
13284  CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED        = 0x00000071,
13285  CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 0x00000072,
13286  CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED     = 0x00000073,
13287  CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED = 0x00000074,
13288  CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC = 0x00000075,
13289  CB_PERF_SEL_RESERVED_118                 = 0x00000076,
13290  CB_PERF_SEL_RESERVED_119                 = 0x00000077,
13291  CB_PERF_SEL_RESERVED_120                 = 0x00000078,
13292  CB_PERF_SEL_RESERVED_121                 = 0x00000079,
13293  CB_PERF_SEL_RESERVED_122                 = 0x0000007a,
13294  CB_PERF_SEL_RESERVED_123                 = 0x0000007b,
13295  CB_PERF_SEL_RESERVED_124                 = 0x0000007c,
13296  CB_PERF_SEL_RESERVED_125                 = 0x0000007d,
13297  CB_PERF_SEL_RESERVED_126                 = 0x0000007e,
13298  CB_PERF_SEL_RESERVED_127                 = 0x0000007f,
13299  CB_PERF_SEL_RESERVED_128                 = 0x00000080,
13300  CB_PERF_SEL_RESERVED_129                 = 0x00000081,
13301  CB_PERF_SEL_RESERVED_130                 = 0x00000082,
13302  CB_PERF_SEL_RESERVED_131                 = 0x00000083,
13303  CB_PERF_SEL_RESERVED_132                 = 0x00000084,
13304  CB_PERF_SEL_RESERVED_133                 = 0x00000085,
13305  CB_PERF_SEL_RESERVED_134                 = 0x00000086,
13306  CB_PERF_SEL_RESERVED_135                 = 0x00000087,
13307  CB_PERF_SEL_RESERVED_136                 = 0x00000088,
13308  CB_PERF_SEL_RESERVED_137                 = 0x00000089,
13309  CB_PERF_SEL_RESERVED_138                 = 0x0000008a,
13310  CB_PERF_SEL_RESERVED_139                 = 0x0000008b,
13311  CB_PERF_SEL_RESERVED_140                 = 0x0000008c,
13312  CB_PERF_SEL_RESERVED_141                 = 0x0000008d,
13313  CB_PERF_SEL_RESERVED_142                 = 0x0000008e,
13314  CB_PERF_SEL_RESERVED_143                 = 0x0000008f,
13315  CB_PERF_SEL_RESERVED_144                 = 0x00000090,
13316  CB_PERF_SEL_RESERVED_145                 = 0x00000091,
13317  CB_PERF_SEL_RESERVED_146                 = 0x00000092,
13318  CB_PERF_SEL_RESERVED_147                 = 0x00000093,
13319  CB_PERF_SEL_RESERVED_148                 = 0x00000094,
13320  CB_PERF_SEL_RESERVED_149                 = 0x00000095,
13321  CB_PERF_SEL_DCC_CACHE_PERF_HIT           = 0x00000096,
13322  CB_PERF_SEL_DCC_CACHE_TAG_MISS           = 0x00000097,
13323  CB_PERF_SEL_DCC_CACHE_SECTOR_MISS        = 0x00000098,
13324  CB_PERF_SEL_DCC_CACHE_REEVICTION_STALL   = 0x00000099,
13325  CB_PERF_SEL_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x0000009a,
13326  CB_PERF_SEL_DCC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x0000009b,
13327  CB_PERF_SEL_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x0000009c,
13328  CB_PERF_SEL_DCC_CACHE_READ_OUTPUT_STALL  = 0x0000009d,
13329  CB_PERF_SEL_DCC_CACHE_WRITE_OUTPUT_STALL = 0x0000009e,
13330  CB_PERF_SEL_DCC_CACHE_ACK_OUTPUT_STALL   = 0x0000009f,
13331  CB_PERF_SEL_DCC_CACHE_STALL              = 0x000000a0,
13332  CB_PERF_SEL_DCC_CACHE_FLUSH              = 0x000000a1,
13333  CB_PERF_SEL_DCC_CACHE_SECTORS_FLUSHED    = 0x000000a2,
13334  CB_PERF_SEL_DCC_CACHE_DIRTY_SECTORS_FLUSHED = 0x000000a3,
13335  CB_PERF_SEL_DCC_CACHE_TAGS_FLUSHED       = 0x000000a4,
13336  CB_PERF_SEL_RESERVED_165                 = 0x000000a5,
13337  CB_PERF_SEL_RESERVED_166                 = 0x000000a6,
13338  CB_PERF_SEL_RESERVED_167                 = 0x000000a7,
13339  CB_PERF_SEL_RESERVED_168                 = 0x000000a8,
13340  CB_PERF_SEL_RESERVED_169                 = 0x000000a9,
13341  CB_PERF_SEL_RESERVED_170                 = 0x000000aa,
13342  CB_PERF_SEL_RESERVED_171                 = 0x000000ab,
13343  CB_PERF_SEL_RESERVED_172                 = 0x000000ac,
13344  CB_PERF_SEL_RESERVED_173                 = 0x000000ad,
13345  CB_PERF_SEL_RESERVED_174                 = 0x000000ae,
13346  CB_PERF_SEL_RESERVED_175                 = 0x000000af,
13347  CB_PERF_SEL_RESERVED_176                 = 0x000000b0,
13348  CB_PERF_SEL_RESERVED_177                 = 0x000000b1,
13349  CB_PERF_SEL_RESERVED_178                 = 0x000000b2,
13350  CB_PERF_SEL_RESERVED_179                 = 0x000000b3,
13351  CB_PERF_SEL_RESERVED_180                 = 0x000000b4,
13352  CB_PERF_SEL_RESERVED_181                 = 0x000000b5,
13353  CB_PERF_SEL_RESERVED_182                 = 0x000000b6,
13354  CB_PERF_SEL_RESERVED_183                 = 0x000000b7,
13355  CB_PERF_SEL_RESERVED_184                 = 0x000000b8,
13356  CB_PERF_SEL_RESERVED_185                 = 0x000000b9,
13357  CB_PERF_SEL_RESERVED_186                 = 0x000000ba,
13358  CB_PERF_SEL_RESERVED_187                 = 0x000000bb,
13359  CB_PERF_SEL_RESERVED_188                 = 0x000000bc,
13360  CB_PERF_SEL_RESERVED_189                 = 0x000000bd,
13361  CB_PERF_SEL_RESERVED_190                 = 0x000000be,
13362  CB_PERF_SEL_RESERVED_191                 = 0x000000bf,
13363  CB_PERF_SEL_RESERVED_192                 = 0x000000c0,
13364  CB_PERF_SEL_RESERVED_193                 = 0x000000c1,
13365  CB_PERF_SEL_RESERVED_194                 = 0x000000c2,
13366  CB_PERF_SEL_RESERVED_195                 = 0x000000c3,
13367  CB_PERF_SEL_RESERVED_196                 = 0x000000c4,
13368  CB_PERF_SEL_RESERVED_197                 = 0x000000c5,
13369  CB_PERF_SEL_RESERVED_198                 = 0x000000c6,
13370  CB_PERF_SEL_RESERVED_199                 = 0x000000c7,
13371  CB_PERF_SEL_BLEND_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED = 0x000000c8,
13372  CB_PERF_SEL_BLEND_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED = 0x000000c9,
13373  CB_PERF_SEL_BLEND_QUAD_COULD_HAVE_BEEN_DISCARDED = 0x000000ca,
13374  CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 0x000000cb,
13375  CB_PERF_SEL_BLEND_STALL_AT_OUTPUT        = 0x000000cc,
13376  CB_PERF_SEL_RESERVED_205                 = 0x000000cd,
13377  CB_PERF_SEL_RESERVED_206                 = 0x000000ce,
13378  CB_PERF_SEL_RESERVED_207                 = 0x000000cf,
13379  CB_PERF_SEL_RESERVED_208                 = 0x000000d0,
13380  CB_PERF_SEL_RESERVED_209                 = 0x000000d1,
13381  CB_PERF_SEL_RESERVED_210                 = 0x000000d2,
13382  CB_PERF_SEL_RESERVED_211                 = 0x000000d3,
13383  CB_PERF_SEL_RESERVED_212                 = 0x000000d4,
13384  CB_PERF_SEL_RESERVED_213                 = 0x000000d5,
13385  CB_PERF_SEL_RESERVED_214                 = 0x000000d6,
13386  CB_PERF_SEL_RESERVED_215                 = 0x000000d7,
13387  CB_PERF_SEL_RESERVED_216                 = 0x000000d8,
13388  CB_PERF_SEL_RESERVED_217                 = 0x000000d9,
13389  CB_PERF_SEL_RESERVED_218                 = 0x000000da,
13390  CB_PERF_SEL_RESERVED_219                 = 0x000000db,
13391  CB_PERF_SEL_RESERVED_220                 = 0x000000dc,
13392  CB_PERF_SEL_RESERVED_221                 = 0x000000dd,
13393  CB_PERF_SEL_RESERVED_222                 = 0x000000de,
13394  CB_PERF_SEL_RESERVED_223                 = 0x000000df,
13395  CB_PERF_SEL_RESERVED_224                 = 0x000000e0,
13396  CB_PERF_SEL_RESERVED_225                 = 0x000000e1,
13397  CB_PERF_SEL_RESERVED_226                 = 0x000000e2,
13398  CB_PERF_SEL_RESERVED_227                 = 0x000000e3,
13399  CB_PERF_SEL_RESERVED_228                 = 0x000000e4,
13400  CB_PERF_SEL_RESERVED_229                 = 0x000000e5,
13401  CB_PERF_SEL_RESERVED_230                 = 0x000000e6,
13402  CB_PERF_SEL_RESERVED_231                 = 0x000000e7,
13403  CB_PERF_SEL_RESERVED_232                 = 0x000000e8,
13404  CB_PERF_SEL_RESERVED_233                 = 0x000000e9,
13405  CB_PERF_SEL_RESERVED_234                 = 0x000000ea,
13406  CB_PERF_SEL_RESERVED_235                 = 0x000000eb,
13407  CB_PERF_SEL_RESERVED_236                 = 0x000000ec,
13408  CB_PERF_SEL_RESERVED_237                 = 0x000000ed,
13409  CB_PERF_SEL_RESERVED_238                 = 0x000000ee,
13410  CB_PERF_SEL_RESERVED_239                 = 0x000000ef,
13411  CB_PERF_SEL_RESERVED_240                 = 0x000000f0,
13412  CB_PERF_SEL_RESERVED_241                 = 0x000000f1,
13413  CB_PERF_SEL_RESERVED_242                 = 0x000000f2,
13414  CB_PERF_SEL_RESERVED_243                 = 0x000000f3,
13415  CB_PERF_SEL_RESERVED_244                 = 0x000000f4,
13416  CB_PERF_SEL_RESERVED_245                 = 0x000000f5,
13417  CB_PERF_SEL_RESERVED_246                 = 0x000000f6,
13418  CB_PERF_SEL_RESERVED_247                 = 0x000000f7,
13419  CB_PERF_SEL_RESERVED_248                 = 0x000000f8,
13420  CB_PERF_SEL_RESERVED_249                 = 0x000000f9,
13421  CB_PERF_SEL_EVENT                        = 0x000000fa,
13422  CB_PERF_SEL_EVENT_CACHE_FLUSH_TS         = 0x000000fb,
13423  CB_PERF_SEL_EVENT_CONTEXT_DONE           = 0x000000fc,
13424  CB_PERF_SEL_EVENT_CACHE_FLUSH            = 0x000000fd,
13425  CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 0x000000fe,
13426  CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 0x000000ff,
13427  CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 0x00000100,
13428  CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META  = 0x00000101,
13429  CB_PERF_SEL_CC_SURFACE_SYNC              = 0x00000102,
13430  CB_PERF_SEL_RESERVED_259                 = 0x00000103,
13431  CB_PERF_SEL_RESERVED_260                 = 0x00000104,
13432  CB_PERF_SEL_RESERVED_261                 = 0x00000105,
13433  CB_PERF_SEL_RESERVED_262                 = 0x00000106,
13434  CB_PERF_SEL_RESERVED_263                 = 0x00000107,
13435  CB_PERF_SEL_RESERVED_264                 = 0x00000108,
13436  CB_PERF_SEL_RESERVED_265                 = 0x00000109,
13437  CB_PERF_SEL_RESERVED_266                 = 0x0000010a,
13438  CB_PERF_SEL_RESERVED_267                 = 0x0000010b,
13439  CB_PERF_SEL_RESERVED_268                 = 0x0000010c,
13440  CB_PERF_SEL_RESERVED_269                 = 0x0000010d,
13441  CB_PERF_SEL_RESERVED_270                 = 0x0000010e,
13442  CB_PERF_SEL_RESERVED_271                 = 0x0000010f,
13443  CB_PERF_SEL_RESERVED_272                 = 0x00000110,
13444  CB_PERF_SEL_RESERVED_273                 = 0x00000111,
13445  CB_PERF_SEL_RESERVED_274                 = 0x00000112,
13446  CB_PERF_SEL_RESERVED_275                 = 0x00000113,
13447  CB_PERF_SEL_RESERVED_276                 = 0x00000114,
13448  CB_PERF_SEL_RESERVED_277                 = 0x00000115,
13449  CB_PERF_SEL_RESERVED_278                 = 0x00000116,
13450  CB_PERF_SEL_RESERVED_279                 = 0x00000117,
13451  CB_PERF_SEL_RESERVED_280                 = 0x00000118,
13452  CB_PERF_SEL_RESERVED_281                 = 0x00000119,
13453  CB_PERF_SEL_RESERVED_282                 = 0x0000011a,
13454  CB_PERF_SEL_RESERVED_283                 = 0x0000011b,
13455  CB_PERF_SEL_RESERVED_284                 = 0x0000011c,
13456  CB_PERF_SEL_RESERVED_285                 = 0x0000011d,
13457  CB_PERF_SEL_RESERVED_286                 = 0x0000011e,
13458  CB_PERF_SEL_RESERVED_287                 = 0x0000011f,
13459  CB_PERF_SEL_RESERVED_288                 = 0x00000120,
13460  CB_PERF_SEL_RESERVED_289                 = 0x00000121,
13461  CB_PERF_SEL_RESERVED_290                 = 0x00000122,
13462  CB_PERF_SEL_RESERVED_291                 = 0x00000123,
13463  CB_PERF_SEL_RESERVED_292                 = 0x00000124,
13464  CB_PERF_SEL_RESERVED_293                 = 0x00000125,
13465  CB_PERF_SEL_RESERVED_294                 = 0x00000126,
13466  CB_PERF_SEL_RESERVED_295                 = 0x00000127,
13467  CB_PERF_SEL_RESERVED_296                 = 0x00000128,
13468  CB_PERF_SEL_RESERVED_297                 = 0x00000129,
13469  CB_PERF_SEL_RESERVED_298                 = 0x0000012a,
13470  CB_PERF_SEL_RESERVED_299                 = 0x0000012b,
13471  CB_PERF_SEL_NACK_CC_READ                 = 0x0000012c,
13472  CB_PERF_SEL_NACK_CC_WRITE                = 0x0000012d,
13473  CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT = 0x0000012e,
13474  CB_PERF_SEL_RESERVED_303                 = 0x0000012f,
13475  CB_PERF_SEL_RESERVED_304                 = 0x00000130,
13476  CB_PERF_SEL_RESERVED_305                 = 0x00000131,
13477  CB_PERF_SEL_RESERVED_306                 = 0x00000132,
13478  CB_PERF_SEL_RESERVED_307                 = 0x00000133,
13479  CB_PERF_SEL_RESERVED_308                 = 0x00000134,
13480  CB_PERF_SEL_RESERVED_309                 = 0x00000135,
13481  CB_PERF_SEL_RESERVED_310                 = 0x00000136,
13482  CB_PERF_SEL_RESERVED_311                 = 0x00000137,
13483  CB_PERF_SEL_RESERVED_312                 = 0x00000138,
13484  CB_PERF_SEL_RESERVED_313                 = 0x00000139,
13485  CB_PERF_SEL_RESERVED_314                 = 0x0000013a,
13486  CB_PERF_SEL_RESERVED_315                 = 0x0000013b,
13487  CB_PERF_SEL_RESERVED_316                 = 0x0000013c,
13488  CB_PERF_SEL_RESERVED_317                 = 0x0000013d,
13489  CB_PERF_SEL_RESERVED_318                 = 0x0000013e,
13490  CB_PERF_SEL_RESERVED_319                 = 0x0000013f,
13491  CB_PERF_SEL_RESERVED_320                 = 0x00000140,
13492  CB_PERF_SEL_RESERVED_321                 = 0x00000141,
13493  CB_PERF_SEL_RESERVED_322                 = 0x00000142,
13494  CB_PERF_SEL_RESERVED_323                 = 0x00000143,
13495  CB_PERF_SEL_RESERVED_324                 = 0x00000144,
13496  CB_PERF_SEL_RESERVED_325                 = 0x00000145,
13497  CB_PERF_SEL_RESERVED_326                 = 0x00000146,
13498  CB_PERF_SEL_RESERVED_327                 = 0x00000147,
13499  CB_PERF_SEL_RESERVED_328                 = 0x00000148,
13500  CB_PERF_SEL_RESERVED_329                 = 0x00000149,
13501  CB_PERF_SEL_RESERVED_330                 = 0x0000014a,
13502  CB_PERF_SEL_RESERVED_331                 = 0x0000014b,
13503  CB_PERF_SEL_RESERVED_332                 = 0x0000014c,
13504  CB_PERF_SEL_RESERVED_333                 = 0x0000014d,
13505  CB_PERF_SEL_RESERVED_334                 = 0x0000014e,
13506  CB_PERF_SEL_RESERVED_335                 = 0x0000014f,
13507  CB_PERF_SEL_RESERVED_336                 = 0x00000150,
13508  CB_PERF_SEL_RESERVED_337                 = 0x00000151,
13509  CB_PERF_SEL_RESERVED_338                 = 0x00000152,
13510  CB_PERF_SEL_RESERVED_339                 = 0x00000153,
13511  CB_PERF_SEL_RESERVED_340                 = 0x00000154,
13512  CB_PERF_SEL_RESERVED_341                 = 0x00000155,
13513  CB_PERF_SEL_RESERVED_342                 = 0x00000156,
13514  CB_PERF_SEL_RESERVED_343                 = 0x00000157,
13515  CB_PERF_SEL_RESERVED_344                 = 0x00000158,
13516  CB_PERF_SEL_RESERVED_345                 = 0x00000159,
13517  CB_PERF_SEL_RESERVED_346                 = 0x0000015a,
13518  CB_PERF_SEL_RESERVED_347                 = 0x0000015b,
13519  CB_PERF_SEL_RESERVED_348                 = 0x0000015c,
13520  CB_PERF_SEL_RESERVED_349                 = 0x0000015d,
13521  CB_PERF_SEL_RESERVED_350                 = 0x0000015e,
13522  CB_PERF_SEL_RESERVED_351                 = 0x0000015f,
13523  CB_PERF_SEL_RESERVED_352                 = 0x00000160,
13524  CB_PERF_SEL_RESERVED_353                 = 0x00000161,
13525  CB_PERF_SEL_RESERVED_354                 = 0x00000162,
13526  CB_PERF_SEL_RESERVED_355                 = 0x00000163,
13527  CB_PERF_SEL_RESERVED_356                 = 0x00000164,
13528  CB_PERF_SEL_RESERVED_357                 = 0x00000165,
13529  CB_PERF_SEL_RESERVED_358                 = 0x00000166,
13530  CB_PERF_SEL_RESERVED_359                 = 0x00000167,
13531  CB_PERF_SEL_RESERVED_360                 = 0x00000168,
13532  CB_PERF_SEL_RESERVED_361                 = 0x00000169,
13533  CB_PERF_SEL_RESERVED_362                 = 0x0000016a,
13534  CB_PERF_SEL_RESERVED_363                 = 0x0000016b,
13535  CB_PERF_SEL_RESERVED_364                 = 0x0000016c,
13536  CB_PERF_SEL_RESERVED_365                 = 0x0000016d,
13537  CB_PERF_SEL_RESERVED_366                 = 0x0000016e,
13538  CB_PERF_SEL_RESERVED_367                 = 0x0000016f,
13539  CB_PERF_SEL_RESERVED_368                 = 0x00000170,
13540  CB_PERF_SEL_RESERVED_369                 = 0x00000171,
13541  CB_PERF_SEL_RESERVED_370                 = 0x00000172,
13542  CB_PERF_SEL_RESERVED_371                 = 0x00000173,
13543  CB_PERF_SEL_RESERVED_372                 = 0x00000174,
13544  CB_PERF_SEL_RESERVED_373                 = 0x00000175,
13545  CB_PERF_SEL_RESERVED_374                 = 0x00000176,
13546  CB_PERF_SEL_RESERVED_375                 = 0x00000177,
13547  CB_PERF_SEL_RESERVED_376                 = 0x00000178,
13548  CB_PERF_SEL_RESERVED_377                 = 0x00000179,
13549  CB_PERF_SEL_RESERVED_378                 = 0x0000017a,
13550  CB_PERF_SEL_RESERVED_379                 = 0x0000017b,
13551  CB_PERF_SEL_RESERVED_380                 = 0x0000017c,
13552  CB_PERF_SEL_RESERVED_381                 = 0x0000017d,
13553  CB_PERF_SEL_RESERVED_382                 = 0x0000017e,
13554  CB_PERF_SEL_RESERVED_383                 = 0x0000017f,
13555  CB_PERF_SEL_RESERVED_384                 = 0x00000180,
13556  CB_PERF_SEL_RESERVED_385                 = 0x00000181,
13557  CB_PERF_SEL_RESERVED_386                 = 0x00000182,
13558  CB_PERF_SEL_RESERVED_387                 = 0x00000183,
13559  CB_PERF_SEL_RESERVED_388                 = 0x00000184,
13560  CB_PERF_SEL_RESERVED_389                 = 0x00000185,
13561  CB_PERF_SEL_RESERVED_390                 = 0x00000186,
13562  CB_PERF_SEL_RESERVED_391                 = 0x00000187,
13563  CB_PERF_SEL_RESERVED_392                 = 0x00000188,
13564  CB_PERF_SEL_RESERVED_393                 = 0x00000189,
13565  CB_PERF_SEL_RESERVED_394                 = 0x0000018a,
13566  CB_PERF_SEL_RESERVED_395                 = 0x0000018b,
13567  CB_PERF_SEL_RESERVED_396                 = 0x0000018c,
13568  CB_PERF_SEL_RESERVED_397                 = 0x0000018d,
13569  CB_PERF_SEL_RESERVED_398                 = 0x0000018e,
13570  CB_PERF_SEL_RESERVED_399                 = 0x0000018f,
13571  CB_PERF_SEL_RESERVED_400                 = 0x00000190,
13572  CB_PERF_SEL_RESERVED_401                 = 0x00000191,
13573  CB_PERF_SEL_RESERVED_402                 = 0x00000192,
13574  CB_PERF_SEL_RESERVED_403                 = 0x00000193,
13575  CB_PERF_SEL_RESERVED_404                 = 0x00000194,
13576  CB_PERF_SEL_RESERVED_405                 = 0x00000195,
13577  CB_PERF_SEL_RESERVED_406                 = 0x00000196,
13578  CB_PERF_SEL_RESERVED_407                 = 0x00000197,
13579  CB_PERF_SEL_RESERVED_408                 = 0x00000198,
13580  CB_PERF_SEL_RESERVED_409                 = 0x00000199,
13581  CB_PERF_SEL_RESERVED_410                 = 0x0000019a,
13582  CB_PERF_SEL_RESERVED_411                 = 0x0000019b,
13583  CB_PERF_SEL_RESERVED_412                 = 0x0000019c,
13584  CB_PERF_SEL_RESERVED_413                 = 0x0000019d,
13585  CB_PERF_SEL_RESERVED_414                 = 0x0000019e,
13586  CB_PERF_SEL_RESERVED_415                 = 0x0000019f,
13587  CB_PERF_SEL_RESERVED_416                 = 0x000001a0,
13588  CB_PERF_SEL_RESERVED_417                 = 0x000001a1,
13589  CB_PERF_SEL_RESERVED_418                 = 0x000001a2,
13590  CB_PERF_SEL_RESERVED_419                 = 0x000001a3,
13591  CB_PERF_SEL_RESERVED_420                 = 0x000001a4,
13592  CB_PERF_SEL_RESERVED_421                 = 0x000001a5,
13593  CB_PERF_SEL_RESERVED_422                 = 0x000001a6,
13594  CB_PERF_SEL_RESERVED_423                 = 0x000001a7,
13595  CB_PERF_SEL_RESERVED_424                 = 0x000001a8,
13596  CB_PERF_SEL_RESERVED_425                 = 0x000001a9,
13597  CB_PERF_SEL_RESERVED_426                 = 0x000001aa,
13598  CB_PERF_SEL_RESERVED_427                 = 0x000001ab,
13599  CB_PERF_SEL_RESERVED_428                 = 0x000001ac,
13600  CB_PERF_SEL_RESERVED_429                 = 0x000001ad,
13601  CB_PERF_SEL_RESERVED_430                 = 0x000001ae,
13602  CB_PERF_SEL_RESERVED_431                 = 0x000001af,
13603  CB_PERF_SEL_RESERVED_432                 = 0x000001b0,
13604  CB_PERF_SEL_RESERVED_433                 = 0x000001b1,
13605  CB_PERF_SEL_RESERVED_434                 = 0x000001b2,
13606  CB_PERF_SEL_RESERVED_435                 = 0x000001b3,
13607  CB_PERF_SEL_RESERVED_436                 = 0x000001b4,
13608  CB_PERF_SEL_RESERVED_437                 = 0x000001b5,
13609  CB_PERF_SEL_RESERVED_438                 = 0x000001b6,
13610  CB_PERF_SEL_RESERVED_439                 = 0x000001b7,
13611  CB_PERF_SEL_RESERVED_440                 = 0x000001b8,
13612  CB_PERF_SEL_RESERVED_441                 = 0x000001b9,
13613  CB_PERF_SEL_RESERVED_442                 = 0x000001ba,
13614  CB_PERF_SEL_RESERVED_443                 = 0x000001bb,
13615  CB_PERF_SEL_RESERVED_444                 = 0x000001bc,
13616  CB_PERF_SEL_RESERVED_445                 = 0x000001bd,
13617  CB_PERF_SEL_RESERVED_446                 = 0x000001be,
13618  CB_PERF_SEL_RESERVED_447                 = 0x000001bf,
13619  CB_PERF_SEL_RESERVED_448                 = 0x000001c0,
13620  CB_PERF_SEL_RESERVED_449                 = 0x000001c1,
13621  CB_PERF_SEL_RESERVED_450                 = 0x000001c2,
13622  CB_PERF_SEL_RESERVED_451                 = 0x000001c3,
13623  CB_PERF_SEL_RESERVED_452                 = 0x000001c4,
13624  CB_PERF_SEL_RESERVED_453                 = 0x000001c5,
13625  CB_PERF_SEL_RESERVED_454                 = 0x000001c6,
13626  CB_PERF_SEL_RESERVED_455                 = 0x000001c7,
13627  CB_PERF_SEL_RESERVED_456                 = 0x000001c8,
13628  CB_PERF_SEL_RESERVED_457                 = 0x000001c9,
13629  CB_PERF_SEL_RESERVED_458                 = 0x000001ca,
13630  CB_PERF_SEL_RESERVED_459                 = 0x000001cb,
13631  CB_PERF_SEL_RESERVED_460                 = 0x000001cc,
13632  CB_PERF_SEL_RESERVED_461                 = 0x000001cd,
13633  CB_PERF_SEL_RESERVED_462                 = 0x000001ce,
13634  CB_PERF_SEL_RESERVED_463                 = 0x000001cf,
13635  CB_PERF_SEL_RESERVED_464                 = 0x000001d0,
13636  CB_PERF_SEL_RESERVED_465                 = 0x000001d1,
13637  } CBPerfSel;
13638  
13639  /*
13640   * CBRamList enum
13641   */
13642  
13643  typedef enum CBRamList {
13644  CB_DCG_CCC_CAS_TAG_ARRAY                 = 0x00000000,
13645  CB_DCG_CCC_CAS_FRAG_PTR                  = 0x00000001,
13646  CB_DCG_CCC_CAS_COLOR_PTR                 = 0x00000002,
13647  CB_DCG_CCC_CAS_SURF_PARAM                = 0x00000003,
13648  CB_DCG_CCC_CAS_KEYID                     = 0x00000004,
13649  CB_DCG_BACKEND_RDLAT_FIFO                = 0x00000005,
13650  CB_DCG_FRONTEND_RDLAT_FIFO               = 0x00000006,
13651  CB_DCG_SRC_FIFO                          = 0x00000007,
13652  CB_DCG_COLOR_STORE                       = 0x00000008,
13653  CB_DCG_COLOR_STORE_DIRTY_BYTE            = 0x00000009,
13654  CB_DCG_FMASK_CACHE_STORE                 = 0x0000000a,
13655  CB_DCG_READ_SKID_FIFO                    = 0x0000000b,
13656  CB_DCG_QUAD_PTR_FIFO                     = 0x0000000c,
13657  CB_DCG_OUTPUT_FIFO                       = 0x0000000d,
13658  CB_DCG_DCC_CACHE                         = 0x0000000e,
13659  CB_DCG_DCC_DIRTY_BITS                    = 0x0000000f,
13660  CB_DCG_QBLOCK_ALLOC                      = 0x00000010,
13661  } CBRamList;
13662  
13663  /*
13664   * CmaskCode enum
13665   */
13666  
13667  typedef enum CmaskCode {
13668  CMASK_CLR00_F0                           = 0x00000000,
13669  CMASK_CLR00_F1                           = 0x00000001,
13670  CMASK_CLR00_F2                           = 0x00000002,
13671  CMASK_CLR00_FX                           = 0x00000003,
13672  CMASK_CLR01_F0                           = 0x00000004,
13673  CMASK_CLR01_F1                           = 0x00000005,
13674  CMASK_CLR01_F2                           = 0x00000006,
13675  CMASK_CLR01_FX                           = 0x00000007,
13676  CMASK_CLR10_F0                           = 0x00000008,
13677  CMASK_CLR10_F1                           = 0x00000009,
13678  CMASK_CLR10_F2                           = 0x0000000a,
13679  CMASK_CLR10_FX                           = 0x0000000b,
13680  CMASK_CLR11_F0                           = 0x0000000c,
13681  CMASK_CLR11_F1                           = 0x0000000d,
13682  CMASK_CLR11_F2                           = 0x0000000e,
13683  CMASK_CLR11_FX                           = 0x0000000f,
13684  } CmaskCode;
13685  
13686  /*
13687   * CombFunc enum
13688   */
13689  
13690  typedef enum CombFunc {
13691  COMB_DST_PLUS_SRC                        = 0x00000000,
13692  COMB_SRC_MINUS_DST                       = 0x00000001,
13693  COMB_MIN_DST_SRC                         = 0x00000002,
13694  COMB_MAX_DST_SRC                         = 0x00000003,
13695  COMB_DST_MINUS_SRC                       = 0x00000004,
13696  } CombFunc;
13697  
13698  /*
13699   * MemArbMode enum
13700   */
13701  
13702  typedef enum MemArbMode {
13703  MEM_ARB_MODE_FIXED                       = 0x00000000,
13704  MEM_ARB_MODE_AGE                         = 0x00000001,
13705  MEM_ARB_MODE_WEIGHT                      = 0x00000002,
13706  MEM_ARB_MODE_BOTH                        = 0x00000003,
13707  } MemArbMode;
13708  
13709  /*
13710   * SourceFormat enum
13711   */
13712  
13713  typedef enum SourceFormat {
13714  EXPORT_4C_32BPC                          = 0x00000000,
13715  EXPORT_4C_16BPC                          = 0x00000001,
13716  EXPORT_2C_32BPC_GR                       = 0x00000002,
13717  EXPORT_2C_32BPC_AR                       = 0x00000003,
13718  } SourceFormat;
13719  
13720  /*******************************************************
13721   * SC Enums
13722   *******************************************************/
13723  
13724  /*
13725   * BinEventCntl enum
13726   */
13727  
13728  typedef enum BinEventCntl {
13729  BINNER_BREAK_BATCH                       = 0x00000000,
13730  BINNER_PIPELINE                          = 0x00000001,
13731  BINNER_DROP                              = 0x00000002,
13732  BINNER_PIPELINE_BREAK                    = 0x00000003,
13733  } BinEventCntl;
13734  
13735  /*
13736   * BinMapMode enum
13737   */
13738  
13739  typedef enum BinMapMode {
13740  BIN_MAP_MODE_NONE                        = 0x00000000,
13741  BIN_MAP_MODE_RTA_INDEX                   = 0x00000001,
13742  BIN_MAP_MODE_POPS                        = 0x00000002,
13743  } BinMapMode;
13744  
13745  /*
13746   * BinSizeExtend enum
13747   */
13748  
13749  typedef enum BinSizeExtend {
13750  BIN_SIZE_32_PIXELS                       = 0x00000000,
13751  BIN_SIZE_64_PIXELS                       = 0x00000001,
13752  BIN_SIZE_128_PIXELS                      = 0x00000002,
13753  BIN_SIZE_256_PIXELS                      = 0x00000003,
13754  BIN_SIZE_512_PIXELS                      = 0x00000004,
13755  } BinSizeExtend;
13756  
13757  /*
13758   * BinningMode enum
13759   */
13760  
13761  typedef enum BinningMode {
13762  BINNING_ALLOWED                          = 0x00000000,
13763  FORCE_BINNING_ON                         = 0x00000001,
13764  DISABLE_BINNING_USE_NEW_SC               = 0x00000002,
13765  DISABLE_BINNING_USE_LEGACY_SC            = 0x00000003,
13766  } BinningMode;
13767  
13768  /*
13769   * CovToShaderSel enum
13770   */
13771  
13772  typedef enum CovToShaderSel {
13773  INPUT_COVERAGE                           = 0x00000000,
13774  INPUT_INNER_COVERAGE                     = 0x00000001,
13775  INPUT_DEPTH_COVERAGE                     = 0x00000002,
13776  RAW                                      = 0x00000003,
13777  } CovToShaderSel;
13778  
13779  /*
13780   * PkrMap enum
13781   */
13782  
13783  typedef enum PkrMap {
13784  RASTER_CONFIG_PKR_MAP_0                  = 0x00000000,
13785  RASTER_CONFIG_PKR_MAP_1                  = 0x00000001,
13786  RASTER_CONFIG_PKR_MAP_2                  = 0x00000002,
13787  RASTER_CONFIG_PKR_MAP_3                  = 0x00000003,
13788  } PkrMap;
13789  
13790  /*
13791   * PkrXsel enum
13792   */
13793  
13794  typedef enum PkrXsel {
13795  RASTER_CONFIG_PKR_XSEL_0                 = 0x00000000,
13796  RASTER_CONFIG_PKR_XSEL_1                 = 0x00000001,
13797  RASTER_CONFIG_PKR_XSEL_2                 = 0x00000002,
13798  RASTER_CONFIG_PKR_XSEL_3                 = 0x00000003,
13799  } PkrXsel;
13800  
13801  /*
13802   * PkrXsel2 enum
13803   */
13804  
13805  typedef enum PkrXsel2 {
13806  RASTER_CONFIG_PKR_XSEL2_0                = 0x00000000,
13807  RASTER_CONFIG_PKR_XSEL2_1                = 0x00000001,
13808  RASTER_CONFIG_PKR_XSEL2_2                = 0x00000002,
13809  RASTER_CONFIG_PKR_XSEL2_3                = 0x00000003,
13810  } PkrXsel2;
13811  
13812  /*
13813   * PkrYsel enum
13814   */
13815  
13816  typedef enum PkrYsel {
13817  RASTER_CONFIG_PKR_YSEL_0                 = 0x00000000,
13818  RASTER_CONFIG_PKR_YSEL_1                 = 0x00000001,
13819  RASTER_CONFIG_PKR_YSEL_2                 = 0x00000002,
13820  RASTER_CONFIG_PKR_YSEL_3                 = 0x00000003,
13821  } PkrYsel;
13822  
13823  /*
13824   * RbMap enum
13825   */
13826  
13827  typedef enum RbMap {
13828  RASTER_CONFIG_RB_MAP_0                   = 0x00000000,
13829  RASTER_CONFIG_RB_MAP_1                   = 0x00000001,
13830  RASTER_CONFIG_RB_MAP_2                   = 0x00000002,
13831  RASTER_CONFIG_RB_MAP_3                   = 0x00000003,
13832  } RbMap;
13833  
13834  /*
13835   * RbXsel enum
13836   */
13837  
13838  typedef enum RbXsel {
13839  RASTER_CONFIG_RB_XSEL_0                  = 0x00000000,
13840  RASTER_CONFIG_RB_XSEL_1                  = 0x00000001,
13841  } RbXsel;
13842  
13843  /*
13844   * RbXsel2 enum
13845   */
13846  
13847  typedef enum RbXsel2 {
13848  RASTER_CONFIG_RB_XSEL2_0                 = 0x00000000,
13849  RASTER_CONFIG_RB_XSEL2_1                 = 0x00000001,
13850  RASTER_CONFIG_RB_XSEL2_2                 = 0x00000002,
13851  RASTER_CONFIG_RB_XSEL2_3                 = 0x00000003,
13852  } RbXsel2;
13853  
13854  /*
13855   * RbYsel enum
13856   */
13857  
13858  typedef enum RbYsel {
13859  RASTER_CONFIG_RB_YSEL_0                  = 0x00000000,
13860  RASTER_CONFIG_RB_YSEL_1                  = 0x00000001,
13861  } RbYsel;
13862  
13863  /*
13864   * SC_PERFCNT_SEL enum
13865   */
13866  
13867  typedef enum SC_PERFCNT_SEL {
13868  SC_SRPS_WINDOW_VALID                     = 0x00000000,
13869  SC_PSSW_WINDOW_VALID                     = 0x00000001,
13870  SC_TPQZ_WINDOW_VALID                     = 0x00000002,
13871  SC_QZQP_WINDOW_VALID                     = 0x00000003,
13872  SC_TRPK_WINDOW_VALID                     = 0x00000004,
13873  SC_SRPS_WINDOW_VALID_BUSY                = 0x00000005,
13874  SC_PSSW_WINDOW_VALID_BUSY                = 0x00000006,
13875  SC_TPQZ_WINDOW_VALID_BUSY                = 0x00000007,
13876  SC_QZQP_WINDOW_VALID_BUSY                = 0x00000008,
13877  SC_TRPK_WINDOW_VALID_BUSY                = 0x00000009,
13878  SC_STARVED_BY_PA                         = 0x0000000a,
13879  SC_STALLED_BY_PRIMFIFO                   = 0x0000000b,
13880  SC_STALLED_BY_DB_TILE                    = 0x0000000c,
13881  SC_STARVED_BY_DB_TILE                    = 0x0000000d,
13882  SC_STALLED_BY_TILEORDERFIFO              = 0x0000000e,
13883  SC_STALLED_BY_TILEFIFO                   = 0x0000000f,
13884  SC_STALLED_BY_DB_QUAD                    = 0x00000010,
13885  SC_STARVED_BY_DB_QUAD                    = 0x00000011,
13886  SC_STALLED_BY_QUADFIFO                   = 0x00000012,
13887  SC_STALLED_BY_BCI                        = 0x00000013,
13888  SC_STALLED_BY_SPI                        = 0x00000014,
13889  SC_SCISSOR_DISCARD                       = 0x00000015,
13890  SC_BB_DISCARD                            = 0x00000016,
13891  SC_SUPERTILE_COUNT                       = 0x00000017,
13892  SC_SUPERTILE_PER_PRIM_H0                 = 0x00000018,
13893  SC_SUPERTILE_PER_PRIM_H1                 = 0x00000019,
13894  SC_SUPERTILE_PER_PRIM_H2                 = 0x0000001a,
13895  SC_SUPERTILE_PER_PRIM_H3                 = 0x0000001b,
13896  SC_SUPERTILE_PER_PRIM_H4                 = 0x0000001c,
13897  SC_SUPERTILE_PER_PRIM_H5                 = 0x0000001d,
13898  SC_SUPERTILE_PER_PRIM_H6                 = 0x0000001e,
13899  SC_SUPERTILE_PER_PRIM_H7                 = 0x0000001f,
13900  SC_SUPERTILE_PER_PRIM_H8                 = 0x00000020,
13901  SC_SUPERTILE_PER_PRIM_H9                 = 0x00000021,
13902  SC_SUPERTILE_PER_PRIM_H10                = 0x00000022,
13903  SC_SUPERTILE_PER_PRIM_H11                = 0x00000023,
13904  SC_SUPERTILE_PER_PRIM_H12                = 0x00000024,
13905  SC_SUPERTILE_PER_PRIM_H13                = 0x00000025,
13906  SC_SUPERTILE_PER_PRIM_H14                = 0x00000026,
13907  SC_SUPERTILE_PER_PRIM_H15                = 0x00000027,
13908  SC_SUPERTILE_PER_PRIM_H16                = 0x00000028,
13909  SC_TILE_PER_PRIM_H0                      = 0x00000029,
13910  SC_TILE_PER_PRIM_H1                      = 0x0000002a,
13911  SC_TILE_PER_PRIM_H2                      = 0x0000002b,
13912  SC_TILE_PER_PRIM_H3                      = 0x0000002c,
13913  SC_TILE_PER_PRIM_H4                      = 0x0000002d,
13914  SC_TILE_PER_PRIM_H5                      = 0x0000002e,
13915  SC_TILE_PER_PRIM_H6                      = 0x0000002f,
13916  SC_TILE_PER_PRIM_H7                      = 0x00000030,
13917  SC_TILE_PER_PRIM_H8                      = 0x00000031,
13918  SC_TILE_PER_PRIM_H9                      = 0x00000032,
13919  SC_TILE_PER_PRIM_H10                     = 0x00000033,
13920  SC_TILE_PER_PRIM_H11                     = 0x00000034,
13921  SC_TILE_PER_PRIM_H12                     = 0x00000035,
13922  SC_TILE_PER_PRIM_H13                     = 0x00000036,
13923  SC_TILE_PER_PRIM_H14                     = 0x00000037,
13924  SC_TILE_PER_PRIM_H15                     = 0x00000038,
13925  SC_TILE_PER_PRIM_H16                     = 0x00000039,
13926  SC_TILE_PER_SUPERTILE_H0                 = 0x0000003a,
13927  SC_TILE_PER_SUPERTILE_H1                 = 0x0000003b,
13928  SC_TILE_PER_SUPERTILE_H2                 = 0x0000003c,
13929  SC_TILE_PER_SUPERTILE_H3                 = 0x0000003d,
13930  SC_TILE_PER_SUPERTILE_H4                 = 0x0000003e,
13931  SC_TILE_PER_SUPERTILE_H5                 = 0x0000003f,
13932  SC_TILE_PER_SUPERTILE_H6                 = 0x00000040,
13933  SC_TILE_PER_SUPERTILE_H7                 = 0x00000041,
13934  SC_TILE_PER_SUPERTILE_H8                 = 0x00000042,
13935  SC_TILE_PER_SUPERTILE_H9                 = 0x00000043,
13936  SC_TILE_PER_SUPERTILE_H10                = 0x00000044,
13937  SC_TILE_PER_SUPERTILE_H11                = 0x00000045,
13938  SC_TILE_PER_SUPERTILE_H12                = 0x00000046,
13939  SC_TILE_PER_SUPERTILE_H13                = 0x00000047,
13940  SC_TILE_PER_SUPERTILE_H14                = 0x00000048,
13941  SC_TILE_PER_SUPERTILE_H15                = 0x00000049,
13942  SC_TILE_PER_SUPERTILE_H16                = 0x0000004a,
13943  SC_TILE_PICKED_H1                        = 0x0000004b,
13944  SC_TILE_PICKED_H2                        = 0x0000004c,
13945  SC_TILE_PICKED_H3                        = 0x0000004d,
13946  SC_TILE_PICKED_H4                        = 0x0000004e,
13947  SC_QZ0_TILE_COUNT                        = 0x0000004f,
13948  SC_QZ1_TILE_COUNT                        = 0x00000050,
13949  SC_QZ2_TILE_COUNT                        = 0x00000051,
13950  SC_QZ3_TILE_COUNT                        = 0x00000052,
13951  SC_QZ0_TILE_COVERED_COUNT                = 0x00000053,
13952  SC_QZ1_TILE_COVERED_COUNT                = 0x00000054,
13953  SC_QZ2_TILE_COVERED_COUNT                = 0x00000055,
13954  SC_QZ3_TILE_COVERED_COUNT                = 0x00000056,
13955  SC_QZ0_TILE_NOT_COVERED_COUNT            = 0x00000057,
13956  SC_QZ1_TILE_NOT_COVERED_COUNT            = 0x00000058,
13957  SC_QZ2_TILE_NOT_COVERED_COUNT            = 0x00000059,
13958  SC_QZ3_TILE_NOT_COVERED_COUNT            = 0x0000005a,
13959  SC_QZ0_QUAD_PER_TILE_H0                  = 0x0000005b,
13960  SC_QZ0_QUAD_PER_TILE_H1                  = 0x0000005c,
13961  SC_QZ0_QUAD_PER_TILE_H2                  = 0x0000005d,
13962  SC_QZ0_QUAD_PER_TILE_H3                  = 0x0000005e,
13963  SC_QZ0_QUAD_PER_TILE_H4                  = 0x0000005f,
13964  SC_QZ0_QUAD_PER_TILE_H5                  = 0x00000060,
13965  SC_QZ0_QUAD_PER_TILE_H6                  = 0x00000061,
13966  SC_QZ0_QUAD_PER_TILE_H7                  = 0x00000062,
13967  SC_QZ0_QUAD_PER_TILE_H8                  = 0x00000063,
13968  SC_QZ0_QUAD_PER_TILE_H9                  = 0x00000064,
13969  SC_QZ0_QUAD_PER_TILE_H10                 = 0x00000065,
13970  SC_QZ0_QUAD_PER_TILE_H11                 = 0x00000066,
13971  SC_QZ0_QUAD_PER_TILE_H12                 = 0x00000067,
13972  SC_QZ0_QUAD_PER_TILE_H13                 = 0x00000068,
13973  SC_QZ0_QUAD_PER_TILE_H14                 = 0x00000069,
13974  SC_QZ0_QUAD_PER_TILE_H15                 = 0x0000006a,
13975  SC_QZ0_QUAD_PER_TILE_H16                 = 0x0000006b,
13976  SC_QZ1_QUAD_PER_TILE_H0                  = 0x0000006c,
13977  SC_QZ1_QUAD_PER_TILE_H1                  = 0x0000006d,
13978  SC_QZ1_QUAD_PER_TILE_H2                  = 0x0000006e,
13979  SC_QZ1_QUAD_PER_TILE_H3                  = 0x0000006f,
13980  SC_QZ1_QUAD_PER_TILE_H4                  = 0x00000070,
13981  SC_QZ1_QUAD_PER_TILE_H5                  = 0x00000071,
13982  SC_QZ1_QUAD_PER_TILE_H6                  = 0x00000072,
13983  SC_QZ1_QUAD_PER_TILE_H7                  = 0x00000073,
13984  SC_QZ1_QUAD_PER_TILE_H8                  = 0x00000074,
13985  SC_QZ1_QUAD_PER_TILE_H9                  = 0x00000075,
13986  SC_QZ1_QUAD_PER_TILE_H10                 = 0x00000076,
13987  SC_QZ1_QUAD_PER_TILE_H11                 = 0x00000077,
13988  SC_QZ1_QUAD_PER_TILE_H12                 = 0x00000078,
13989  SC_QZ1_QUAD_PER_TILE_H13                 = 0x00000079,
13990  SC_QZ1_QUAD_PER_TILE_H14                 = 0x0000007a,
13991  SC_QZ1_QUAD_PER_TILE_H15                 = 0x0000007b,
13992  SC_QZ1_QUAD_PER_TILE_H16                 = 0x0000007c,
13993  SC_QZ2_QUAD_PER_TILE_H0                  = 0x0000007d,
13994  SC_QZ2_QUAD_PER_TILE_H1                  = 0x0000007e,
13995  SC_QZ2_QUAD_PER_TILE_H2                  = 0x0000007f,
13996  SC_QZ2_QUAD_PER_TILE_H3                  = 0x00000080,
13997  SC_QZ2_QUAD_PER_TILE_H4                  = 0x00000081,
13998  SC_QZ2_QUAD_PER_TILE_H5                  = 0x00000082,
13999  SC_QZ2_QUAD_PER_TILE_H6                  = 0x00000083,
14000  SC_QZ2_QUAD_PER_TILE_H7                  = 0x00000084,
14001  SC_QZ2_QUAD_PER_TILE_H8                  = 0x00000085,
14002  SC_QZ2_QUAD_PER_TILE_H9                  = 0x00000086,
14003  SC_QZ2_QUAD_PER_TILE_H10                 = 0x00000087,
14004  SC_QZ2_QUAD_PER_TILE_H11                 = 0x00000088,
14005  SC_QZ2_QUAD_PER_TILE_H12                 = 0x00000089,
14006  SC_QZ2_QUAD_PER_TILE_H13                 = 0x0000008a,
14007  SC_QZ2_QUAD_PER_TILE_H14                 = 0x0000008b,
14008  SC_QZ2_QUAD_PER_TILE_H15                 = 0x0000008c,
14009  SC_QZ2_QUAD_PER_TILE_H16                 = 0x0000008d,
14010  SC_QZ3_QUAD_PER_TILE_H0                  = 0x0000008e,
14011  SC_QZ3_QUAD_PER_TILE_H1                  = 0x0000008f,
14012  SC_QZ3_QUAD_PER_TILE_H2                  = 0x00000090,
14013  SC_QZ3_QUAD_PER_TILE_H3                  = 0x00000091,
14014  SC_QZ3_QUAD_PER_TILE_H4                  = 0x00000092,
14015  SC_QZ3_QUAD_PER_TILE_H5                  = 0x00000093,
14016  SC_QZ3_QUAD_PER_TILE_H6                  = 0x00000094,
14017  SC_QZ3_QUAD_PER_TILE_H7                  = 0x00000095,
14018  SC_QZ3_QUAD_PER_TILE_H8                  = 0x00000096,
14019  SC_QZ3_QUAD_PER_TILE_H9                  = 0x00000097,
14020  SC_QZ3_QUAD_PER_TILE_H10                 = 0x00000098,
14021  SC_QZ3_QUAD_PER_TILE_H11                 = 0x00000099,
14022  SC_QZ3_QUAD_PER_TILE_H12                 = 0x0000009a,
14023  SC_QZ3_QUAD_PER_TILE_H13                 = 0x0000009b,
14024  SC_QZ3_QUAD_PER_TILE_H14                 = 0x0000009c,
14025  SC_QZ3_QUAD_PER_TILE_H15                 = 0x0000009d,
14026  SC_QZ3_QUAD_PER_TILE_H16                 = 0x0000009e,
14027  SC_QZ0_QUAD_COUNT                        = 0x0000009f,
14028  SC_QZ1_QUAD_COUNT                        = 0x000000a0,
14029  SC_QZ2_QUAD_COUNT                        = 0x000000a1,
14030  SC_QZ3_QUAD_COUNT                        = 0x000000a2,
14031  SC_P0_HIZ_TILE_COUNT                     = 0x000000a3,
14032  SC_P1_HIZ_TILE_COUNT                     = 0x000000a4,
14033  SC_P2_HIZ_TILE_COUNT                     = 0x000000a5,
14034  SC_P3_HIZ_TILE_COUNT                     = 0x000000a6,
14035  SC_P0_HIZ_QUAD_PER_TILE_H0               = 0x000000a7,
14036  SC_P0_HIZ_QUAD_PER_TILE_H1               = 0x000000a8,
14037  SC_P0_HIZ_QUAD_PER_TILE_H2               = 0x000000a9,
14038  SC_P0_HIZ_QUAD_PER_TILE_H3               = 0x000000aa,
14039  SC_P0_HIZ_QUAD_PER_TILE_H4               = 0x000000ab,
14040  SC_P0_HIZ_QUAD_PER_TILE_H5               = 0x000000ac,
14041  SC_P0_HIZ_QUAD_PER_TILE_H6               = 0x000000ad,
14042  SC_P0_HIZ_QUAD_PER_TILE_H7               = 0x000000ae,
14043  SC_P0_HIZ_QUAD_PER_TILE_H8               = 0x000000af,
14044  SC_P0_HIZ_QUAD_PER_TILE_H9               = 0x000000b0,
14045  SC_P0_HIZ_QUAD_PER_TILE_H10              = 0x000000b1,
14046  SC_P0_HIZ_QUAD_PER_TILE_H11              = 0x000000b2,
14047  SC_P0_HIZ_QUAD_PER_TILE_H12              = 0x000000b3,
14048  SC_P0_HIZ_QUAD_PER_TILE_H13              = 0x000000b4,
14049  SC_P0_HIZ_QUAD_PER_TILE_H14              = 0x000000b5,
14050  SC_P0_HIZ_QUAD_PER_TILE_H15              = 0x000000b6,
14051  SC_P0_HIZ_QUAD_PER_TILE_H16              = 0x000000b7,
14052  SC_P1_HIZ_QUAD_PER_TILE_H0               = 0x000000b8,
14053  SC_P1_HIZ_QUAD_PER_TILE_H1               = 0x000000b9,
14054  SC_P1_HIZ_QUAD_PER_TILE_H2               = 0x000000ba,
14055  SC_P1_HIZ_QUAD_PER_TILE_H3               = 0x000000bb,
14056  SC_P1_HIZ_QUAD_PER_TILE_H4               = 0x000000bc,
14057  SC_P1_HIZ_QUAD_PER_TILE_H5               = 0x000000bd,
14058  SC_P1_HIZ_QUAD_PER_TILE_H6               = 0x000000be,
14059  SC_P1_HIZ_QUAD_PER_TILE_H7               = 0x000000bf,
14060  SC_P1_HIZ_QUAD_PER_TILE_H8               = 0x000000c0,
14061  SC_P1_HIZ_QUAD_PER_TILE_H9               = 0x000000c1,
14062  SC_P1_HIZ_QUAD_PER_TILE_H10              = 0x000000c2,
14063  SC_P1_HIZ_QUAD_PER_TILE_H11              = 0x000000c3,
14064  SC_P1_HIZ_QUAD_PER_TILE_H12              = 0x000000c4,
14065  SC_P1_HIZ_QUAD_PER_TILE_H13              = 0x000000c5,
14066  SC_P1_HIZ_QUAD_PER_TILE_H14              = 0x000000c6,
14067  SC_P1_HIZ_QUAD_PER_TILE_H15              = 0x000000c7,
14068  SC_P1_HIZ_QUAD_PER_TILE_H16              = 0x000000c8,
14069  SC_P2_HIZ_QUAD_PER_TILE_H0               = 0x000000c9,
14070  SC_P2_HIZ_QUAD_PER_TILE_H1               = 0x000000ca,
14071  SC_P2_HIZ_QUAD_PER_TILE_H2               = 0x000000cb,
14072  SC_P2_HIZ_QUAD_PER_TILE_H3               = 0x000000cc,
14073  SC_P2_HIZ_QUAD_PER_TILE_H4               = 0x000000cd,
14074  SC_P2_HIZ_QUAD_PER_TILE_H5               = 0x000000ce,
14075  SC_P2_HIZ_QUAD_PER_TILE_H6               = 0x000000cf,
14076  SC_P2_HIZ_QUAD_PER_TILE_H7               = 0x000000d0,
14077  SC_P2_HIZ_QUAD_PER_TILE_H8               = 0x000000d1,
14078  SC_P2_HIZ_QUAD_PER_TILE_H9               = 0x000000d2,
14079  SC_P2_HIZ_QUAD_PER_TILE_H10              = 0x000000d3,
14080  SC_P2_HIZ_QUAD_PER_TILE_H11              = 0x000000d4,
14081  SC_P2_HIZ_QUAD_PER_TILE_H12              = 0x000000d5,
14082  SC_P2_HIZ_QUAD_PER_TILE_H13              = 0x000000d6,
14083  SC_P2_HIZ_QUAD_PER_TILE_H14              = 0x000000d7,
14084  SC_P2_HIZ_QUAD_PER_TILE_H15              = 0x000000d8,
14085  SC_P2_HIZ_QUAD_PER_TILE_H16              = 0x000000d9,
14086  SC_P3_HIZ_QUAD_PER_TILE_H0               = 0x000000da,
14087  SC_P3_HIZ_QUAD_PER_TILE_H1               = 0x000000db,
14088  SC_P3_HIZ_QUAD_PER_TILE_H2               = 0x000000dc,
14089  SC_P3_HIZ_QUAD_PER_TILE_H3               = 0x000000dd,
14090  SC_P3_HIZ_QUAD_PER_TILE_H4               = 0x000000de,
14091  SC_P3_HIZ_QUAD_PER_TILE_H5               = 0x000000df,
14092  SC_P3_HIZ_QUAD_PER_TILE_H6               = 0x000000e0,
14093  SC_P3_HIZ_QUAD_PER_TILE_H7               = 0x000000e1,
14094  SC_P3_HIZ_QUAD_PER_TILE_H8               = 0x000000e2,
14095  SC_P3_HIZ_QUAD_PER_TILE_H9               = 0x000000e3,
14096  SC_P3_HIZ_QUAD_PER_TILE_H10              = 0x000000e4,
14097  SC_P3_HIZ_QUAD_PER_TILE_H11              = 0x000000e5,
14098  SC_P3_HIZ_QUAD_PER_TILE_H12              = 0x000000e6,
14099  SC_P3_HIZ_QUAD_PER_TILE_H13              = 0x000000e7,
14100  SC_P3_HIZ_QUAD_PER_TILE_H14              = 0x000000e8,
14101  SC_P3_HIZ_QUAD_PER_TILE_H15              = 0x000000e9,
14102  SC_P3_HIZ_QUAD_PER_TILE_H16              = 0x000000ea,
14103  SC_P0_HIZ_QUAD_COUNT                     = 0x000000eb,
14104  SC_P1_HIZ_QUAD_COUNT                     = 0x000000ec,
14105  SC_P2_HIZ_QUAD_COUNT                     = 0x000000ed,
14106  SC_P3_HIZ_QUAD_COUNT                     = 0x000000ee,
14107  SC_P0_DETAIL_QUAD_COUNT                  = 0x000000ef,
14108  SC_P1_DETAIL_QUAD_COUNT                  = 0x000000f0,
14109  SC_P2_DETAIL_QUAD_COUNT                  = 0x000000f1,
14110  SC_P3_DETAIL_QUAD_COUNT                  = 0x000000f2,
14111  SC_P0_DETAIL_QUAD_WITH_1_PIX             = 0x000000f3,
14112  SC_P0_DETAIL_QUAD_WITH_2_PIX             = 0x000000f4,
14113  SC_P0_DETAIL_QUAD_WITH_3_PIX             = 0x000000f5,
14114  SC_P0_DETAIL_QUAD_WITH_4_PIX             = 0x000000f6,
14115  SC_P1_DETAIL_QUAD_WITH_1_PIX             = 0x000000f7,
14116  SC_P1_DETAIL_QUAD_WITH_2_PIX             = 0x000000f8,
14117  SC_P1_DETAIL_QUAD_WITH_3_PIX             = 0x000000f9,
14118  SC_P1_DETAIL_QUAD_WITH_4_PIX             = 0x000000fa,
14119  SC_P2_DETAIL_QUAD_WITH_1_PIX             = 0x000000fb,
14120  SC_P2_DETAIL_QUAD_WITH_2_PIX             = 0x000000fc,
14121  SC_P2_DETAIL_QUAD_WITH_3_PIX             = 0x000000fd,
14122  SC_P2_DETAIL_QUAD_WITH_4_PIX             = 0x000000fe,
14123  SC_P3_DETAIL_QUAD_WITH_1_PIX             = 0x000000ff,
14124  SC_P3_DETAIL_QUAD_WITH_2_PIX             = 0x00000100,
14125  SC_P3_DETAIL_QUAD_WITH_3_PIX             = 0x00000101,
14126  SC_P3_DETAIL_QUAD_WITH_4_PIX             = 0x00000102,
14127  SC_EARLYZ_QUAD_COUNT                     = 0x00000103,
14128  SC_EARLYZ_QUAD_WITH_1_PIX                = 0x00000104,
14129  SC_EARLYZ_QUAD_WITH_2_PIX                = 0x00000105,
14130  SC_EARLYZ_QUAD_WITH_3_PIX                = 0x00000106,
14131  SC_EARLYZ_QUAD_WITH_4_PIX                = 0x00000107,
14132  SC_PKR_QUAD_PER_ROW_H1                   = 0x00000108,
14133  SC_PKR_QUAD_PER_ROW_H2                   = 0x00000109,
14134  SC_PKR_4X2_QUAD_SPLIT                    = 0x0000010a,
14135  SC_PKR_4X2_FILL_QUAD                     = 0x0000010b,
14136  SC_PKR_END_OF_VECTOR                     = 0x0000010c,
14137  SC_PKR_CONTROL_XFER                      = 0x0000010d,
14138  SC_PKR_DBHANG_FORCE_EOV                  = 0x0000010e,
14139  SC_REG_SCLK_BUSY                         = 0x0000010f,
14140  SC_GRP0_DYN_SCLK_BUSY                    = 0x00000110,
14141  SC_GRP1_DYN_SCLK_BUSY                    = 0x00000111,
14142  SC_GRP2_DYN_SCLK_BUSY                    = 0x00000112,
14143  SC_GRP3_DYN_SCLK_BUSY                    = 0x00000113,
14144  SC_GRP4_DYN_SCLK_BUSY                    = 0x00000114,
14145  SC_PA0_SC_DATA_FIFO_RD                   = 0x00000115,
14146  SC_PA0_SC_DATA_FIFO_WE                   = 0x00000116,
14147  SC_PA1_SC_DATA_FIFO_RD                   = 0x00000117,
14148  SC_PA1_SC_DATA_FIFO_WE                   = 0x00000118,
14149  SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES   = 0x00000119,
14150  SC_PS_ARB_XFC_ONLY_PRIM_CYCLES           = 0x0000011a,
14151  SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM      = 0x0000011b,
14152  SC_PS_ARB_STALLED_FROM_BELOW             = 0x0000011c,
14153  SC_PS_ARB_STARVED_FROM_ABOVE             = 0x0000011d,
14154  SC_PS_ARB_SC_BUSY                        = 0x0000011e,
14155  SC_PS_ARB_PA_SC_BUSY                     = 0x0000011f,
14156  SC_PA2_SC_DATA_FIFO_RD                   = 0x00000120,
14157  SC_PA2_SC_DATA_FIFO_WE                   = 0x00000121,
14158  SC_PA3_SC_DATA_FIFO_RD                   = 0x00000122,
14159  SC_PA3_SC_DATA_FIFO_WE                   = 0x00000123,
14160  SC_PA_SC_DEALLOC_0_0_WE                  = 0x00000124,
14161  SC_PA_SC_DEALLOC_0_1_WE                  = 0x00000125,
14162  SC_PA_SC_DEALLOC_1_0_WE                  = 0x00000126,
14163  SC_PA_SC_DEALLOC_1_1_WE                  = 0x00000127,
14164  SC_PA_SC_DEALLOC_2_0_WE                  = 0x00000128,
14165  SC_PA_SC_DEALLOC_2_1_WE                  = 0x00000129,
14166  SC_PA_SC_DEALLOC_3_0_WE                  = 0x0000012a,
14167  SC_PA_SC_DEALLOC_3_1_WE                  = 0x0000012b,
14168  SC_PA0_SC_EOP_WE                         = 0x0000012c,
14169  SC_PA0_SC_EOPG_WE                        = 0x0000012d,
14170  SC_PA0_SC_EVENT_WE                       = 0x0000012e,
14171  SC_PA1_SC_EOP_WE                         = 0x0000012f,
14172  SC_PA1_SC_EOPG_WE                        = 0x00000130,
14173  SC_PA1_SC_EVENT_WE                       = 0x00000131,
14174  SC_PA2_SC_EOP_WE                         = 0x00000132,
14175  SC_PA2_SC_EOPG_WE                        = 0x00000133,
14176  SC_PA2_SC_EVENT_WE                       = 0x00000134,
14177  SC_PA3_SC_EOP_WE                         = 0x00000135,
14178  SC_PA3_SC_EOPG_WE                        = 0x00000136,
14179  SC_PA3_SC_EVENT_WE                       = 0x00000137,
14180  SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO = 0x00000138,
14181  SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH          = 0x00000139,
14182  SC_PS_ARB_NULL_PRIM_BUBBLE_POP           = 0x0000013a,
14183  SC_PS_ARB_EOP_POP_SYNC_POP               = 0x0000013b,
14184  SC_PS_ARB_EVENT_SYNC_POP                 = 0x0000013c,
14185  SC_PS_ENG_MULTICYCLE_BUBBLE              = 0x0000013d,
14186  SC_PA0_SC_FPOV_WE                        = 0x0000013e,
14187  SC_PA1_SC_FPOV_WE                        = 0x0000013f,
14188  SC_PA2_SC_FPOV_WE                        = 0x00000140,
14189  SC_PA3_SC_FPOV_WE                        = 0x00000141,
14190  SC_PA0_SC_LPOV_WE                        = 0x00000142,
14191  SC_PA1_SC_LPOV_WE                        = 0x00000143,
14192  SC_PA2_SC_LPOV_WE                        = 0x00000144,
14193  SC_PA3_SC_LPOV_WE                        = 0x00000145,
14194  SC_SPI_DEALLOC_0_0                       = 0x00000146,
14195  SC_SPI_DEALLOC_0_1                       = 0x00000147,
14196  SC_SPI_DEALLOC_0_2                       = 0x00000148,
14197  SC_SPI_DEALLOC_1_0                       = 0x00000149,
14198  SC_SPI_DEALLOC_1_1                       = 0x0000014a,
14199  SC_SPI_DEALLOC_1_2                       = 0x0000014b,
14200  SC_SPI_DEALLOC_2_0                       = 0x0000014c,
14201  SC_SPI_DEALLOC_2_1                       = 0x0000014d,
14202  SC_SPI_DEALLOC_2_2                       = 0x0000014e,
14203  SC_SPI_DEALLOC_3_0                       = 0x0000014f,
14204  SC_SPI_DEALLOC_3_1                       = 0x00000150,
14205  SC_SPI_DEALLOC_3_2                       = 0x00000151,
14206  SC_SPI_FPOV_0                            = 0x00000152,
14207  SC_SPI_FPOV_1                            = 0x00000153,
14208  SC_SPI_FPOV_2                            = 0x00000154,
14209  SC_SPI_FPOV_3                            = 0x00000155,
14210  SC_SPI_EVENT                             = 0x00000156,
14211  SC_PS_TS_EVENT_FIFO_PUSH                 = 0x00000157,
14212  SC_PS_TS_EVENT_FIFO_POP                  = 0x00000158,
14213  SC_PS_CTX_DONE_FIFO_PUSH                 = 0x00000159,
14214  SC_PS_CTX_DONE_FIFO_POP                  = 0x0000015a,
14215  SC_MULTICYCLE_BUBBLE_FREEZE              = 0x0000015b,
14216  SC_EOP_SYNC_WINDOW                       = 0x0000015c,
14217  SC_PA0_SC_NULL_WE                        = 0x0000015d,
14218  SC_PA0_SC_NULL_DEALLOC_WE                = 0x0000015e,
14219  SC_PA0_SC_DATA_FIFO_EOPG_RD              = 0x0000015f,
14220  SC_PA0_SC_DATA_FIFO_EOP_RD               = 0x00000160,
14221  SC_PA0_SC_DEALLOC_0_RD                   = 0x00000161,
14222  SC_PA0_SC_DEALLOC_1_RD                   = 0x00000162,
14223  SC_PA1_SC_DATA_FIFO_EOPG_RD              = 0x00000163,
14224  SC_PA1_SC_DATA_FIFO_EOP_RD               = 0x00000164,
14225  SC_PA1_SC_DEALLOC_0_RD                   = 0x00000165,
14226  SC_PA1_SC_DEALLOC_1_RD                   = 0x00000166,
14227  SC_PA1_SC_NULL_WE                        = 0x00000167,
14228  SC_PA1_SC_NULL_DEALLOC_WE                = 0x00000168,
14229  SC_PA2_SC_DATA_FIFO_EOPG_RD              = 0x00000169,
14230  SC_PA2_SC_DATA_FIFO_EOP_RD               = 0x0000016a,
14231  SC_PA2_SC_DEALLOC_0_RD                   = 0x0000016b,
14232  SC_PA2_SC_DEALLOC_1_RD                   = 0x0000016c,
14233  SC_PA2_SC_NULL_WE                        = 0x0000016d,
14234  SC_PA2_SC_NULL_DEALLOC_WE                = 0x0000016e,
14235  SC_PA3_SC_DATA_FIFO_EOPG_RD              = 0x0000016f,
14236  SC_PA3_SC_DATA_FIFO_EOP_RD               = 0x00000170,
14237  SC_PA3_SC_DEALLOC_0_RD                   = 0x00000171,
14238  SC_PA3_SC_DEALLOC_1_RD                   = 0x00000172,
14239  SC_PA3_SC_NULL_WE                        = 0x00000173,
14240  SC_PA3_SC_NULL_DEALLOC_WE                = 0x00000174,
14241  SC_PS_PA0_SC_FIFO_EMPTY                  = 0x00000175,
14242  SC_PS_PA0_SC_FIFO_FULL                   = 0x00000176,
14243  SC_RESERVED_0                            = 0x00000177,
14244  SC_PS_PA1_SC_FIFO_EMPTY                  = 0x00000178,
14245  SC_PS_PA1_SC_FIFO_FULL                   = 0x00000179,
14246  SC_RESERVED_1                            = 0x0000017a,
14247  SC_PS_PA2_SC_FIFO_EMPTY                  = 0x0000017b,
14248  SC_PS_PA2_SC_FIFO_FULL                   = 0x0000017c,
14249  SC_RESERVED_2                            = 0x0000017d,
14250  SC_PS_PA3_SC_FIFO_EMPTY                  = 0x0000017e,
14251  SC_PS_PA3_SC_FIFO_FULL                   = 0x0000017f,
14252  SC_RESERVED_3                            = 0x00000180,
14253  SC_BUSY_PROCESSING_MULTICYCLE_PRIM       = 0x00000181,
14254  SC_BUSY_CNT_NOT_ZERO                     = 0x00000182,
14255  SC_BM_BUSY                               = 0x00000183,
14256  SC_BACKEND_BUSY                          = 0x00000184,
14257  SC_SCF_SCB_INTERFACE_BUSY                = 0x00000185,
14258  SC_SCB_BUSY                              = 0x00000186,
14259  SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY = 0x00000187,
14260  SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL = 0x00000188,
14261  SC_PBB_BIN_HIST_NUM_PRIMS                = 0x00000189,
14262  SC_PBB_BATCH_HIST_NUM_PRIMS              = 0x0000018a,
14263  SC_PBB_BIN_HIST_NUM_CONTEXTS             = 0x0000018b,
14264  SC_PBB_BATCH_HIST_NUM_CONTEXTS           = 0x0000018c,
14265  SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES    = 0x0000018d,
14266  SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES  = 0x0000018e,
14267  SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS     = 0x0000018f,
14268  SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS = 0x00000190,
14269  SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM      = 0x00000191,
14270  SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW    = 0x00000192,
14271  SC_PBB_BUSY                              = 0x00000193,
14272  SC_PBB_BUSY_AND_NO_SENDS                 = 0x00000194,
14273  SC_PBB_STALLS_PA_DUE_TO_NO_TILES         = 0x00000195,
14274  SC_PBB_NUM_BINS                          = 0x00000196,
14275  SC_PBB_END_OF_BIN                        = 0x00000197,
14276  SC_PBB_END_OF_BATCH                      = 0x00000198,
14277  SC_PBB_PRIMBIN_PROCESSED                 = 0x00000199,
14278  SC_PBB_PRIM_ADDED_TO_BATCH               = 0x0000019a,
14279  SC_PBB_NONBINNED_PRIM                    = 0x0000019b,
14280  SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB       = 0x0000019c,
14281  SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB       = 0x0000019d,
14282  SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION = 0x0000019e,
14283  SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW = 0x0000019f,
14284  SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN = 0x000001a0,
14285  SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE = 0x000001a1,
14286  SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE  = 0x000001a2,
14287  SC_PBB_BATCH_BREAK_DUE_TO_PRIM           = 0x000001a3,
14288  SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE     = 0x000001a4,
14289  SC_PBB_BATCH_BREAK_DUE_TO_EVENT          = 0x000001a5,
14290  SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT     = 0x000001a6,
14291  SC_POPS_INTRA_WAVE_OVERLAPS              = 0x000001a7,
14292  SC_POPS_FORCE_EOV                        = 0x000001a8,
14293  SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_WAVES_SINCE_OVLP_SET_TO_MAX = 0x000001a9,
14294  SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_NO_CHANGE_TO_WAVES_SINCE_OVLP = 0x000001aa,
14295  SC_PKR_QUAD_OVLP_FOUND_IN_WAVE_TABLE     = 0x000001ab,
14296  SC_FULL_FULL_QUAD                        = 0x000001ac,
14297  SC_FULL_HALF_QUAD                        = 0x000001ad,
14298  SC_FULL_QTR_QUAD                         = 0x000001ae,
14299  SC_HALF_FULL_QUAD                        = 0x000001af,
14300  SC_HALF_HALF_QUAD                        = 0x000001b0,
14301  SC_HALF_QTR_QUAD                         = 0x000001b1,
14302  SC_QTR_FULL_QUAD                         = 0x000001b2,
14303  SC_QTR_HALF_QUAD                         = 0x000001b3,
14304  SC_QTR_QTR_QUAD                          = 0x000001b4,
14305  SC_GRP5_DYN_SCLK_BUSY                    = 0x000001b5,
14306  SC_GRP6_DYN_SCLK_BUSY                    = 0x000001b6,
14307  SC_GRP7_DYN_SCLK_BUSY                    = 0x000001b7,
14308  SC_GRP8_DYN_SCLK_BUSY                    = 0x000001b8,
14309  SC_GRP9_DYN_SCLK_BUSY                    = 0x000001b9,
14310  SC_PS_TO_BE_SCLK_GATE_STALL              = 0x000001ba,
14311  SC_PA_TO_PBB_SCLK_GATE_STALL_STALL       = 0x000001bb,
14312  SC_PK_BUSY                               = 0x000001bc,
14313  SC_PK_MAX_DEALLOC_FORCE_EOV              = 0x000001bd,
14314  SC_PK_DEALLOC_WAVE_BREAK                 = 0x000001be,
14315  SC_SPI_SEND                              = 0x000001bf,
14316  SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND  = 0x000001c0,
14317  SC_SPI_CREDIT_AT_MAX                     = 0x000001c1,
14318  SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND     = 0x000001c2,
14319  SC_BCI_SEND                              = 0x000001c3,
14320  SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND  = 0x000001c4,
14321  SC_BCI_CREDIT_AT_MAX                     = 0x000001c5,
14322  SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND     = 0x000001c6,
14323  SC_SPIBC_FULL_FREEZE                     = 0x000001c7,
14324  SC_PW_BM_PASS_EMPTY_PRIM                 = 0x000001c8,
14325  SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM = 0x000001c9,
14326  SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0 = 0x000001ca,
14327  SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1 = 0x000001cb,
14328  SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2 = 0x000001cc,
14329  SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3 = 0x000001cd,
14330  SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4 = 0x000001ce,
14331  SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5 = 0x000001cf,
14332  SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6 = 0x000001d0,
14333  SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7 = 0x000001d1,
14334  SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8 = 0x000001d2,
14335  SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9 = 0x000001d3,
14336  SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10 = 0x000001d4,
14337  SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11 = 0x000001d5,
14338  SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12 = 0x000001d6,
14339  SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13 = 0x000001d7,
14340  SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14 = 0x000001d8,
14341  SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15 = 0x000001d9,
14342  SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16 = 0x000001da,
14343  SC_DB0_TILE_INTERFACE_BUSY               = 0x000001db,
14344  SC_DB0_TILE_INTERFACE_SEND               = 0x000001dc,
14345  SC_DB0_TILE_INTERFACE_SEND_EVENT         = 0x000001dd,
14346  SC_DB0_TILE_INTERFACE_SEND_SOP_ONLY_EVENT = 0x000001de,
14347  SC_DB0_TILE_INTERFACE_SEND_SOP           = 0x000001df,
14348  SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001e0,
14349  SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX      = 0x000001e1,
14350  SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND = 0x000001e2,
14351  SC_DB1_TILE_INTERFACE_BUSY               = 0x000001e3,
14352  SC_DB1_TILE_INTERFACE_SEND               = 0x000001e4,
14353  SC_DB1_TILE_INTERFACE_SEND_EVENT         = 0x000001e5,
14354  SC_DB1_TILE_INTERFACE_SEND_SOP_ONLY_EVENT = 0x000001e6,
14355  SC_DB1_TILE_INTERFACE_SEND_SOP           = 0x000001e7,
14356  SC_DB1_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001e8,
14357  SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX      = 0x000001e9,
14358  SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND = 0x000001ea,
14359  SC_BACKEND_PRIM_FIFO_FULL                = 0x000001eb,
14360  SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER = 0x000001ec,
14361  SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH = 0x000001ed,
14362  SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH = 0x000001ee,
14363  SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT = 0x000001ef,
14364  SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT = 0x000001f0,
14365  SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV = 0x000001f1,
14366  SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE    = 0x000001f2,
14367  SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE = 0x000001f3,
14368  SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT = 0x000001f4,
14369  SC_PBB_BATCH_BREAK_DUE_TO_PIPE_RESET     = 0x000001f5,
14370  SC_PBB_BATCH_BREAK_DUE_TO_GFX_PIPE_CHANGE = 0x000001f6,
14371  SC_STALLED_BY_DB0_TILEFIFO               = 0x000001f7,
14372  SC_DB0_QUAD_INTF_SEND                    = 0x000001f8,
14373  SC_DB0_QUAD_INTF_BUSY                    = 0x000001f9,
14374  SC_DB0_QUAD_INTF_STALLED_BY_DB           = 0x000001fa,
14375  SC_DB0_QUAD_INTF_CREDIT_AT_MAX           = 0x000001fb,
14376  SC_DB0_QUAD_INTF_IDLE                    = 0x000001fc,
14377  SC_DB1_QUAD_INTF_SEND                    = 0x000001fd,
14378  SC_STALLED_BY_DB1_TILEFIFO               = 0x000001fe,
14379  SC_DB1_QUAD_INTF_BUSY                    = 0x000001ff,
14380  SC_DB1_QUAD_INTF_STALLED_BY_DB           = 0x00000200,
14381  SC_DB1_QUAD_INTF_CREDIT_AT_MAX           = 0x00000201,
14382  SC_DB1_QUAD_INTF_IDLE                    = 0x00000202,
14383  SC_PKR_WAVE_BREAK_OUTSIDE_REGION         = 0x00000203,
14384  SC_PKR_WAVE_BREAK_FULL_TILE              = 0x00000204,
14385  SC_FSR_WALKED                            = 0x00000205,
14386  SC_PBB_EMPTY_INPUT_CYCLE_WHEN_BATCH_OPEN = 0x00000206,
14387  SC_PBB_BATCH_BREAK_DUE_TO_NULL_PRIM_BREAK_BATCH_LIMIT = 0x00000207,
14388  SC_DB0_WE_STALLED_BY_RSLT_FIFO_FULL      = 0x00000208,
14389  SC_DB0_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL = 0x00000209,
14390  SC_DB0_TILE_MASK_FIFO_FULL               = 0x0000020a,
14391  SC_DB1_WE_STALLED_BY_RSLT_FIFO_FULL      = 0x0000020b,
14392  SC_DB1_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL = 0x0000020c,
14393  SC_DB1_TILE_MASK_FIFO_FULL               = 0x0000020d,
14394  SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PFF_PW_FULL = 0x0000020e,
14395  SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_ZFF_PW_FULL = 0x0000020f,
14396  SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PBB_TO_PSE_FIFO_FULL = 0x00000210,
14397  SC_PS_PM_PFF_PW_FULL                     = 0x00000211,
14398  SC_PS_PM_ZFF_PW_FULL                     = 0x00000212,
14399  SC_PS_PM_PBB_TO_PSE_FIFO_FULL            = 0x00000213,
14400  SC_PK_PM_QD1_FD_CONFLICT_WAVE_BRK_1H     = 0x00000214,
14401  SC_PK_PM_QD1_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H = 0x00000215,
14402  SC_PK_PM_QD1_AVOID_DEALLOC_ADD_WAVE_BRK_1H = 0x00000216,
14403  SC_PK_PM_4X2_SPLIT_WAVE_BRK_1H           = 0x00000217,
14404  SC_PK_PM_PKR_FILL_4X2_WAVE_BRK_1H        = 0x00000218,
14405  SC_PK_PM_SPLIT_OR_FILL_4X2_WAVE_BRK_1H   = 0x00000219,
14406  SC_PK_PM_END_OF_VECTOR_WAVE_BRK_1H       = 0x0000021a,
14407  SC_PK_PM_LAST_AND_DEALLOC_WAVE_BRK_1H    = 0x0000021b,
14408  SC_PK_PM_CTL_ONLY_CMD_WAVE_BRK_1H        = 0x0000021c,
14409  SC_PK_PM_AVOID_DEALLOC_ADD_WAVE_BRK_1H   = 0x0000021d,
14410  SC_PK_PM_FD_CONFLICT_WAVE_BRK_1H         = 0x0000021e,
14411  SC_PK_PM_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H = 0x0000021f,
14412  SC_PK_PM_AE_CONFLICT_WAVE_BRK_1H         = 0x00000220,
14413  SC_PK_PM_EOP_OR_LAD_WAVE_BRK_1H          = 0x00000221,
14414  SC_PK_PM_FULL_TILE_WAVE_BRK_1H           = 0x00000222,
14415  SC_PK_PM_POPS_FORCE_EOV_WAVE_BRK_1H      = 0x00000223,
14416  SC_PK_PM_MAX_DEALLOC_FORCE_EOV_WAVE_BRK_1H = 0x00000224,
14417  SC_PK_PM_WAVE_BREAK_OUTSIDE_REGION_WAVE_BRK_1H = 0x00000225,
14418  SC_PK_PM_MAX_CLK_CNT_FORCE_EOV_WAVE_BRK_1H = 0x00000226,
14419  SC_PK_PM_MAX_REZ_CNT_FORCE_EOV_WAVE_BRK_1H = 0x00000227,
14420  SC_PK_PM_VRS_RATE_X_00_Y_00_QUAD         = 0x00000228,
14421  SC_PK_PM_VRS_RATE_X_00_Y_01_QUAD         = 0x00000229,
14422  SC_PK_PM_VRS_RATE_X_00_Y_10_QUAD         = 0x0000022a,
14423  SC_PK_PM_VRS_RATE_X_00_Y_11_QUAD         = 0x0000022b,
14424  SC_PK_PM_VRS_RATE_X_01_Y_00_QUAD         = 0x0000022c,
14425  SC_PK_PM_VRS_RATE_X_01_Y_01_QUAD         = 0x0000022d,
14426  SC_PK_PM_VRS_RATE_X_01_Y_10_QUAD         = 0x0000022e,
14427  SC_PK_PM_VRS_RATE_X_01_Y_11_QUAD         = 0x0000022f,
14428  SC_PK_PM_VRS_RATE_X_10_Y_00_QUAD         = 0x00000230,
14429  SC_PK_PM_VRS_RATE_X_10_Y_01_QUAD         = 0x00000231,
14430  SC_PK_PM_VRS_RATE_X_10_Y_10_QUAD         = 0x00000232,
14431  SC_PK_PM_VRS_RATE_X_10_Y_11_QUAD         = 0x00000233,
14432  SC_PK_PM_VRS_RATE_X_11_Y_00_QUAD         = 0x00000234,
14433  SC_PK_PM_VRS_RATE_X_11_Y_01_QUAD         = 0x00000235,
14434  SC_PK_PM_VRS_RATE_X_11_Y_10_QUAD         = 0x00000236,
14435  SC_PK_PM_VRS_RATE_X_11_Y_11_QUAD         = 0x00000237,
14436  SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_MODE_CHANGE = 0x00000238,
14437  SC_PBB_RESERVED                          = 0x00000239,
14438  SC_BM_BE0_STALLED                        = 0x0000023a,
14439  SC_BM_BE1_STALLED                        = 0x0000023b,
14440  SC_BM_BE2_STALLED                        = 0x0000023c,
14441  SC_BM_BE3_STALLED                        = 0x0000023d,
14442  SC_BM_MULTI_ACCUM_1_BE_STALLED           = 0x0000023e,
14443  SC_BM_MULTI_ACCUM_2_BE_STALLED           = 0x0000023f,
14444  SC_BM_MULTI_ACCUM_3_BE_STALLED           = 0x00000240,
14445  SC_BM_MULTI_ACCUM_4_BE_STALLED           = 0x00000241,
14446  } SC_PERFCNT_SEL;
14447  
14448  /*
14449   * ScMap enum
14450   */
14451  
14452  typedef enum ScMap {
14453  RASTER_CONFIG_SC_MAP_0                   = 0x00000000,
14454  RASTER_CONFIG_SC_MAP_1                   = 0x00000001,
14455  RASTER_CONFIG_SC_MAP_2                   = 0x00000002,
14456  RASTER_CONFIG_SC_MAP_3                   = 0x00000003,
14457  } ScMap;
14458  
14459  /*
14460   * ScUncertaintyRegionMode enum
14461   */
14462  
14463  typedef enum ScUncertaintyRegionMode {
14464  SC_HALF_LSB                              = 0x00000000,
14465  SC_LSB_ONE_SIDED                         = 0x00000001,
14466  SC_LSB_TWO_SIDED                         = 0x00000002,
14467  } ScUncertaintyRegionMode;
14468  
14469  /*
14470   * ScUncertaintyRegionMult enum
14471   */
14472  
14473  typedef enum ScUncertaintyRegionMult {
14474  SC_UR_1X                                 = 0x00000000,
14475  SC_UR_2X                                 = 0x00000001,
14476  SC_UR_4X                                 = 0x00000002,
14477  SC_UR_8X                                 = 0x00000003,
14478  } ScUncertaintyRegionMult;
14479  
14480  /*
14481   * ScXsel enum
14482   */
14483  
14484  typedef enum ScXsel {
14485  RASTER_CONFIG_SC_XSEL_8_WIDE_TILE        = 0x00000000,
14486  RASTER_CONFIG_SC_XSEL_16_WIDE_TILE       = 0x00000001,
14487  RASTER_CONFIG_SC_XSEL_32_WIDE_TILE       = 0x00000002,
14488  RASTER_CONFIG_SC_XSEL_64_WIDE_TILE       = 0x00000003,
14489  } ScXsel;
14490  
14491  /*
14492   * ScYsel enum
14493   */
14494  
14495  typedef enum ScYsel {
14496  RASTER_CONFIG_SC_YSEL_8_WIDE_TILE        = 0x00000000,
14497  RASTER_CONFIG_SC_YSEL_16_WIDE_TILE       = 0x00000001,
14498  RASTER_CONFIG_SC_YSEL_32_WIDE_TILE       = 0x00000002,
14499  RASTER_CONFIG_SC_YSEL_64_WIDE_TILE       = 0x00000003,
14500  } ScYsel;
14501  
14502  /*
14503   * SeMap enum
14504   */
14505  
14506  typedef enum SeMap {
14507  RASTER_CONFIG_SE_MAP_0                   = 0x00000000,
14508  RASTER_CONFIG_SE_MAP_1                   = 0x00000001,
14509  RASTER_CONFIG_SE_MAP_2                   = 0x00000002,
14510  RASTER_CONFIG_SE_MAP_3                   = 0x00000003,
14511  } SeMap;
14512  
14513  /*
14514   * SePairMap enum
14515   */
14516  
14517  typedef enum SePairMap {
14518  RASTER_CONFIG_SE_PAIR_MAP_0              = 0x00000000,
14519  RASTER_CONFIG_SE_PAIR_MAP_1              = 0x00000001,
14520  RASTER_CONFIG_SE_PAIR_MAP_2              = 0x00000002,
14521  RASTER_CONFIG_SE_PAIR_MAP_3              = 0x00000003,
14522  } SePairMap;
14523  
14524  /*
14525   * SePairXsel enum
14526   */
14527  
14528  typedef enum SePairXsel {
14529  RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE   = 0x00000000,
14530  RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE  = 0x00000001,
14531  RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE  = 0x00000002,
14532  RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE  = 0x00000003,
14533  } SePairXsel;
14534  
14535  /*
14536   * SePairYsel enum
14537   */
14538  
14539  typedef enum SePairYsel {
14540  RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE   = 0x00000000,
14541  RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE  = 0x00000001,
14542  RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE  = 0x00000002,
14543  RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE  = 0x00000003,
14544  } SePairYsel;
14545  
14546  /*
14547   * SeXsel enum
14548   */
14549  
14550  typedef enum SeXsel {
14551  RASTER_CONFIG_SE_XSEL_8_WIDE_TILE        = 0x00000000,
14552  RASTER_CONFIG_SE_XSEL_16_WIDE_TILE       = 0x00000001,
14553  RASTER_CONFIG_SE_XSEL_32_WIDE_TILE       = 0x00000002,
14554  RASTER_CONFIG_SE_XSEL_64_WIDE_TILE       = 0x00000003,
14555  } SeXsel;
14556  
14557  /*
14558   * SeYsel enum
14559   */
14560  
14561  typedef enum SeYsel {
14562  RASTER_CONFIG_SE_YSEL_8_WIDE_TILE        = 0x00000000,
14563  RASTER_CONFIG_SE_YSEL_16_WIDE_TILE       = 0x00000001,
14564  RASTER_CONFIG_SE_YSEL_32_WIDE_TILE       = 0x00000002,
14565  RASTER_CONFIG_SE_YSEL_64_WIDE_TILE       = 0x00000003,
14566  } SeYsel;
14567  
14568  /*
14569   * VRSCombinerModeSC enum
14570   */
14571  
14572  typedef enum VRSCombinerModeSC {
14573  SC_VRS_COMB_MODE_PASSTHRU                = 0x00000000,
14574  SC_VRS_COMB_MODE_OVERRIDE                = 0x00000001,
14575  SC_VRS_COMB_MODE_MIN                     = 0x00000002,
14576  SC_VRS_COMB_MODE_MAX                     = 0x00000003,
14577  SC_VRS_COMB_MODE_SATURATE                = 0x00000004,
14578  } VRSCombinerModeSC;
14579  
14580  /*
14581   * VRSrate enum
14582   */
14583  
14584  typedef enum VRSrate {
14585  VRS_SHADING_RATE_1X1                     = 0x00000000,
14586  VRS_SHADING_RATE_1X2                     = 0x00000001,
14587  VRS_SHADING_RATE_UNDEFINED0              = 0x00000002,
14588  VRS_SHADING_RATE_UNDEFINED1              = 0x00000003,
14589  VRS_SHADING_RATE_2X1                     = 0x00000004,
14590  VRS_SHADING_RATE_2X2                     = 0x00000005,
14591  VRS_SHADING_RATE_2X4                     = 0x00000006,
14592  VRS_SHADING_RATE_UNDEFINED2              = 0x00000007,
14593  VRS_SHADING_RATE_UNDEFINED3              = 0x00000008,
14594  VRS_SHADING_RATE_4X2                     = 0x00000009,
14595  VRS_SHADING_RATE_4X4                     = 0x0000000a,
14596  VRS_SHADING_RATE_UNDEFINED4              = 0x0000000b,
14597  VRS_SHADING_RATE_16X_SSAA                = 0x0000000c,
14598  VRS_SHADING_RATE_8X_SSAA                 = 0x0000000d,
14599  VRS_SHADING_RATE_4X_SSAA                 = 0x0000000e,
14600  VRS_SHADING_RATE_2X_SSAA                 = 0x0000000f,
14601  } VRSrate;
14602  
14603  /*******************************************************
14604   * TC Enums
14605   *******************************************************/
14606  
14607  /*
14608   * TC_EA_CID enum
14609   */
14610  
14611  typedef enum TC_EA_CID {
14612  TC_EA_CID_RT                             = 0x00000000,
14613  TC_EA_CID_FMASK                          = 0x00000001,
14614  TC_EA_CID_DCC                            = 0x00000002,
14615  TC_EA_CID_TCPMETA                        = 0x00000003,
14616  TC_EA_CID_Z                              = 0x00000004,
14617  TC_EA_CID_STENCIL                        = 0x00000005,
14618  TC_EA_CID_HTILE                          = 0x00000006,
14619  TC_EA_CID_MISC                           = 0x00000007,
14620  TC_EA_CID_TCP                            = 0x00000008,
14621  TC_EA_CID_SQC                            = 0x00000009,
14622  TC_EA_CID_CPF                            = 0x0000000a,
14623  TC_EA_CID_CPG                            = 0x0000000b,
14624  TC_EA_CID_IA                             = 0x0000000c,
14625  TC_EA_CID_WD                             = 0x0000000d,
14626  TC_EA_CID_PA                             = 0x0000000e,
14627  TC_EA_CID_UTCL2_TPI                      = 0x0000000f,
14628  } TC_EA_CID;
14629  
14630  /*
14631   * TC_NACKS enum
14632   */
14633  
14634  typedef enum TC_NACKS {
14635  TC_NACK_NO_FAULT                         = 0x00000000,
14636  TC_NACK_PAGE_FAULT                       = 0x00000001,
14637  TC_NACK_PROTECTION_FAULT                 = 0x00000002,
14638  TC_NACK_DATA_ERROR                       = 0x00000003,
14639  } TC_NACKS;
14640  
14641  /*
14642   * TC_OP enum
14643   */
14644  
14645  typedef enum TC_OP {
14646  TC_OP_READ                               = 0x00000000,
14647  TC_OP_ATOMIC_FCMPSWAP_RTN_32             = 0x00000001,
14648  TC_OP_ATOMIC_FMIN_RTN_32                 = 0x00000002,
14649  TC_OP_ATOMIC_FMAX_RTN_32                 = 0x00000003,
14650  TC_OP_RESERVED_FOP_RTN_32_0              = 0x00000004,
14651  TC_OP_RESERVED_FADD_RTN_32               = 0x00000005,
14652  TC_OP_RESERVED_FOP_RTN_32_2              = 0x00000006,
14653  TC_OP_ATOMIC_SWAP_RTN_32                 = 0x00000007,
14654  TC_OP_ATOMIC_CMPSWAP_RTN_32              = 0x00000008,
14655  TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 0x00000009,
14656  TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32    = 0x0000000a,
14657  TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32    = 0x0000000b,
14658  TC_OP_PROBE_FILTER                       = 0x0000000c,
14659  TC_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32    = 0x0000000d,
14660  TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 0x0000000e,
14661  TC_OP_ATOMIC_ADD_RTN_32                  = 0x0000000f,
14662  TC_OP_ATOMIC_SUB_RTN_32                  = 0x00000010,
14663  TC_OP_ATOMIC_SMIN_RTN_32                 = 0x00000011,
14664  TC_OP_ATOMIC_UMIN_RTN_32                 = 0x00000012,
14665  TC_OP_ATOMIC_SMAX_RTN_32                 = 0x00000013,
14666  TC_OP_ATOMIC_UMAX_RTN_32                 = 0x00000014,
14667  TC_OP_ATOMIC_AND_RTN_32                  = 0x00000015,
14668  TC_OP_ATOMIC_OR_RTN_32                   = 0x00000016,
14669  TC_OP_ATOMIC_XOR_RTN_32                  = 0x00000017,
14670  TC_OP_ATOMIC_INC_RTN_32                  = 0x00000018,
14671  TC_OP_ATOMIC_DEC_RTN_32                  = 0x00000019,
14672  TC_OP_WBINVL1_VOL                        = 0x0000001a,
14673  TC_OP_WBINVL1_SD                         = 0x0000001b,
14674  TC_OP_RESERVED_NON_FLOAT_RTN_32_0        = 0x0000001c,
14675  TC_OP_RESERVED_NON_FLOAT_RTN_32_1        = 0x0000001d,
14676  TC_OP_RESERVED_NON_FLOAT_RTN_32_2        = 0x0000001e,
14677  TC_OP_RESERVED_NON_FLOAT_RTN_32_3        = 0x0000001f,
14678  TC_OP_WRITE                              = 0x00000020,
14679  TC_OP_ATOMIC_FCMPSWAP_RTN_64             = 0x00000021,
14680  TC_OP_ATOMIC_FMIN_RTN_64                 = 0x00000022,
14681  TC_OP_ATOMIC_FMAX_RTN_64                 = 0x00000023,
14682  TC_OP_RESERVED_FOP_RTN_64_0              = 0x00000024,
14683  TC_OP_RESERVED_FOP_RTN_64_1              = 0x00000025,
14684  TC_OP_RESERVED_FOP_RTN_64_2              = 0x00000026,
14685  TC_OP_ATOMIC_SWAP_RTN_64                 = 0x00000027,
14686  TC_OP_ATOMIC_CMPSWAP_RTN_64              = 0x00000028,
14687  TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 0x00000029,
14688  TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64    = 0x0000002a,
14689  TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64    = 0x0000002b,
14690  TC_OP_WBINVL2_SD                         = 0x0000002c,
14691  TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 0x0000002d,
14692  TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 0x0000002e,
14693  TC_OP_ATOMIC_ADD_RTN_64                  = 0x0000002f,
14694  TC_OP_ATOMIC_SUB_RTN_64                  = 0x00000030,
14695  TC_OP_ATOMIC_SMIN_RTN_64                 = 0x00000031,
14696  TC_OP_ATOMIC_UMIN_RTN_64                 = 0x00000032,
14697  TC_OP_ATOMIC_SMAX_RTN_64                 = 0x00000033,
14698  TC_OP_ATOMIC_UMAX_RTN_64                 = 0x00000034,
14699  TC_OP_ATOMIC_AND_RTN_64                  = 0x00000035,
14700  TC_OP_ATOMIC_OR_RTN_64                   = 0x00000036,
14701  TC_OP_ATOMIC_XOR_RTN_64                  = 0x00000037,
14702  TC_OP_ATOMIC_INC_RTN_64                  = 0x00000038,
14703  TC_OP_ATOMIC_DEC_RTN_64                  = 0x00000039,
14704  TC_OP_WBL2_NC                            = 0x0000003a,
14705  TC_OP_WBL2_WC                            = 0x0000003b,
14706  TC_OP_RESERVED_NON_FLOAT_RTN_64_1        = 0x0000003c,
14707  TC_OP_RESERVED_NON_FLOAT_RTN_64_2        = 0x0000003d,
14708  TC_OP_RESERVED_NON_FLOAT_RTN_64_3        = 0x0000003e,
14709  TC_OP_RESERVED_NON_FLOAT_RTN_64_4        = 0x0000003f,
14710  TC_OP_WBINVL1                            = 0x00000040,
14711  TC_OP_ATOMIC_FCMPSWAP_32                 = 0x00000041,
14712  TC_OP_ATOMIC_FMIN_32                     = 0x00000042,
14713  TC_OP_ATOMIC_FMAX_32                     = 0x00000043,
14714  TC_OP_RESERVED_FOP_32_0                  = 0x00000044,
14715  TC_OP_RESERVED_FADD_32                   = 0x00000045,
14716  TC_OP_RESERVED_FOP_32_2                  = 0x00000046,
14717  TC_OP_ATOMIC_SWAP_32                     = 0x00000047,
14718  TC_OP_ATOMIC_CMPSWAP_32                  = 0x00000048,
14719  TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32    = 0x00000049,
14720  TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32        = 0x0000004a,
14721  TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32        = 0x0000004b,
14722  TC_OP_INV_METADATA                       = 0x0000004c,
14723  TC_OP_ATOMIC_FADD_FLUSH_DENORM_32        = 0x0000004d,
14724  TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2     = 0x0000004e,
14725  TC_OP_ATOMIC_ADD_32                      = 0x0000004f,
14726  TC_OP_ATOMIC_SUB_32                      = 0x00000050,
14727  TC_OP_ATOMIC_SMIN_32                     = 0x00000051,
14728  TC_OP_ATOMIC_UMIN_32                     = 0x00000052,
14729  TC_OP_ATOMIC_SMAX_32                     = 0x00000053,
14730  TC_OP_ATOMIC_UMAX_32                     = 0x00000054,
14731  TC_OP_ATOMIC_AND_32                      = 0x00000055,
14732  TC_OP_ATOMIC_OR_32                       = 0x00000056,
14733  TC_OP_ATOMIC_XOR_32                      = 0x00000057,
14734  TC_OP_ATOMIC_INC_32                      = 0x00000058,
14735  TC_OP_ATOMIC_DEC_32                      = 0x00000059,
14736  TC_OP_INVL2_NC                           = 0x0000005a,
14737  TC_OP_NOP_RTN0                           = 0x0000005b,
14738  TC_OP_RESERVED_NON_FLOAT_32_1            = 0x0000005c,
14739  TC_OP_RESERVED_NON_FLOAT_32_2            = 0x0000005d,
14740  TC_OP_RESERVED_NON_FLOAT_32_3            = 0x0000005e,
14741  TC_OP_RESERVED_NON_FLOAT_32_4            = 0x0000005f,
14742  TC_OP_WBINVL2                            = 0x00000060,
14743  TC_OP_ATOMIC_FCMPSWAP_64                 = 0x00000061,
14744  TC_OP_ATOMIC_FMIN_64                     = 0x00000062,
14745  TC_OP_ATOMIC_FMAX_64                     = 0x00000063,
14746  TC_OP_RESERVED_FOP_64_0                  = 0x00000064,
14747  TC_OP_RESERVED_FOP_64_1                  = 0x00000065,
14748  TC_OP_RESERVED_FOP_64_2                  = 0x00000066,
14749  TC_OP_ATOMIC_SWAP_64                     = 0x00000067,
14750  TC_OP_ATOMIC_CMPSWAP_64                  = 0x00000068,
14751  TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64    = 0x00000069,
14752  TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64        = 0x0000006a,
14753  TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64        = 0x0000006b,
14754  TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0     = 0x0000006c,
14755  TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1     = 0x0000006d,
14756  TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2     = 0x0000006e,
14757  TC_OP_ATOMIC_ADD_64                      = 0x0000006f,
14758  TC_OP_ATOMIC_SUB_64                      = 0x00000070,
14759  TC_OP_ATOMIC_SMIN_64                     = 0x00000071,
14760  TC_OP_ATOMIC_UMIN_64                     = 0x00000072,
14761  TC_OP_ATOMIC_SMAX_64                     = 0x00000073,
14762  TC_OP_ATOMIC_UMAX_64                     = 0x00000074,
14763  TC_OP_ATOMIC_AND_64                      = 0x00000075,
14764  TC_OP_ATOMIC_OR_64                       = 0x00000076,
14765  TC_OP_ATOMIC_XOR_64                      = 0x00000077,
14766  TC_OP_ATOMIC_INC_64                      = 0x00000078,
14767  TC_OP_ATOMIC_DEC_64                      = 0x00000079,
14768  TC_OP_WBINVL2_NC                         = 0x0000007a,
14769  TC_OP_NOP_ACK                            = 0x0000007b,
14770  TC_OP_RESERVED_NON_FLOAT_64_1            = 0x0000007c,
14771  TC_OP_RESERVED_NON_FLOAT_64_2            = 0x0000007d,
14772  TC_OP_RESERVED_NON_FLOAT_64_3            = 0x0000007e,
14773  TC_OP_RESERVED_NON_FLOAT_64_4            = 0x0000007f,
14774  } TC_OP;
14775  
14776  /*
14777   * TC_OP_MASKS enum
14778   */
14779  
14780  typedef enum TC_OP_MASKS {
14781  TC_OP_MASK_FLUSH_DENROM                  = 0x00000008,
14782  TC_OP_MASK_64                            = 0x00000020,
14783  TC_OP_MASK_NO_RTN                        = 0x00000040,
14784  } TC_OP_MASKS;
14785  
14786  /*******************************************************
14787   * GL2 Enums
14788   *******************************************************/
14789  
14790  /*
14791   * GL2_EA_CID enum
14792   */
14793  
14794  typedef enum GL2_EA_CID {
14795  GL2_EA_CID_CLIENT                        = 0x00000000,
14796  GL2_EA_CID_SDMA                          = 0x00000001,
14797  GL2_EA_CID_RLC                           = 0x00000002,
14798  GL2_EA_CID_SQC                           = 0x00000003,
14799  GL2_EA_CID_CP                            = 0x00000004,
14800  GL2_EA_CID_CPDMA                         = 0x00000005,
14801  GL2_EA_CID_UTCL2                         = 0x00000006,
14802  GL2_EA_CID_RT                            = 0x00000007,
14803  GL2_EA_CID_FMASK                         = 0x00000008,
14804  GL2_EA_CID_DCC                           = 0x00000009,
14805  GL2_EA_CID_Z_STENCIL                     = 0x0000000a,
14806  GL2_EA_CID_ZPCPSD                        = 0x0000000b,
14807  GL2_EA_CID_HTILE                         = 0x0000000c,
14808  GL2_EA_CID_MES                           = 0x0000000d,
14809  GL2_EA_CID_TCPMETA                       = 0x0000000f,
14810  } GL2_EA_CID;
14811  
14812  /*
14813   * GL2_NACKS enum
14814   */
14815  
14816  typedef enum GL2_NACKS {
14817  GL2_NACK_NO_FAULT                        = 0x00000000,
14818  GL2_NACK_PAGE_FAULT                      = 0x00000001,
14819  GL2_NACK_PROTECTION_FAULT                = 0x00000002,
14820  GL2_NACK_DATA_ERROR                      = 0x00000003,
14821  } GL2_NACKS;
14822  
14823  /*
14824   * GL2_OP enum
14825   */
14826  
14827  typedef enum GL2_OP {
14828  GL2_OP_READ                              = 0x00000000,
14829  GL2_OP_ATOMIC_FCMPSWAP_RTN_32            = 0x00000001,
14830  GL2_OP_ATOMIC_FMIN_RTN_32                = 0x00000002,
14831  GL2_OP_ATOMIC_FMAX_RTN_32                = 0x00000003,
14832  GL2_OP_ATOMIC_SWAP_RTN_32                = 0x00000007,
14833  GL2_OP_ATOMIC_CMPSWAP_RTN_32             = 0x00000008,
14834  GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 0x00000009,
14835  GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32   = 0x0000000a,
14836  GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32   = 0x0000000b,
14837  GL2_OP_PROBE_FILTER                      = 0x0000000c,
14838  GL2_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32   = 0x0000000d,
14839  GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 0x0000000e,
14840  GL2_OP_ATOMIC_ADD_RTN_32                 = 0x0000000f,
14841  GL2_OP_ATOMIC_SUB_RTN_32                 = 0x00000010,
14842  GL2_OP_ATOMIC_SMIN_RTN_32                = 0x00000011,
14843  GL2_OP_ATOMIC_UMIN_RTN_32                = 0x00000012,
14844  GL2_OP_ATOMIC_SMAX_RTN_32                = 0x00000013,
14845  GL2_OP_ATOMIC_UMAX_RTN_32                = 0x00000014,
14846  GL2_OP_ATOMIC_AND_RTN_32                 = 0x00000015,
14847  GL2_OP_ATOMIC_OR_RTN_32                  = 0x00000016,
14848  GL2_OP_ATOMIC_XOR_RTN_32                 = 0x00000017,
14849  GL2_OP_ATOMIC_INC_RTN_32                 = 0x00000018,
14850  GL2_OP_ATOMIC_DEC_RTN_32                 = 0x00000019,
14851  GL2_OP_ATOMIC_CLAMP_SUB_RTN_32           = 0x0000001a,
14852  GL2_OP_WRITE                             = 0x00000020,
14853  GL2_OP_ATOMIC_FCMPSWAP_RTN_64            = 0x00000021,
14854  GL2_OP_ATOMIC_FMIN_RTN_64                = 0x00000022,
14855  GL2_OP_ATOMIC_FMAX_RTN_64                = 0x00000023,
14856  GL2_OP_ATOMIC_SWAP_RTN_64                = 0x00000027,
14857  GL2_OP_ATOMIC_CMPSWAP_RTN_64             = 0x00000028,
14858  GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 0x00000029,
14859  GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64   = 0x0000002a,
14860  GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64   = 0x0000002b,
14861  GL2_OP_ATOMIC_ADD_RTN_64                 = 0x0000002f,
14862  GL2_OP_ATOMIC_SUB_RTN_64                 = 0x00000030,
14863  GL2_OP_ATOMIC_SMIN_RTN_64                = 0x00000031,
14864  GL2_OP_ATOMIC_UMIN_RTN_64                = 0x00000032,
14865  GL2_OP_ATOMIC_SMAX_RTN_64                = 0x00000033,
14866  GL2_OP_ATOMIC_UMAX_RTN_64                = 0x00000034,
14867  GL2_OP_ATOMIC_AND_RTN_64                 = 0x00000035,
14868  GL2_OP_ATOMIC_OR_RTN_64                  = 0x00000036,
14869  GL2_OP_ATOMIC_XOR_RTN_64                 = 0x00000037,
14870  GL2_OP_ATOMIC_INC_RTN_64                 = 0x00000038,
14871  GL2_OP_ATOMIC_DEC_RTN_64                 = 0x00000039,
14872  GL2_OP_GL1_INV                           = 0x00000040,
14873  GL2_OP_ATOMIC_FCMPSWAP_32                = 0x00000041,
14874  GL2_OP_ATOMIC_FMIN_32                    = 0x00000042,
14875  GL2_OP_ATOMIC_FMAX_32                    = 0x00000043,
14876  GL2_OP_ATOMIC_SWAP_32                    = 0x00000047,
14877  GL2_OP_ATOMIC_CMPSWAP_32                 = 0x00000048,
14878  GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32   = 0x00000049,
14879  GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32       = 0x0000004a,
14880  GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32       = 0x0000004b,
14881  GL2_OP_ATOMIC_UMIN_8                     = 0x0000004c,
14882  GL2_OP_ATOMIC_FADD_FLUSH_DENORM_32       = 0x0000004d,
14883  GL2_OP_ATOMIC_ADD_32                     = 0x0000004f,
14884  GL2_OP_ATOMIC_SUB_32                     = 0x00000050,
14885  GL2_OP_ATOMIC_SMIN_32                    = 0x00000051,
14886  GL2_OP_ATOMIC_UMIN_32                    = 0x00000052,
14887  GL2_OP_ATOMIC_SMAX_32                    = 0x00000053,
14888  GL2_OP_ATOMIC_UMAX_32                    = 0x00000054,
14889  GL2_OP_ATOMIC_AND_32                     = 0x00000055,
14890  GL2_OP_ATOMIC_OR_32                      = 0x00000056,
14891  GL2_OP_ATOMIC_XOR_32                     = 0x00000057,
14892  GL2_OP_ATOMIC_INC_32                     = 0x00000058,
14893  GL2_OP_ATOMIC_DEC_32                     = 0x00000059,
14894  GL2_OP_NOP_RTN0                          = 0x0000005b,
14895  GL2_OP_ATOMIC_FCMPSWAP_64                = 0x00000061,
14896  GL2_OP_ATOMIC_FMIN_64                    = 0x00000062,
14897  GL2_OP_ATOMIC_FMAX_64                    = 0x00000063,
14898  GL2_OP_ATOMIC_SWAP_64                    = 0x00000067,
14899  GL2_OP_ATOMIC_CMPSWAP_64                 = 0x00000068,
14900  GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64   = 0x00000069,
14901  GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64       = 0x0000006a,
14902  GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64       = 0x0000006b,
14903  GL2_OP_ATOMIC_ADD_64                     = 0x0000006f,
14904  GL2_OP_ATOMIC_SUB_64                     = 0x00000070,
14905  GL2_OP_ATOMIC_SMIN_64                    = 0x00000071,
14906  GL2_OP_ATOMIC_UMIN_64                    = 0x00000072,
14907  GL2_OP_ATOMIC_SMAX_64                    = 0x00000073,
14908  GL2_OP_ATOMIC_UMAX_64                    = 0x00000074,
14909  GL2_OP_ATOMIC_AND_64                     = 0x00000075,
14910  GL2_OP_ATOMIC_OR_64                      = 0x00000076,
14911  GL2_OP_ATOMIC_XOR_64                     = 0x00000077,
14912  GL2_OP_ATOMIC_INC_64                     = 0x00000078,
14913  GL2_OP_ATOMIC_DEC_64                     = 0x00000079,
14914  GL2_OP_ATOMIC_UMAX_8                     = 0x0000007a,
14915  GL2_OP_NOP_ACK                           = 0x0000007b,
14916  } GL2_OP;
14917  
14918  /*
14919   * GL2_OP_MASKS enum
14920   */
14921  
14922  typedef enum GL2_OP_MASKS {
14923  GL2_OP_MASK_FLUSH_DENROM                 = 0x00000008,
14924  GL2_OP_MASK_64                           = 0x00000020,
14925  GL2_OP_MASK_NO_RTN                       = 0x00000040,
14926  } GL2_OP_MASKS;
14927  
14928  /*******************************************************
14929   * RLC Enums
14930   *******************************************************/
14931  
14932  /*
14933   * RLC_DOORBELL_MODE enum
14934   */
14935  
14936  typedef enum RLC_DOORBELL_MODE {
14937  RLC_DOORBELL_MODE_DISABLE                = 0x00000000,
14938  RLC_DOORBELL_MODE_ENABLE                 = 0x00000001,
14939  RLC_DOORBELL_MODE_ENABLE_PF              = 0x00000002,
14940  RLC_DOORBELL_MODE_ENABLE_PF_VF           = 0x00000003,
14941  } RLC_DOORBELL_MODE;
14942  
14943  /*
14944   * RLC_PERFCOUNTER_SEL enum
14945   */
14946  
14947  typedef enum RLC_PERFCOUNTER_SEL {
14948  RLC_PERF_SEL_POWER_FEATURE_0             = 0x00000000,
14949  RLC_PERF_SEL_POWER_FEATURE_1             = 0x00000001,
14950  RLC_PERF_SEL_CP_INTERRUPT                = 0x00000002,
14951  RLC_PERF_SEL_GRBM_INTERRUPT              = 0x00000003,
14952  RLC_PERF_SEL_SPM_INTERRUPT               = 0x00000004,
14953  RLC_PERF_SEL_IH_INTERRUPT                = 0x00000005,
14954  RLC_PERF_SEL_SERDES_COMMAND_WRITE        = 0x00000006,
14955  } RLC_PERFCOUNTER_SEL;
14956  
14957  /*
14958   * RLC_PERFMON_STATE enum
14959   */
14960  
14961  typedef enum RLC_PERFMON_STATE {
14962  RLC_PERFMON_STATE_RESET                  = 0x00000000,
14963  RLC_PERFMON_STATE_ENABLE                 = 0x00000001,
14964  RLC_PERFMON_STATE_DISABLE                = 0x00000002,
14965  RLC_PERFMON_STATE_RESERVED_3             = 0x00000003,
14966  RLC_PERFMON_STATE_RESERVED_4             = 0x00000004,
14967  RLC_PERFMON_STATE_RESERVED_5             = 0x00000005,
14968  RLC_PERFMON_STATE_RESERVED_6             = 0x00000006,
14969  RLC_PERFMON_STATE_ROLLOVER               = 0x00000007,
14970  } RLC_PERFMON_STATE;
14971  
14972  /*
14973   * RSPM_CMD enum
14974   */
14975  
14976  typedef enum RSPM_CMD {
14977  RSPM_CMD_INVALID                         = 0x00000000,
14978  RSPM_CMD_IDLE                            = 0x00000001,
14979  RSPM_CMD_CALIBRATE                       = 0x00000002,
14980  RSPM_CMD_SPM_RESET                       = 0x00000003,
14981  RSPM_CMD_SPM_START                       = 0x00000004,
14982  RSPM_CMD_SPM_STOP                        = 0x00000005,
14983  RSPM_CMD_PERF_RESET                      = 0x00000006,
14984  RSPM_CMD_PERF_SAMPLE                     = 0x00000007,
14985  RSPM_CMD_PROF_START                      = 0x00000008,
14986  RSPM_CMD_PROF_STOP                       = 0x00000009,
14987  RSPM_CMD_FORCE_SAMPLE                    = 0x0000000a,
14988  } RSPM_CMD;
14989  
14990  /*******************************************************
14991   * SPI Enums
14992   *******************************************************/
14993  
14994  /*
14995   * CLKGATE_BASE_MODE enum
14996   */
14997  
14998  typedef enum CLKGATE_BASE_MODE {
14999  MULT_8                                   = 0x00000000,
15000  MULT_16                                  = 0x00000001,
15001  } CLKGATE_BASE_MODE;
15002  
15003  /*
15004   * CLKGATE_SM_MODE enum
15005   */
15006  
15007  typedef enum CLKGATE_SM_MODE {
15008  ON_SEQ                                   = 0x00000000,
15009  OFF_SEQ                                  = 0x00000001,
15010  PROG_SEQ                                 = 0x00000002,
15011  READ_SEQ                                 = 0x00000003,
15012  SM_MODE_RESERVED                         = 0x00000004,
15013  } CLKGATE_SM_MODE;
15014  
15015  /*
15016   * SPI_FOG_MODE enum
15017   */
15018  
15019  typedef enum SPI_FOG_MODE {
15020  SPI_FOG_NONE                             = 0x00000000,
15021  SPI_FOG_EXP                              = 0x00000001,
15022  SPI_FOG_EXP2                             = 0x00000002,
15023  SPI_FOG_LINEAR                           = 0x00000003,
15024  } SPI_FOG_MODE;
15025  
15026  /*
15027   * SPI_LB_WAVES_SELECT enum
15028   */
15029  
15030  typedef enum SPI_LB_WAVES_SELECT {
15031  HS_GS                                    = 0x00000000,
15032  PS                                       = 0x00000001,
15033  CS_NA                                    = 0x00000002,
15034  SPI_LB_WAVES_RSVD                        = 0x00000003,
15035  } SPI_LB_WAVES_SELECT;
15036  
15037  /*
15038   * SPI_PERFCNT_SEL enum
15039   */
15040  
15041  typedef enum SPI_PERFCNT_SEL {
15042  SPI_PERF_GS_WINDOW_VALID                 = 0x00000001,
15043  SPI_PERF_GS_BUSY                         = 0x00000002,
15044  SPI_PERF_GS_CRAWLER_STALL                = 0x00000003,
15045  SPI_PERF_GS_EVENT_WAVE                   = 0x00000004,
15046  SPI_PERF_GS_WAVE                         = 0x00000005,
15047  SPI_PERF_GS_PERS_UPD_FULL0               = 0x00000006,
15048  SPI_PERF_GS_PERS_UPD_FULL1               = 0x00000007,
15049  SPI_PERF_GS_FIRST_SUBGRP                 = 0x00000008,
15050  SPI_PERF_GS_HS_DEALLOC                   = 0x00000009,
15051  SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT      = 0x0000000a,
15052  SPI_PERF_GS_POS0_STALL                   = 0x0000000b,
15053  SPI_PERF_GS_POS1_STALL                   = 0x0000000c,
15054  SPI_PERF_GS_INDX0_STALL                  = 0x0000000d,
15055  SPI_PERF_GS_INDX1_STALL                  = 0x0000000e,
15056  SPI_PERF_GS_PWS_STALL                    = 0x0000000f,
15057  SPI_PERF_HS_WINDOW_VALID                 = 0x00000015,
15058  SPI_PERF_HS_BUSY                         = 0x00000016,
15059  SPI_PERF_HS_CRAWLER_STALL                = 0x00000017,
15060  SPI_PERF_HS_FIRST_WAVE                   = 0x00000018,
15061  SPI_PERF_HS_OFFCHIP_LDS_STALL            = 0x00000019,
15062  SPI_PERF_HS_EVENT_WAVE                   = 0x0000001a,
15063  SPI_PERF_HS_WAVE                         = 0x0000001b,
15064  SPI_PERF_HS_PERS_UPD_FULL0               = 0x0000001c,
15065  SPI_PERF_HS_PERS_UPD_FULL1               = 0x0000001d,
15066  SPI_PERF_HS_PWS_STALL                    = 0x0000001e,
15067  SPI_PERF_CSGN_WINDOW_VALID               = 0x00000025,
15068  SPI_PERF_CSGN_BUSY                       = 0x00000026,
15069  SPI_PERF_CSGN_NUM_THREADGROUPS           = 0x00000027,
15070  SPI_PERF_CSGN_CRAWLER_STALL              = 0x00000028,
15071  SPI_PERF_CSGN_EVENT_WAVE                 = 0x00000029,
15072  SPI_PERF_CSGN_WAVE                       = 0x0000002a,
15073  SPI_PERF_CSGN_PWS_STALL                  = 0x0000002b,
15074  SPI_PERF_CSN_WINDOW_VALID                = 0x0000002c,
15075  SPI_PERF_CSN_BUSY                        = 0x0000002d,
15076  SPI_PERF_CSN_NUM_THREADGROUPS            = 0x0000002e,
15077  SPI_PERF_CSN_CRAWLER_STALL               = 0x0000002f,
15078  SPI_PERF_CSN_EVENT_WAVE                  = 0x00000030,
15079  SPI_PERF_CSN_WAVE                        = 0x00000031,
15080  SPI_PERF_PS0_WINDOW_VALID                = 0x00000035,
15081  SPI_PERF_PS1_WINDOW_VALID                = 0x00000036,
15082  SPI_PERF_PS2_WINDOW_VALID                = 0x00000037,
15083  SPI_PERF_PS3_WINDOW_VALID                = 0x00000038,
15084  SPI_PERF_PS0_BUSY                        = 0x00000039,
15085  SPI_PERF_PS1_BUSY                        = 0x0000003a,
15086  SPI_PERF_PS2_BUSY                        = 0x0000003b,
15087  SPI_PERF_PS3_BUSY                        = 0x0000003c,
15088  SPI_PERF_PS0_ACTIVE                      = 0x0000003d,
15089  SPI_PERF_PS1_ACTIVE                      = 0x0000003e,
15090  SPI_PERF_PS2_ACTIVE                      = 0x0000003f,
15091  SPI_PERF_PS3_ACTIVE                      = 0x00000040,
15092  SPI_PERF_PS0_DEALLOC                     = 0x00000041,
15093  SPI_PERF_PS1_DEALLOC                     = 0x00000042,
15094  SPI_PERF_PS2_DEALLOC                     = 0x00000043,
15095  SPI_PERF_PS3_DEALLOC                     = 0x00000044,
15096  SPI_PERF_PS0_EVENT_WAVE                  = 0x00000045,
15097  SPI_PERF_PS1_EVENT_WAVE                  = 0x00000046,
15098  SPI_PERF_PS2_EVENT_WAVE                  = 0x00000047,
15099  SPI_PERF_PS3_EVENT_WAVE                  = 0x00000048,
15100  SPI_PERF_PS0_WAVE                        = 0x00000049,
15101  SPI_PERF_PS1_WAVE                        = 0x0000004a,
15102  SPI_PERF_PS2_WAVE                        = 0x0000004b,
15103  SPI_PERF_PS3_WAVE                        = 0x0000004c,
15104  SPI_PERF_PS0_OPT_WAVE                    = 0x0000004d,
15105  SPI_PERF_PS1_OPT_WAVE                    = 0x0000004e,
15106  SPI_PERF_PS2_OPT_WAVE                    = 0x0000004f,
15107  SPI_PERF_PS3_OPT_WAVE                    = 0x00000050,
15108  SPI_PERF_PS0_PRIM_BIN0                   = 0x00000051,
15109  SPI_PERF_PS1_PRIM_BIN0                   = 0x00000052,
15110  SPI_PERF_PS2_PRIM_BIN0                   = 0x00000053,
15111  SPI_PERF_PS3_PRIM_BIN0                   = 0x00000054,
15112  SPI_PERF_PS0_PRIM_BIN1                   = 0x00000055,
15113  SPI_PERF_PS1_PRIM_BIN1                   = 0x00000056,
15114  SPI_PERF_PS2_PRIM_BIN1                   = 0x00000057,
15115  SPI_PERF_PS3_PRIM_BIN1                   = 0x00000058,
15116  SPI_PERF_PS0_CRAWLER_STALL               = 0x00000059,
15117  SPI_PERF_PS1_CRAWLER_STALL               = 0x0000005a,
15118  SPI_PERF_PS2_CRAWLER_STALL               = 0x0000005b,
15119  SPI_PERF_PS3_CRAWLER_STALL               = 0x0000005c,
15120  SPI_PERF_PS_PERS_UPD_FULL0               = 0x0000005d,
15121  SPI_PERF_PS_PERS_UPD_FULL1               = 0x0000005e,
15122  SPI_PERF_PS0_2_WAVE_GROUPS               = 0x0000005f,
15123  SPI_PERF_PS1_2_WAVE_GROUPS               = 0x00000060,
15124  SPI_PERF_PS2_2_WAVE_GROUPS               = 0x00000061,
15125  SPI_PERF_PS3_2_WAVE_GROUPS               = 0x00000062,
15126  SPI_PERF_PS0_WAVE_GROUP_CLOCK_DELAY      = 0x00000063,
15127  SPI_PERF_PS1_WAVE_GROUP_CLOCK_DELAY      = 0x00000064,
15128  SPI_PERF_PS2_WAVE_GROUP_CLOCK_DELAY      = 0x00000065,
15129  SPI_PERF_PS3_WAVE_GROUP_CLOCK_DELAY      = 0x00000066,
15130  SPI_PERF_PS0_WAVE_GROUP_TIMEOUTS         = 0x00000067,
15131  SPI_PERF_PS1_WAVE_GROUP_TIMEOUTS         = 0x00000068,
15132  SPI_PERF_PS2_WAVE_GROUP_TIMEOUTS         = 0x00000069,
15133  SPI_PERF_PS3_WAVE_GROUP_TIMEOUTS         = 0x0000006a,
15134  SPI_PERF_PS_PWS_STALL                    = 0x0000006b,
15135  SPI_PERF_RA_PIPE_REQ_BIN2                = 0x0000008d,
15136  SPI_PERF_RA_TASK_REQ_BIN3                = 0x0000008e,
15137  SPI_PERF_RA_WR_CTL_FULL                  = 0x0000008f,
15138  SPI_PERF_RA_REQ_NO_ALLOC                 = 0x00000090,
15139  SPI_PERF_RA_REQ_NO_ALLOC_PS              = 0x00000091,
15140  SPI_PERF_RA_REQ_NO_ALLOC_GS              = 0x00000092,
15141  SPI_PERF_RA_REQ_NO_ALLOC_HS              = 0x00000093,
15142  SPI_PERF_RA_REQ_NO_ALLOC_CSG             = 0x00000094,
15143  SPI_PERF_RA_REQ_NO_ALLOC_CSN             = 0x00000095,
15144  SPI_PERF_RA_RES_STALL_PS                 = 0x00000096,
15145  SPI_PERF_RA_RES_STALL_GS                 = 0x00000097,
15146  SPI_PERF_RA_RES_STALL_HS                 = 0x00000098,
15147  SPI_PERF_RA_RES_STALL_CSG                = 0x00000099,
15148  SPI_PERF_RA_RES_STALL_CSN                = 0x0000009a,
15149  SPI_PERF_RA_TMP_STALL_PS                 = 0x0000009b,
15150  SPI_PERF_RA_TMP_STALL_GS                 = 0x0000009c,
15151  SPI_PERF_RA_TMP_STALL_HS                 = 0x0000009d,
15152  SPI_PERF_RA_TMP_STALL_CSG                = 0x0000009e,
15153  SPI_PERF_RA_TMP_STALL_CSN                = 0x0000009f,
15154  SPI_PERF_RA_WAVE_SIMD_FULL_PS            = 0x000000a0,
15155  SPI_PERF_RA_WAVE_SIMD_FULL_GS            = 0x000000a1,
15156  SPI_PERF_RA_WAVE_SIMD_FULL_HS            = 0x000000a2,
15157  SPI_PERF_RA_WAVE_SIMD_FULL_CSG           = 0x000000a3,
15158  SPI_PERF_RA_WAVE_SIMD_FULL_CSN           = 0x000000a4,
15159  SPI_PERF_RA_VGPR_SIMD_FULL_PS            = 0x000000a5,
15160  SPI_PERF_RA_VGPR_SIMD_FULL_GS            = 0x000000a6,
15161  SPI_PERF_RA_VGPR_SIMD_FULL_HS            = 0x000000a7,
15162  SPI_PERF_RA_VGPR_SIMD_FULL_CSG           = 0x000000a8,
15163  SPI_PERF_RA_VGPR_SIMD_FULL_CSN           = 0x000000a9,
15164  SPI_PERF_RA_LDS_CU_FULL_PS               = 0x000000aa,
15165  SPI_PERF_RA_LDS_CU_FULL_HS               = 0x000000ab,
15166  SPI_PERF_RA_LDS_CU_FULL_GS               = 0x000000ac,
15167  SPI_PERF_RA_LDS_CU_FULL_CSG              = 0x000000ad,
15168  SPI_PERF_RA_LDS_CU_FULL_CSN              = 0x000000ae,
15169  SPI_PERF_RA_BAR_CU_FULL_HS               = 0x000000af,
15170  SPI_PERF_RA_BAR_CU_FULL_CSG              = 0x000000b0,
15171  SPI_PERF_RA_BAR_CU_FULL_CSN              = 0x000000b1,
15172  SPI_PERF_RA_BULKY_CU_FULL_CSG            = 0x000000b2,
15173  SPI_PERF_RA_BULKY_CU_FULL_CSN            = 0x000000b3,
15174  SPI_PERF_RA_TGLIM_CU_FULL_CSG            = 0x000000b4,
15175  SPI_PERF_RA_TGLIM_CU_FULL_CSN            = 0x000000b5,
15176  SPI_PERF_RA_WVLIM_STALL_PS               = 0x000000b6,
15177  SPI_PERF_RA_WVLIM_STALL_GS               = 0x000000b7,
15178  SPI_PERF_RA_WVLIM_STALL_HS               = 0x000000b8,
15179  SPI_PERF_RA_WVLIM_STALL_CSG              = 0x000000b9,
15180  SPI_PERF_RA_WVLIM_STALL_CSN              = 0x000000ba,
15181  SPI_PERF_RA_GS_LOCK                      = 0x000000bb,
15182  SPI_PERF_RA_HS_LOCK                      = 0x000000bc,
15183  SPI_PERF_RA_CSG_LOCK                     = 0x000000bd,
15184  SPI_PERF_RA_CSN_LOCK                     = 0x000000be,
15185  SPI_PERF_RA_RSV_UPD                      = 0x000000bf,
15186  SPI_PERF_RA_PRE_ALLOC_STALL              = 0x000000c0,
15187  SPI_PERF_RA_GFX_UNDER_TUNNEL             = 0x000000c1,
15188  SPI_PERF_RA_CSC_UNDER_TUNNEL             = 0x000000c2,
15189  SPI_PERF_RA_WVALLOC_STALL                = 0x000000c3,
15190  SPI_PERF_RA_ACCUM0_SIMD_FULL_PS          = 0x000000c4,
15191  SPI_PERF_RA_ACCUM1_SIMD_FULL_PS          = 0x000000c5,
15192  SPI_PERF_RA_ACCUM2_SIMD_FULL_PS          = 0x000000c6,
15193  SPI_PERF_RA_ACCUM3_SIMD_FULL_PS          = 0x000000c7,
15194  SPI_PERF_RA_ACCUM0_SIMD_FULL_GS          = 0x000000c8,
15195  SPI_PERF_RA_ACCUM1_SIMD_FULL_GS          = 0x000000c9,
15196  SPI_PERF_RA_ACCUM2_SIMD_FULL_GS          = 0x000000ca,
15197  SPI_PERF_RA_ACCUM3_SIMD_FULL_GS          = 0x000000cb,
15198  SPI_PERF_RA_ACCUM0_SIMD_FULL_HS          = 0x000000cc,
15199  SPI_PERF_RA_ACCUM1_SIMD_FULL_HS          = 0x000000cd,
15200  SPI_PERF_RA_ACCUM2_SIMD_FULL_HS          = 0x000000ce,
15201  SPI_PERF_RA_ACCUM3_SIMD_FULL_HS          = 0x000000cf,
15202  SPI_PERF_RA_ACCUM0_SIMD_FULL_CSG         = 0x000000d0,
15203  SPI_PERF_RA_ACCUM1_SIMD_FULL_CSG         = 0x000000d1,
15204  SPI_PERF_RA_ACCUM2_SIMD_FULL_CSG         = 0x000000d2,
15205  SPI_PERF_RA_ACCUM3_SIMD_FULL_CSG         = 0x000000d3,
15206  SPI_PERF_RA_ACCUM0_SIMD_FULL_CSN         = 0x000000d4,
15207  SPI_PERF_RA_ACCUM1_SIMD_FULL_CSN         = 0x000000d5,
15208  SPI_PERF_RA_ACCUM2_SIMD_FULL_CSN         = 0x000000d6,
15209  SPI_PERF_RA_ACCUM3_SIMD_FULL_CSN         = 0x000000d7,
15210  SPI_PERF_EXP_ARB_COL_CNT                 = 0x000000d8,
15211  SPI_PERF_EXP_ARB_POS_CNT                 = 0x000000d9,
15212  SPI_PERF_EXP_ARB_GDS_CNT                 = 0x000000da,
15213  SPI_PERF_EXP_ARB_IDX_CNT                 = 0x000000db,
15214  SPI_PERF_EXP_WITH_CONFLICT               = 0x000000dc,
15215  SPI_PERF_EXP_WITH_CONFLICT_CLEAR         = 0x000000dd,
15216  SPI_PERF_GS_EXP_DONE                     = 0x000000de,
15217  SPI_PERF_PS_EXP_DONE                     = 0x000000df,
15218  SPI_PERF_PS_EXP_ARB_CONFLICT             = 0x000000e0,
15219  SPI_PERF_PS_EXP_ALLOC                    = 0x000000e1,
15220  SPI_PERF_PS0_WAVEID_STARVED              = 0x000000e2,
15221  SPI_PERF_PS1_WAVEID_STARVED              = 0x000000e3,
15222  SPI_PERF_PS2_WAVEID_STARVED              = 0x000000e4,
15223  SPI_PERF_PS3_WAVEID_STARVED              = 0x000000e5,
15224  SPI_PERF_PS0_EXP_ALLOC_WITH_CONFLICT     = 0x000000e6,
15225  SPI_PERF_PS1_EXP_ALLOC_WITH_CONFLICT     = 0x000000e7,
15226  SPI_PERF_PS2_EXP_ALLOC_WITH_CONFLICT     = 0x000000e8,
15227  SPI_PERF_PS3_EXP_ALLOC_WITH_CONFLICT     = 0x000000e9,
15228  SPI_PERF_NUM_PS_COL_SA0SQ0_EXPORTS       = 0x000000ea,
15229  SPI_PERF_NUM_PS_COL_SA0SQ1_EXPORTS       = 0x000000eb,
15230  SPI_PERF_NUM_PS_COL_SA1SQ0_EXPORTS       = 0x000000ec,
15231  SPI_PERF_NUM_PS_COL_SA1SQ1_EXPORTS       = 0x000000ed,
15232  SPI_PERF_NUM_POS_SA0SQ0_EXPORTS          = 0x000000ee,
15233  SPI_PERF_NUM_POS_SA0SQ1_EXPORTS          = 0x000000ef,
15234  SPI_PERF_NUM_POS_SA1SQ0_EXPORTS          = 0x000000f0,
15235  SPI_PERF_NUM_POS_SA1SQ1_EXPORTS          = 0x000000f1,
15236  SPI_PERF_NUM_GDS_SA0SQ0_EXPORTS          = 0x000000f2,
15237  SPI_PERF_NUM_GDS_SA0SQ1_EXPORTS          = 0x000000f3,
15238  SPI_PERF_NUM_GDS_SA1SQ0_EXPORTS          = 0x000000f4,
15239  SPI_PERF_NUM_GDS_SA1SQ1_EXPORTS          = 0x000000f5,
15240  SPI_PERF_NUM_EXPGRANT_EXPORTS            = 0x000000f6,
15241  SPI_PERF_PIX_ALLOC_PEND_CNT              = 0x000000fd,
15242  SPI_PERF_EXPORT_SCB0_STALL               = 0x000000fe,
15243  SPI_PERF_EXPORT_SCB1_STALL               = 0x000000ff,
15244  SPI_PERF_EXPORT_SCB2_STALL               = 0x00000100,
15245  SPI_PERF_EXPORT_SCB3_STALL               = 0x00000101,
15246  SPI_PERF_EXPORT_DB0_STALL                = 0x00000102,
15247  SPI_PERF_EXPORT_DB1_STALL                = 0x00000103,
15248  SPI_PERF_EXPORT_DB2_STALL                = 0x00000104,
15249  SPI_PERF_EXPORT_DB3_STALL                = 0x00000105,
15250  SPI_PERF_EXPORT_DB4_STALL                = 0x00000106,
15251  SPI_PERF_EXPORT_DB5_STALL                = 0x00000107,
15252  SPI_PERF_EXPORT_DB6_STALL                = 0x00000108,
15253  SPI_PERF_EXPORT_DB7_STALL                = 0x00000109,
15254  SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC         = 0x0000010a,
15255  SPI_PERF_GS_NGG_STALL_MSG_VAL            = 0x0000010b,
15256  SPI_PERF_SWC_PS_WR                       = 0x0000010c,
15257  SPI_PERF_SWC_GS_WR                       = 0x0000010d,
15258  SPI_PERF_SWC_HS_WR                       = 0x0000010e,
15259  SPI_PERF_SWC_CSGN_WR                     = 0x0000010f,
15260  SPI_PERF_SWC_CSN_WR                      = 0x00000110,
15261  SPI_PERF_VWC_PS_WR                       = 0x00000111,
15262  SPI_PERF_VWC_ES_WR                       = 0x00000112,
15263  SPI_PERF_VWC_GS_WR                       = 0x00000113,
15264  SPI_PERF_VWC_LS_WR                       = 0x00000114,
15265  SPI_PERF_VWC_HS_WR                       = 0x00000115,
15266  SPI_PERF_VWC_CSGN_WR                     = 0x00000116,
15267  SPI_PERF_VWC_CSN_WR                      = 0x00000117,
15268  SPI_PERF_EXP_THROT_UPSTEP                = 0x00000118,
15269  SPI_PERF_EXP_THROT_DOWNSTEP              = 0x00000119,
15270  SPI_PERF_EXP_THROT_CAUSALITY_DETECTED    = 0x0000011a,
15271  SPI_PERF_BUSY                            = 0x0000011b,
15272  } SPI_PERFCNT_SEL;
15273  
15274  /*
15275   * SPI_PNT_SPRITE_OVERRIDE enum
15276   */
15277  
15278  typedef enum SPI_PNT_SPRITE_OVERRIDE {
15279  SPI_PNT_SPRITE_SEL_0                     = 0x00000000,
15280  SPI_PNT_SPRITE_SEL_1                     = 0x00000001,
15281  SPI_PNT_SPRITE_SEL_S                     = 0x00000002,
15282  SPI_PNT_SPRITE_SEL_T                     = 0x00000003,
15283  SPI_PNT_SPRITE_SEL_NONE                  = 0x00000004,
15284  } SPI_PNT_SPRITE_OVERRIDE;
15285  
15286  /*
15287   * SPI_PS_LDS_GROUP_SIZE enum
15288   */
15289  
15290  typedef enum SPI_PS_LDS_GROUP_SIZE {
15291  SPI_PS_LDS_GROUP_1                       = 0x00000000,
15292  SPI_PS_LDS_GROUP_2                       = 0x00000001,
15293  SPI_PS_LDS_GROUP_4                       = 0x00000002,
15294  } SPI_PS_LDS_GROUP_SIZE;
15295  
15296  /*
15297   * SPI_SAMPLE_CNTL enum
15298   */
15299  
15300  typedef enum SPI_SAMPLE_CNTL {
15301  CENTROIDS_ONLY                           = 0x00000000,
15302  CENTERS_ONLY                             = 0x00000001,
15303  CENTROIDS_AND_CENTERS                    = 0x00000002,
15304  UNDEF                                    = 0x00000003,
15305  } SPI_SAMPLE_CNTL;
15306  
15307  /*
15308   * SPI_SHADER_EX_FORMAT enum
15309   */
15310  
15311  typedef enum SPI_SHADER_EX_FORMAT {
15312  SPI_SHADER_ZERO                          = 0x00000000,
15313  SPI_SHADER_32_R                          = 0x00000001,
15314  SPI_SHADER_32_GR                         = 0x00000002,
15315  SPI_SHADER_32_AR                         = 0x00000003,
15316  SPI_SHADER_FP16_ABGR                     = 0x00000004,
15317  SPI_SHADER_UNORM16_ABGR                  = 0x00000005,
15318  SPI_SHADER_SNORM16_ABGR                  = 0x00000006,
15319  SPI_SHADER_UINT16_ABGR                   = 0x00000007,
15320  SPI_SHADER_SINT16_ABGR                   = 0x00000008,
15321  SPI_SHADER_32_ABGR                       = 0x00000009,
15322  } SPI_SHADER_EX_FORMAT;
15323  
15324  /*
15325   * SPI_SHADER_FORMAT enum
15326   */
15327  
15328  typedef enum SPI_SHADER_FORMAT {
15329  SPI_SHADER_NONE                          = 0x00000000,
15330  SPI_SHADER_1COMP                         = 0x00000001,
15331  SPI_SHADER_2COMP                         = 0x00000002,
15332  SPI_SHADER_4COMPRESS                     = 0x00000003,
15333  SPI_SHADER_4COMP                         = 0x00000004,
15334  } SPI_SHADER_FORMAT;
15335  
15336  /*******************************************************
15337   * SQ Enums
15338   *******************************************************/
15339  
15340  /*
15341   * SH_MEM_ADDRESS_MODE enum
15342   */
15343  
15344  typedef enum SH_MEM_ADDRESS_MODE {
15345  SH_MEM_ADDRESS_MODE_64                   = 0x00000000,
15346  SH_MEM_ADDRESS_MODE_32                   = 0x00000001,
15347  } SH_MEM_ADDRESS_MODE;
15348  
15349  /*
15350   * SH_MEM_ALIGNMENT_MODE enum
15351   */
15352  
15353  typedef enum SH_MEM_ALIGNMENT_MODE {
15354  SH_MEM_ALIGNMENT_MODE_DWORD              = 0x00000000,
15355  SH_MEM_ALIGNMENT_MODE_DWORD_STRICT       = 0x00000001,
15356  SH_MEM_ALIGNMENT_MODE_STRICT             = 0x00000002,
15357  SH_MEM_ALIGNMENT_MODE_UNALIGNED          = 0x00000003,
15358  } SH_MEM_ALIGNMENT_MODE;
15359  
15360  /*
15361   * SQG_PERF_SEL enum
15362   */
15363  
15364  typedef enum SQG_PERF_SEL {
15365  SQG_PERF_SEL_NONE                        = 0x00000000,
15366  SQG_PERF_SEL_MSG_BUS_BUSY                = 0x00000001,
15367  SQG_PERF_SEL_EXP_REQ0_BUS_BUSY           = 0x00000002,
15368  SQG_PERF_SEL_EXP_REQ1_BUS_BUSY           = 0x00000003,
15369  SQG_PERF_SEL_EXP_BUS0_BUSY               = 0x00000004,
15370  SQG_PERF_SEL_EXP_BUS1_BUSY               = 0x00000005,
15371  SQG_PERF_SEL_TTRACE_REQS                 = 0x00000006,
15372  SQG_PERF_SEL_TTRACE_INFLIGHT_REQS        = 0x00000007,
15373  SQG_PERF_SEL_TTRACE_STALL                = 0x00000008,
15374  SQG_PERF_SEL_TTRACE_LOST_PACKETS         = 0x00000009,
15375  SQG_PERF_SEL_WAVES_INITIAL_PREFETCH      = 0x0000000a,
15376  SQG_PERF_SEL_EVENTS                      = 0x0000000b,
15377  SQG_PERF_SEL_WAVES_RESTORED              = 0x0000000c,
15378  SQG_PERF_SEL_WAVES_SAVED                 = 0x0000000d,
15379  SQG_PERF_SEL_ACCUM_PREV                  = 0x0000000e,
15380  SQG_PERF_SEL_CYCLES                      = 0x0000000f,
15381  SQG_PERF_SEL_BUSY_CYCLES                 = 0x00000010,
15382  SQG_PERF_SEL_WAVE_CYCLES                 = 0x00000011,
15383  SQG_PERF_SEL_MSG                         = 0x00000012,
15384  SQG_PERF_SEL_MSG_INTERRUPT               = 0x00000013,
15385  SQG_PERF_SEL_WAVES                       = 0x00000014,
15386  SQG_PERF_SEL_WAVES_32                    = 0x00000015,
15387  SQG_PERF_SEL_WAVES_64                    = 0x00000016,
15388  SQG_PERF_SEL_LEVEL_WAVES                 = 0x00000017,
15389  SQG_PERF_SEL_ITEMS                       = 0x00000018,
15390  SQG_PERF_SEL_WAVE32_ITEMS                = 0x00000019,
15391  SQG_PERF_SEL_WAVE64_ITEMS                = 0x0000001a,
15392  SQG_PERF_SEL_PS_QUADS                    = 0x0000001b,
15393  SQG_PERF_SEL_WAVES_EQ_64                 = 0x0000001c,
15394  SQG_PERF_SEL_WAVES_EQ_32                 = 0x0000001d,
15395  SQG_PERF_SEL_WAVES_LT_64                 = 0x0000001e,
15396  SQG_PERF_SEL_WAVES_LT_48                 = 0x0000001f,
15397  SQG_PERF_SEL_WAVES_LT_32                 = 0x00000020,
15398  SQG_PERF_SEL_WAVES_LT_16                 = 0x00000021,
15399  SQG_PERF_SEL_DUMMY_LAST                  = 0x00000022,
15400  } SQG_PERF_SEL;
15401  
15402  /*
15403   * SQ_CAC_POWER_SEL enum
15404   */
15405  
15406  typedef enum SQ_CAC_POWER_SEL {
15407  SQ_CAC_POWER_VALU                        = 0x00000000,
15408  SQ_CAC_POWER_VALU0                       = 0x00000001,
15409  SQ_CAC_POWER_VALU1                       = 0x00000002,
15410  SQ_CAC_POWER_VALU2                       = 0x00000003,
15411  SQ_CAC_POWER_GPR_RD                      = 0x00000004,
15412  SQ_CAC_POWER_GPR_WR                      = 0x00000005,
15413  SQ_CAC_POWER_LDS_BUSY                    = 0x00000006,
15414  SQ_CAC_POWER_ALU_BUSY                    = 0x00000007,
15415  SQ_CAC_POWER_TEX_BUSY                    = 0x00000008,
15416  } SQ_CAC_POWER_SEL;
15417  
15418  /*
15419   * SQ_EDC_INFO_SOURCE enum
15420   */
15421  
15422  typedef enum SQ_EDC_INFO_SOURCE {
15423  SQ_EDC_INFO_SOURCE_INVALID               = 0x00000000,
15424  SQ_EDC_INFO_SOURCE_INST                  = 0x00000001,
15425  SQ_EDC_INFO_SOURCE_SGPR                  = 0x00000002,
15426  SQ_EDC_INFO_SOURCE_VGPR                  = 0x00000003,
15427  SQ_EDC_INFO_SOURCE_LDS                   = 0x00000004,
15428  SQ_EDC_INFO_SOURCE_GDS                   = 0x00000005,
15429  SQ_EDC_INFO_SOURCE_TA                    = 0x00000006,
15430  } SQ_EDC_INFO_SOURCE;
15431  
15432  /*
15433   * SQ_IBUF_ST enum
15434   */
15435  
15436  typedef enum SQ_IBUF_ST {
15437  SQ_IBUF_IB_IDLE                          = 0x00000000,
15438  SQ_IBUF_IB_INI_WAIT_GNT                  = 0x00000001,
15439  SQ_IBUF_IB_INI_WAIT_DRET                 = 0x00000002,
15440  SQ_IBUF_IB_LE_4DW                        = 0x00000003,
15441  SQ_IBUF_IB_WAIT_DRET                     = 0x00000004,
15442  SQ_IBUF_IB_EMPTY_WAIT_DRET               = 0x00000005,
15443  SQ_IBUF_IB_DRET                          = 0x00000006,
15444  SQ_IBUF_IB_EMPTY_WAIT_GNT                = 0x00000007,
15445  } SQ_IBUF_ST;
15446  
15447  /*
15448   * SQ_IMG_FILTER_TYPE enum
15449   */
15450  
15451  typedef enum SQ_IMG_FILTER_TYPE {
15452  SQ_IMG_FILTER_MODE_BLEND                 = 0x00000000,
15453  SQ_IMG_FILTER_MODE_MIN                   = 0x00000001,
15454  SQ_IMG_FILTER_MODE_MAX                   = 0x00000002,
15455  } SQ_IMG_FILTER_TYPE;
15456  
15457  /*
15458   * SQ_IND_CMD_CMD enum
15459   */
15460  
15461  typedef enum SQ_IND_CMD_CMD {
15462  SQ_IND_CMD_CMD_NULL                      = 0x00000000,
15463  SQ_IND_CMD_CMD_SETHALT                   = 0x00000001,
15464  SQ_IND_CMD_CMD_SAVECTX                   = 0x00000002,
15465  SQ_IND_CMD_CMD_KILL                      = 0x00000003,
15466  SQ_IND_CMD_CMD_TRAP_AFTER_INST           = 0x00000004,
15467  SQ_IND_CMD_CMD_TRAP                      = 0x00000005,
15468  SQ_IND_CMD_CMD_SET_SPI_PRIO              = 0x00000006,
15469  SQ_IND_CMD_CMD_SETFATALHALT              = 0x00000007,
15470  SQ_IND_CMD_CMD_SINGLE_STEP               = 0x00000008,
15471  } SQ_IND_CMD_CMD;
15472  
15473  /*
15474   * SQ_IND_CMD_MODE enum
15475   */
15476  
15477  typedef enum SQ_IND_CMD_MODE {
15478  SQ_IND_CMD_MODE_SINGLE                   = 0x00000000,
15479  SQ_IND_CMD_MODE_BROADCAST                = 0x00000001,
15480  SQ_IND_CMD_MODE_BROADCAST_QUEUE          = 0x00000002,
15481  SQ_IND_CMD_MODE_BROADCAST_PIPE           = 0x00000003,
15482  SQ_IND_CMD_MODE_BROADCAST_ME             = 0x00000004,
15483  } SQ_IND_CMD_MODE;
15484  
15485  /*
15486   * SQ_INST_STR_ST enum
15487   */
15488  
15489  typedef enum SQ_INST_STR_ST {
15490  SQ_INST_STR_IB_WAVE_NORML                = 0x00000000,
15491  SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV    = 0x00000001,
15492  SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV     = 0x00000002,
15493  SQ_INST_STR_IB_WAVE_INST_SKIP_AV         = 0x00000003,
15494  SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT       = 0x00000004,
15495  SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 0x00000005,
15496  } SQ_INST_STR_ST;
15497  
15498  /*
15499   * SQ_INST_TYPE enum
15500   */
15501  
15502  typedef enum SQ_INST_TYPE {
15503  SQ_INST_TYPE_VALU                        = 0x00000000,
15504  SQ_INST_TYPE_SCALAR                      = 0x00000001,
15505  SQ_INST_TYPE_TEX                         = 0x00000002,
15506  SQ_INST_TYPE_LDS                         = 0x00000003,
15507  SQ_INST_TYPE_LDS_DIRECT                  = 0x00000004,
15508  SQ_INST_TYPE_EXP                         = 0x00000005,
15509  SQ_INST_TYPE_MSG                         = 0x00000006,
15510  SQ_INST_TYPE_BARRIER                     = 0x00000007,
15511  SQ_INST_TYPE_BRANCH_NOT_TAKEN            = 0x00000008,
15512  SQ_INST_TYPE_BRANCH_TAKEN                = 0x00000009,
15513  SQ_INST_TYPE_JUMP                        = 0x0000000a,
15514  SQ_INST_TYPE_OTHER                       = 0x0000000b,
15515  SQ_INST_TYPE_NONE                        = 0x0000000c,
15516  } SQ_INST_TYPE;
15517  
15518  /*
15519   * SQ_LLC_CTL enum
15520   */
15521  
15522  typedef enum SQ_LLC_CTL {
15523  SQ_LLC_0                                 = 0x00000000,
15524  SQ_LLC_1                                 = 0x00000001,
15525  SQ_LLC_RSVD_2                            = 0x00000002,
15526  SQ_LLC_BYPASS                            = 0x00000003,
15527  } SQ_LLC_CTL;
15528  
15529  /*
15530   * SQ_NO_INST_ISSUE enum
15531   */
15532  
15533  typedef enum SQ_NO_INST_ISSUE {
15534  SQ_NO_INST_ISSUE_NO_INSTS                = 0x00000000,
15535  SQ_NO_INST_ISSUE_ALU_DEP                 = 0x00000001,
15536  SQ_NO_INST_ISSUE_S_WAITCNT               = 0x00000002,
15537  SQ_NO_INST_ISSUE_NO_ARB_WIN              = 0x00000003,
15538  SQ_NO_INST_ISSUE_SLEEP_WAIT              = 0x00000004,
15539  SQ_NO_INST_ISSUE_BARRIER_WAIT            = 0x00000005,
15540  SQ_NO_INST_ISSUE_OTHER                   = 0x00000006,
15541  } SQ_NO_INST_ISSUE;
15542  
15543  /*
15544   * SQ_OOB_SELECT enum
15545   */
15546  
15547  typedef enum SQ_OOB_SELECT {
15548  SQ_OOB_INDEX_AND_OFFSET                  = 0x00000000,
15549  SQ_OOB_INDEX_ONLY                        = 0x00000001,
15550  SQ_OOB_NUM_RECORDS_0                     = 0x00000002,
15551  SQ_OOB_COMPLETE                          = 0x00000003,
15552  } SQ_OOB_SELECT;
15553  
15554  /*
15555   * SQ_PERF_SEL enum
15556   */
15557  
15558  typedef enum SQ_PERF_SEL {
15559  SQ_PERF_SEL_NONE                         = 0x00000000,
15560  SQ_PERF_SEL_ACCUM_PREV                   = 0x00000001,
15561  SQ_PERF_SEL_CYCLES                       = 0x00000002,
15562  SQ_PERF_SEL_BUSY_CYCLES                  = 0x00000003,
15563  SQ_PERF_SEL_WAVES                        = 0x00000004,
15564  SQ_PERF_SEL_WAVES_32                     = 0x00000005,
15565  SQ_PERF_SEL_WAVES_64                     = 0x00000006,
15566  SQ_PERF_SEL_LEVEL_WAVES                  = 0x00000007,
15567  SQ_PERF_SEL_ITEMS                        = 0x00000008,
15568  SQ_PERF_SEL_WAVE32_ITEMS                 = 0x00000009,
15569  SQ_PERF_SEL_WAVE64_ITEMS                 = 0x0000000a,
15570  SQ_PERF_SEL_PS_QUADS                     = 0x0000000b,
15571  SQ_PERF_SEL_EVENTS                       = 0x0000000c,
15572  SQ_PERF_SEL_WAVES_EQ_32                  = 0x0000000d,
15573  SQ_PERF_SEL_WAVES_EQ_64                  = 0x0000000e,
15574  SQ_PERF_SEL_WAVES_LT_64                  = 0x0000000f,
15575  SQ_PERF_SEL_WAVES_LT_48                  = 0x00000010,
15576  SQ_PERF_SEL_WAVES_LT_32                  = 0x00000011,
15577  SQ_PERF_SEL_WAVES_LT_16                  = 0x00000012,
15578  SQ_PERF_SEL_WAVES_RESTORED               = 0x00000013,
15579  SQ_PERF_SEL_WAVES_SAVED                  = 0x00000014,
15580  SQ_PERF_SEL_MSG                          = 0x00000015,
15581  SQ_PERF_SEL_MSG_INTERRUPT                = 0x00000016,
15582  SQ_PERF_SEL_WAVES_INITIAL_PREFETCH       = 0x00000017,
15583  SQ_PERF_SEL_WAVE_CYCLES                  = 0x00000018,
15584  SQ_PERF_SEL_WAVE_READY                   = 0x00000019,
15585  SQ_PERF_SEL_WAIT_INST_ANY                = 0x0000001a,
15586  SQ_PERF_SEL_WAIT_INST_VALU               = 0x0000001b,
15587  SQ_PERF_SEL_WAIT_INST_SCA                = 0x0000001c,
15588  SQ_PERF_SEL_WAIT_INST_LDS                = 0x0000001d,
15589  SQ_PERF_SEL_WAIT_INST_TEX                = 0x0000001e,
15590  SQ_PERF_SEL_WAIT_INST_FLAT               = 0x0000001f,
15591  SQ_PERF_SEL_WAIT_INST_VMEM               = 0x00000020,
15592  SQ_PERF_SEL_WAIT_INST_EXP_GDS            = 0x00000021,
15593  SQ_PERF_SEL_WAIT_INST_BR_MSG             = 0x00000022,
15594  SQ_PERF_SEL_WAIT_ANY                     = 0x00000023,
15595  SQ_PERF_SEL_WAIT_CNT_ANY                 = 0x00000024,
15596  SQ_PERF_SEL_WAIT_CNT_VMVS                = 0x00000025,
15597  SQ_PERF_SEL_WAIT_CNT_LGKM                = 0x00000026,
15598  SQ_PERF_SEL_WAIT_CNT_EXP                 = 0x00000027,
15599  SQ_PERF_SEL_WAIT_TTRACE                  = 0x00000028,
15600  SQ_PERF_SEL_WAIT_IFETCH                  = 0x00000029,
15601  SQ_PERF_SEL_WAIT_BARRIER                 = 0x0000002a,
15602  SQ_PERF_SEL_WAIT_EXP_ALLOC               = 0x0000002b,
15603  SQ_PERF_SEL_WAIT_SLEEP                   = 0x0000002c,
15604  SQ_PERF_SEL_WAIT_DELAY_ALU               = 0x0000002d,
15605  SQ_PERF_SEL_WAIT_DEPCTR                  = 0x0000002e,
15606  SQ_PERF_SEL_WAIT_OTHER                   = 0x0000002f,
15607  SQ_PERF_SEL_INSTS_ALL                    = 0x00000030,
15608  SQ_PERF_SEL_INSTS_BRANCH                 = 0x00000031,
15609  SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN      = 0x00000032,
15610  SQ_PERF_SEL_INSTS_CBRANCH_TAKEN          = 0x00000033,
15611  SQ_PERF_SEL_INSTS_CBRANCH_TAKEN_HIT_IS   = 0x00000034,
15612  SQ_PERF_SEL_INSTS_EXP_GDS                = 0x00000035,
15613  SQ_PERF_SEL_INSTS_GDS                    = 0x00000036,
15614  SQ_PERF_SEL_INSTS_EXP                    = 0x00000037,
15615  SQ_PERF_SEL_INSTS_FLAT                   = 0x00000038,
15616  SQ_PERF_SEL_INSTS_LDS                    = 0x00000039,
15617  SQ_PERF_SEL_INSTS_SALU                   = 0x0000003a,
15618  SQ_PERF_SEL_INSTS_SMEM                   = 0x0000003b,
15619  SQ_PERF_SEL_INSTS_SMEM_NORM              = 0x0000003c,
15620  SQ_PERF_SEL_INSTS_SENDMSG                = 0x0000003d,
15621  SQ_PERF_SEL_INSTS_VALU                   = 0x0000003e,
15622  SQ_PERF_SEL_INSTS_VALU_TRANS32           = 0x0000003f,
15623  SQ_PERF_SEL_INSTS_VALU_NO_COEXEC         = 0x00000040,
15624  SQ_PERF_SEL_INSTS_TEX                    = 0x00000041,
15625  SQ_PERF_SEL_INSTS_TEX_LOAD               = 0x00000042,
15626  SQ_PERF_SEL_INSTS_TEX_STORE              = 0x00000043,
15627  SQ_PERF_SEL_INSTS_DELAY_ALU              = 0x00000044,
15628  SQ_PERF_SEL_INSTS_INTERNAL               = 0x00000045,
15629  SQ_PERF_SEL_INSTS_WAVE32                 = 0x00000046,
15630  SQ_PERF_SEL_INSTS_WAVE32_FLAT            = 0x00000047,
15631  SQ_PERF_SEL_INSTS_WAVE32_LDS             = 0x00000048,
15632  SQ_PERF_SEL_INSTS_WAVE32_VALU            = 0x00000049,
15633  SQ_PERF_SEL_WAVE32_INSTS_EXP_GDS         = 0x0000004a,
15634  SQ_PERF_SEL_INSTS_WAVE32_VALU_TRANS32    = 0x0000004b,
15635  SQ_PERF_SEL_INSTS_WAVE32_VALU_NO_COEXEC  = 0x0000004c,
15636  SQ_PERF_SEL_INSTS_WAVE32_TEX             = 0x0000004d,
15637  SQ_PERF_SEL_INSTS_WAVE32_TEX_LOAD        = 0x0000004e,
15638  SQ_PERF_SEL_INSTS_WAVE32_TEX_STORE       = 0x0000004f,
15639  SQ_PERF_SEL_ITEM_CYCLES_VALU             = 0x00000050,
15640  SQ_PERF_SEL_VALU_READWRITELANE_CYCLES    = 0x00000051,
15641  SQ_PERF_SEL_WAVE32_INSTS                 = 0x00000052,
15642  SQ_PERF_SEL_WAVE64_INSTS                 = 0x00000053,
15643  SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED      = 0x00000054,
15644  SQ_PERF_SEL_WAVE64_HALF_SKIP             = 0x00000055,
15645  SQ_PERF_SEL_INST_LEVEL_EXP               = 0x00000056,
15646  SQ_PERF_SEL_INST_LEVEL_GDS               = 0x00000057,
15647  SQ_PERF_SEL_INST_LEVEL_LDS               = 0x00000058,
15648  SQ_PERF_SEL_INST_LEVEL_SMEM              = 0x00000059,
15649  SQ_PERF_SEL_INST_LEVEL_TEX_LOAD          = 0x0000005a,
15650  SQ_PERF_SEL_INST_LEVEL_TEX_STORE         = 0x0000005b,
15651  SQ_PERF_SEL_IFETCH_REQS                  = 0x0000005c,
15652  SQ_PERF_SEL_IFETCH_LEVEL                 = 0x0000005d,
15653  SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL = 0x0000005e,
15654  SQ_PERF_SEL_VALU_SGATHER_STALL           = 0x0000005f,
15655  SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL   = 0x00000060,
15656  SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL = 0x00000061,
15657  SQ_PERF_SEL_VALU_SGATHER_FULL_STALL      = 0x00000062,
15658  SQ_PERF_SEL_SALU_SGATHER_STALL           = 0x00000063,
15659  SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL = 0x00000064,
15660  SQ_PERF_SEL_SALU_GATHER_FULL_STALL       = 0x00000065,
15661  SQ_PERF_SEL_SMEM_DCACHE_FIFO_FULL_STALL  = 0x00000066,
15662  SQ_PERF_SEL_INST_CYCLES_VALU             = 0x00000067,
15663  SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32     = 0x00000068,
15664  SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC   = 0x00000069,
15665  SQ_PERF_SEL_INST_CYCLES_VMEM             = 0x0000006a,
15666  SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD        = 0x0000006b,
15667  SQ_PERF_SEL_INST_CYCLES_VMEM_STORE       = 0x0000006c,
15668  SQ_PERF_SEL_INST_CYCLES_LDS              = 0x0000006d,
15669  SQ_PERF_SEL_INST_CYCLES_TEX              = 0x0000006e,
15670  SQ_PERF_SEL_INST_CYCLES_FLAT             = 0x0000006f,
15671  SQ_PERF_SEL_INST_CYCLES_EXP_GDS          = 0x00000070,
15672  SQ_PERF_SEL_INST_CYCLES_EXP              = 0x00000071,
15673  SQ_PERF_SEL_INST_CYCLES_GDS              = 0x00000072,
15674  SQ_PERF_SEL_VALU_STARVE                  = 0x00000073,
15675  SQ_PERF_SEL_VMEM_ARB_FIFO_FULL           = 0x00000074,
15676  SQ_PERF_SEL_MSG_FIFO_FULL_STALL          = 0x00000075,
15677  SQ_PERF_SEL_EXP_REQ_FIFO_FULL            = 0x00000076,
15678  SQ_PERF_SEL_VMEM_BUS_ACTIVE              = 0x00000077,
15679  SQ_PERF_SEL_VMEM_BUS_STALL               = 0x00000078,
15680  SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL = 0x00000079,
15681  SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL = 0x0000007a,
15682  SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL = 0x0000007b,
15683  SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL = 0x0000007c,
15684  SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY    = 0x0000007d,
15685  SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY   = 0x0000007e,
15686  SQ_PERF_SEL_SALU_PIPE_STALL              = 0x0000007f,
15687  SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES    = 0x00000080,
15688  SQ_PERF_SEL_MSG_BUS_BUSY                 = 0x00000081,
15689  SQ_PERF_SEL_EXP_REQ_BUS_STALL            = 0x00000082,
15690  SQ_PERF_SEL_EXP_REQ0_BUS_BUSY            = 0x00000083,
15691  SQ_PERF_SEL_EXP_REQ1_BUS_BUSY            = 0x00000084,
15692  SQ_PERF_SEL_EXP_BUS0_BUSY                = 0x00000085,
15693  SQ_PERF_SEL_EXP_BUS1_BUSY                = 0x00000086,
15694  SQ_PERF_SEL_INST_CACHE_REQ_STALL         = 0x00000087,
15695  SQ_PERF_SEL_USER0                        = 0x00000088,
15696  SQ_PERF_SEL_USER1                        = 0x00000089,
15697  SQ_PERF_SEL_USER2                        = 0x0000008a,
15698  SQ_PERF_SEL_USER3                        = 0x0000008b,
15699  SQ_PERF_SEL_USER4                        = 0x0000008c,
15700  SQ_PERF_SEL_USER5                        = 0x0000008d,
15701  SQ_PERF_SEL_USER6                        = 0x0000008e,
15702  SQ_PERF_SEL_USER7                        = 0x0000008f,
15703  SQ_PERF_SEL_USER8                        = 0x00000090,
15704  SQ_PERF_SEL_USER9                        = 0x00000091,
15705  SQ_PERF_SEL_USER10                       = 0x00000092,
15706  SQ_PERF_SEL_USER11                       = 0x00000093,
15707  SQ_PERF_SEL_USER12                       = 0x00000094,
15708  SQ_PERF_SEL_USER13                       = 0x00000095,
15709  SQ_PERF_SEL_USER14                       = 0x00000096,
15710  SQ_PERF_SEL_USER15                       = 0x00000097,
15711  SQ_PERF_SEL_USER_LEVEL0                  = 0x00000098,
15712  SQ_PERF_SEL_USER_LEVEL1                  = 0x00000099,
15713  SQ_PERF_SEL_USER_LEVEL2                  = 0x0000009a,
15714  SQ_PERF_SEL_USER_LEVEL3                  = 0x0000009b,
15715  SQ_PERF_SEL_USER_LEVEL4                  = 0x0000009c,
15716  SQ_PERF_SEL_USER_LEVEL5                  = 0x0000009d,
15717  SQ_PERF_SEL_USER_LEVEL6                  = 0x0000009e,
15718  SQ_PERF_SEL_USER_LEVEL7                  = 0x0000009f,
15719  SQ_PERF_SEL_USER_LEVEL8                  = 0x000000a0,
15720  SQ_PERF_SEL_USER_LEVEL9                  = 0x000000a1,
15721  SQ_PERF_SEL_USER_LEVEL10                 = 0x000000a2,
15722  SQ_PERF_SEL_USER_LEVEL11                 = 0x000000a3,
15723  SQ_PERF_SEL_USER_LEVEL12                 = 0x000000a4,
15724  SQ_PERF_SEL_USER_LEVEL13                 = 0x000000a5,
15725  SQ_PERF_SEL_USER_LEVEL14                 = 0x000000a6,
15726  SQ_PERF_SEL_USER_LEVEL15                 = 0x000000a7,
15727  SQ_PERF_SEL_VALU_RETURN_SDST             = 0x000000a8,
15728  SQ_PERF_SEL_VMEM_VGPR_READ_STALLED_BY_EXPORT = 0x000000a9,
15729  SQ_PERF_SEL_INSTS_VALU_TRANS             = 0x000000aa,
15730  SQ_PERF_SEL_INSTS_LDS_DIRECT_LOAD        = 0x000000ab,
15731  SQ_PERF_SEL_INSTS_LDS_PARAM_LOAD         = 0x000000ac,
15732  SQ_PERF_SEL_INSTS_WAVE32_LDS_PARAM_LOAD  = 0x000000ad,
15733  SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64  = 0x000000ae,
15734  SQ_PERF_SEL_INSTS_VALU_VINTERP           = 0x000000af,
15735  SQ_PERF_SEL_INSTS_VALU_WAVE32_VINTERP    = 0x000000b0,
15736  SQ_PERF_SEL_OVERFLOW_PREV                = 0x000000b1,
15737  SQ_PERF_SEL_INSTS_DUAL_VALU_WAVE32       = 0x000000b2,
15738  SQ_PERF_SEL_INSTS_VALU_1_PASS            = 0x000000b3,
15739  SQ_PERF_SEL_INSTS_VALU_2_PASS            = 0x000000b4,
15740  SQ_PERF_SEL_INSTS_VALU_4_PASS            = 0x000000b5,
15741  SQ_PERF_SEL_INSTS_VALU_DP                = 0x000000b6,
15742  SQ_PERF_SEL_SP_CONST_CYCLES              = 0x000000b7,
15743  SQ_PERF_SEL_SP_CONST_STALL_CYCLES        = 0x000000b8,
15744  SQ_PERF_SEL_ITEMS_VALU                   = 0x000000b9,
15745  SQ_PERF_SEL_ITEMS_MAX_VALU               = 0x000000ba,
15746  SQ_PERF_SEL_ITEM_CYCLES_VMEM             = 0x000000bb,
15747  SQ_PERF_SEL_DUMMY_END                    = 0x000000bc,
15748  SQ_PERF_SEL_DUMMY_LAST                   = 0x000000ff,
15749  SQC_PERF_SEL_LDS_BANK_CONFLICT           = 0x00000100,
15750  SQC_PERF_SEL_LDS_ADDR_CONFLICT           = 0x00000101,
15751  SQC_PERF_SEL_LDS_UNALIGNED_STALL         = 0x00000102,
15752  SQC_PERF_SEL_LDS_MEM_VIOLATIONS          = 0x00000103,
15753  SQC_PERF_SEL_LDS_ATOMIC_RETURN           = 0x00000104,
15754  SQC_PERF_SEL_LDS_IDX_ACTIVE              = 0x00000105,
15755  SQC_PERF_SEL_LDS_ADDR_STALL              = 0x00000106,
15756  SQC_PERF_SEL_LDS_ADDR_ACTIVE             = 0x00000107,
15757  SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD   = 0x00000108,
15758  SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD = 0x00000109,
15759  SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL    = 0x0000010a,
15760  SQC_PERF_SEL_LDS_FP_ADD_CYCLES           = 0x0000010b,
15761  SQC_PERF_SEL_ICACHE_BUSY_CYCLES          = 0x0000010c,
15762  SQC_PERF_SEL_ICACHE_REQ                  = 0x0000010d,
15763  SQC_PERF_SEL_ICACHE_HITS                 = 0x0000010e,
15764  SQC_PERF_SEL_ICACHE_MISSES               = 0x0000010f,
15765  SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE     = 0x00000110,
15766  SQC_PERF_SEL_ICACHE_INVAL_INST           = 0x00000111,
15767  SQC_PERF_SEL_ICACHE_INVAL_ASYNC          = 0x00000112,
15768  SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL       = 0x00000113,
15769  SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL       = 0x00000114,
15770  SQC_PERF_SEL_TC_INFLIGHT_LEVEL           = 0x00000115,
15771  SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL    = 0x00000116,
15772  SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL    = 0x00000117,
15773  SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB   = 0x00000118,
15774  SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB   = 0x00000119,
15775  SQC_PERF_SEL_TC_REQ                      = 0x0000011a,
15776  SQC_PERF_SEL_TC_INST_REQ                 = 0x0000011b,
15777  SQC_PERF_SEL_TC_DATA_READ_REQ            = 0x0000011c,
15778  SQC_PERF_SEL_TC_STALL                    = 0x0000011d,
15779  SQC_PERF_SEL_TC_STARVE                   = 0x0000011e,
15780  SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 0x0000011f,
15781  SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 0x00000120,
15782  SQC_PERF_SEL_ICACHE_CACHE_STALLED        = 0x00000121,
15783  SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 0x00000122,
15784  SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0x00000123,
15785  SQC_PERF_SEL_DCACHE_BUSY_CYCLES          = 0x00000124,
15786  SQC_PERF_SEL_DCACHE_REQ                  = 0x00000125,
15787  SQC_PERF_SEL_DCACHE_HITS                 = 0x00000126,
15788  SQC_PERF_SEL_DCACHE_MISSES               = 0x00000127,
15789  SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE     = 0x00000128,
15790  SQC_PERF_SEL_DCACHE_INVAL_INST           = 0x00000129,
15791  SQC_PERF_SEL_DCACHE_INVAL_ASYNC          = 0x0000012a,
15792  SQC_PERF_SEL_DCACHE_HIT_LRU_READ         = 0x0000012b,
15793  SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 0x0000012c,
15794  SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 0x0000012d,
15795  SQC_PERF_SEL_DCACHE_CACHE_STALLED        = 0x0000012e,
15796  SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 0x0000012f,
15797  SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT   = 0x00000130,
15798  SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0x00000131,
15799  SQC_PERF_SEL_DCACHE_REQ_READ_1           = 0x00000132,
15800  SQC_PERF_SEL_DCACHE_REQ_READ_2           = 0x00000133,
15801  SQC_PERF_SEL_DCACHE_REQ_READ_4           = 0x00000134,
15802  SQC_PERF_SEL_DCACHE_REQ_READ_8           = 0x00000135,
15803  SQC_PERF_SEL_DCACHE_REQ_READ_16          = 0x00000136,
15804  SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE        = 0x00000137,
15805  SQC_PERF_SEL_SQ_DCACHE_REQS              = 0x00000138,
15806  SQC_PERF_SEL_DCACHE_FLAT_REQ             = 0x00000139,
15807  SQC_PERF_SEL_TD_VGPR_BUSY                = 0x0000013a,
15808  SQC_PERF_SEL_LDS_VGPR_BUSY               = 0x0000013b,
15809  SQC_PERF_SEL_LDS_TD_VGPR_CONF_STALL      = 0x0000013c,
15810  SQC_PERF_SEL_ICACHE_GCR                  = 0x0000013d,
15811  SQC_PERF_SEL_ICACHE_GCR_HITS             = 0x0000013e,
15812  SQC_PERF_SEL_DCACHE_GCR                  = 0x0000013f,
15813  SQC_PERF_SEL_DCACHE_GCR_HITS             = 0x00000140,
15814  SQC_PERF_SEL_ICACHE_GCR_INVALIDATE       = 0x00000141,
15815  SQC_PERF_SEL_DCACHE_GCR_INVALIDATE       = 0x00000142,
15816  SQC_PERF_SEL_DCACHE_SPI_RETURN_STALL     = 0x00000143,
15817  SQC_PERF_SEL_DUMMY_LAST                  = 0x00000144,
15818  SP_PERF_SEL_DST_BUF_ALLOC_STALL          = 0x000001c0,
15819  SP_PERF_SEL_DST_BUF_WB_CONF_W_TD_LDS     = 0x000001c1,
15820  SP_PERF_SEL_DST_BUF_WB_CONF_W_SPI        = 0x000001c2,
15821  SP_PERF_SEL_DST_BUF_EVEN_DIRTY           = 0x000001c3,
15822  SP_PERF_SEL_DST_BUF_ODD_DIRTY            = 0x000001c4,
15823  SP_PERF_SEL_SRC_CACHE_HIT_B0             = 0x000001c5,
15824  SP_PERF_SEL_SRC_CACHE_HIT_B1             = 0x000001c6,
15825  SP_PERF_SEL_SRC_CACHE_HIT_B2             = 0x000001c7,
15826  SP_PERF_SEL_SRC_CACHE_HIT_B3             = 0x000001c8,
15827  SP_PERF_SEL_SRC_CACHE_PROBE_B0           = 0x000001c9,
15828  SP_PERF_SEL_SRC_CACHE_PROBE_B1           = 0x000001ca,
15829  SP_PERF_SEL_SRC_CACHE_PROBE_B2           = 0x000001cb,
15830  SP_PERF_SEL_SRC_CACHE_PROBE_B3           = 0x000001cc,
15831  SP_PERF_SEL_SRC_CACHE_VGPR_RD_B0         = 0x000001cd,
15832  SP_PERF_SEL_SRC_CACHE_VGPR_RD_B1         = 0x000001ce,
15833  SP_PERF_SEL_SRC_CACHE_VGPR_RD_B2         = 0x000001cf,
15834  SP_PERF_SEL_SRC_CACHE_VGPR_RD_B3         = 0x000001d0,
15835  SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B0     = 0x000001d1,
15836  SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B1     = 0x000001d2,
15837  SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B2     = 0x000001d3,
15838  SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B3     = 0x000001d4,
15839  SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B0   = 0x000001d5,
15840  SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B1   = 0x000001d6,
15841  SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B2   = 0x000001d7,
15842  SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B3   = 0x000001d8,
15843  SP_PERF_SEL_VALU_PENDING_QUEUE_STALL     = 0x000001d9,
15844  SP_PERF_SEL_VALU_OPERAND                 = 0x000001da,
15845  SP_PERF_SEL_VALU_VGPR_OPERAND            = 0x000001db,
15846  SP_PERF_SEL_VALU_OPERAND_FROM_DST_BUF    = 0x000001dc,
15847  SP_PERF_SEL_VALU_EXEC_MASK_CHANGE        = 0x000001dd,
15848  SP_PERF_SEL_VALU_COEXEC_WITH_TRANS       = 0x000001de,
15849  SP_PERF_SEL_VALU_SGPR_FWD_BUF_FULL       = 0x000001df,
15850  SP_PERF_SEL_VALU_STALL                   = 0x000001e0,
15851  SP_PERF_SEL_VALU_STALL_VGPR_NOT_READY    = 0x000001e1,
15852  SP_PERF_SEL_VALU_STALL_SGPR_NOT_READY    = 0x000001e2,
15853  SP_PERF_SEL_VALU_STALL_VDST_FWD          = 0x000001e3,
15854  SP_PERF_SEL_VALU_STALL_SDST_FWD          = 0x000001e4,
15855  SP_PERF_SEL_VALU_STALL_DST_STALL         = 0x000001e5,
15856  SP_PERF_SEL_VALU_FAST_OP_STALL_VGPR_NOT_READY = 0x000001e6,
15857  SP_PERF_SEL_VGPR_VMEM_RD                 = 0x000001e7,
15858  SP_PERF_SEL_VGPR_EXP_RD                  = 0x000001e8,
15859  SP_PERF_SEL_VGPR_SPI_WR                  = 0x000001e9,
15860  SP_PERF_SEL_VGPR_TDLDS_DATA_WR           = 0x000001ea,
15861  SP_PERF_SEL_VGPR_WR                      = 0x000001eb,
15862  SP_PERF_SEL_VGPR_RD                      = 0x000001ec,
15863  SP_PERF_SEL_DUMMY_LAST                   = 0x000001ed,
15864  SQ_PERF_SEL_NONE2                        = 0x000001ff,
15865  } SQ_PERF_SEL;
15866  
15867  /*
15868   * SQ_ROUND_MODE enum
15869   */
15870  
15871  typedef enum SQ_ROUND_MODE {
15872  SQ_ROUND_NEAREST_EVEN                    = 0x00000000,
15873  SQ_ROUND_PLUS_INFINITY                   = 0x00000001,
15874  SQ_ROUND_MINUS_INFINITY                  = 0x00000002,
15875  SQ_ROUND_TO_ZERO                         = 0x00000003,
15876  } SQ_ROUND_MODE;
15877  
15878  /*
15879   * SQ_RSRC_BUF_TYPE enum
15880   */
15881  
15882  typedef enum SQ_RSRC_BUF_TYPE {
15883  SQ_RSRC_BUF                              = 0x00000000,
15884  SQ_RSRC_BUF_RSVD_1                       = 0x00000001,
15885  SQ_RSRC_BUF_RSVD_2                       = 0x00000002,
15886  SQ_RSRC_BUF_RSVD_3                       = 0x00000003,
15887  } SQ_RSRC_BUF_TYPE;
15888  
15889  /*
15890   * SQ_RSRC_FLAT_TYPE enum
15891   */
15892  
15893  typedef enum SQ_RSRC_FLAT_TYPE {
15894  SQ_RSRC_FLAT_RSVD_0                      = 0x00000000,
15895  SQ_RSRC_FLAT                             = 0x00000001,
15896  SQ_RSRC_FLAT_RSVD_2                      = 0x00000002,
15897  SQ_RSRC_FLAT_RSVD_3                      = 0x00000003,
15898  } SQ_RSRC_FLAT_TYPE;
15899  
15900  /*
15901   * SQ_RSRC_IMG_TYPE enum
15902   */
15903  
15904  typedef enum SQ_RSRC_IMG_TYPE {
15905  SQ_RSRC_IMG_RSVD_0                       = 0x00000000,
15906  SQ_RSRC_IMG_RSVD_1                       = 0x00000001,
15907  SQ_RSRC_IMG_RSVD_2                       = 0x00000002,
15908  SQ_RSRC_IMG_RSVD_3                       = 0x00000003,
15909  SQ_RSRC_IMG_RSVD_4                       = 0x00000004,
15910  SQ_RSRC_IMG_RSVD_5                       = 0x00000005,
15911  SQ_RSRC_IMG_RSVD_6                       = 0x00000006,
15912  SQ_RSRC_IMG_RSVD_7                       = 0x00000007,
15913  SQ_RSRC_IMG_1D                           = 0x00000008,
15914  SQ_RSRC_IMG_2D                           = 0x00000009,
15915  SQ_RSRC_IMG_3D                           = 0x0000000a,
15916  SQ_RSRC_IMG_CUBE                         = 0x0000000b,
15917  SQ_RSRC_IMG_1D_ARRAY                     = 0x0000000c,
15918  SQ_RSRC_IMG_2D_ARRAY                     = 0x0000000d,
15919  SQ_RSRC_IMG_2D_MSAA                      = 0x0000000e,
15920  SQ_RSRC_IMG_2D_MSAA_ARRAY                = 0x0000000f,
15921  } SQ_RSRC_IMG_TYPE;
15922  
15923  /*
15924   * SQ_SEL_XYZW01 enum
15925   */
15926  
15927  typedef enum SQ_SEL_XYZW01 {
15928  SQ_SEL_0                                 = 0x00000000,
15929  SQ_SEL_1                                 = 0x00000001,
15930  SQ_SEL_N_BC_1                            = 0x00000002,
15931  SQ_SEL_RESERVED_1                        = 0x00000003,
15932  SQ_SEL_X                                 = 0x00000004,
15933  SQ_SEL_Y                                 = 0x00000005,
15934  SQ_SEL_Z                                 = 0x00000006,
15935  SQ_SEL_W                                 = 0x00000007,
15936  } SQ_SEL_XYZW01;
15937  
15938  /*
15939   * SQ_TEX_ANISO_RATIO enum
15940   */
15941  
15942  typedef enum SQ_TEX_ANISO_RATIO {
15943  SQ_TEX_ANISO_RATIO_1                     = 0x00000000,
15944  SQ_TEX_ANISO_RATIO_2                     = 0x00000001,
15945  SQ_TEX_ANISO_RATIO_4                     = 0x00000002,
15946  SQ_TEX_ANISO_RATIO_8                     = 0x00000003,
15947  SQ_TEX_ANISO_RATIO_16                    = 0x00000004,
15948  } SQ_TEX_ANISO_RATIO;
15949  
15950  /*
15951   * SQ_TEX_BORDER_COLOR enum
15952   */
15953  
15954  typedef enum SQ_TEX_BORDER_COLOR {
15955  SQ_TEX_BORDER_COLOR_TRANS_BLACK          = 0x00000000,
15956  SQ_TEX_BORDER_COLOR_OPAQUE_BLACK         = 0x00000001,
15957  SQ_TEX_BORDER_COLOR_OPAQUE_WHITE         = 0x00000002,
15958  SQ_TEX_BORDER_COLOR_REGISTER             = 0x00000003,
15959  } SQ_TEX_BORDER_COLOR;
15960  
15961  /*
15962   * SQ_TEX_CLAMP enum
15963   */
15964  
15965  typedef enum SQ_TEX_CLAMP {
15966  SQ_TEX_WRAP                              = 0x00000000,
15967  SQ_TEX_MIRROR                            = 0x00000001,
15968  SQ_TEX_CLAMP_LAST_TEXEL                  = 0x00000002,
15969  SQ_TEX_MIRROR_ONCE_LAST_TEXEL            = 0x00000003,
15970  SQ_TEX_CLAMP_HALF_BORDER                 = 0x00000004,
15971  SQ_TEX_MIRROR_ONCE_HALF_BORDER           = 0x00000005,
15972  SQ_TEX_CLAMP_BORDER                      = 0x00000006,
15973  SQ_TEX_MIRROR_ONCE_BORDER                = 0x00000007,
15974  } SQ_TEX_CLAMP;
15975  
15976  /*
15977   * SQ_TEX_DEPTH_COMPARE enum
15978   */
15979  
15980  typedef enum SQ_TEX_DEPTH_COMPARE {
15981  SQ_TEX_DEPTH_COMPARE_NEVER               = 0x00000000,
15982  SQ_TEX_DEPTH_COMPARE_LESS                = 0x00000001,
15983  SQ_TEX_DEPTH_COMPARE_EQUAL               = 0x00000002,
15984  SQ_TEX_DEPTH_COMPARE_LESSEQUAL           = 0x00000003,
15985  SQ_TEX_DEPTH_COMPARE_GREATER             = 0x00000004,
15986  SQ_TEX_DEPTH_COMPARE_NOTEQUAL            = 0x00000005,
15987  SQ_TEX_DEPTH_COMPARE_GREATEREQUAL        = 0x00000006,
15988  SQ_TEX_DEPTH_COMPARE_ALWAYS              = 0x00000007,
15989  } SQ_TEX_DEPTH_COMPARE;
15990  
15991  /*
15992   * SQ_TEX_MIP_FILTER enum
15993   */
15994  
15995  typedef enum SQ_TEX_MIP_FILTER {
15996  SQ_TEX_MIP_FILTER_NONE                   = 0x00000000,
15997  SQ_TEX_MIP_FILTER_POINT                  = 0x00000001,
15998  SQ_TEX_MIP_FILTER_LINEAR                 = 0x00000002,
15999  SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ        = 0x00000003,
16000  } SQ_TEX_MIP_FILTER;
16001  
16002  /*
16003   * SQ_TEX_XY_FILTER enum
16004   */
16005  
16006  typedef enum SQ_TEX_XY_FILTER {
16007  SQ_TEX_XY_FILTER_POINT                   = 0x00000000,
16008  SQ_TEX_XY_FILTER_BILINEAR                = 0x00000001,
16009  SQ_TEX_XY_FILTER_ANISO_POINT             = 0x00000002,
16010  SQ_TEX_XY_FILTER_ANISO_BILINEAR          = 0x00000003,
16011  } SQ_TEX_XY_FILTER;
16012  
16013  /*
16014   * SQ_TEX_Z_FILTER enum
16015   */
16016  
16017  typedef enum SQ_TEX_Z_FILTER {
16018  SQ_TEX_Z_FILTER_NONE                     = 0x00000000,
16019  SQ_TEX_Z_FILTER_POINT                    = 0x00000001,
16020  SQ_TEX_Z_FILTER_LINEAR                   = 0x00000002,
16021  } SQ_TEX_Z_FILTER;
16022  
16023  /*
16024   * SQ_TT_MODE enum
16025   */
16026  
16027  typedef enum SQ_TT_MODE {
16028  SQ_TT_MODE_OFF                           = 0x00000000,
16029  SQ_TT_MODE_ON                            = 0x00000001,
16030  SQ_TT_MODE_GLOBAL                        = 0x00000002,
16031  SQ_TT_MODE_DETAIL                        = 0x00000003,
16032  } SQ_TT_MODE;
16033  
16034  /*
16035   * SQ_TT_RT_FREQ enum
16036   */
16037  
16038  typedef enum SQ_TT_RT_FREQ {
16039  SQ_TT_RT_FREQ_NEVER                      = 0x00000000,
16040  SQ_TT_RT_FREQ_1024_CLK                   = 0x00000001,
16041  SQ_TT_RT_FREQ_4096_CLK                   = 0x00000002,
16042  } SQ_TT_RT_FREQ;
16043  
16044  /*
16045   * SQ_TT_TOKEN_MASK_INST_EXCLUDE enum
16046   */
16047  
16048  typedef enum SQ_TT_TOKEN_MASK_INST_EXCLUDE {
16049  SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_BIT   = 0x00000001,
16050  SQ_TT_INST_EXCLUDE_EXPGNT234_BIT         = 0x00000002,
16051  } SQ_TT_TOKEN_MASK_INST_EXCLUDE;
16052  
16053  /*
16054   * SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT enum
16055   */
16056  
16057  typedef enum SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT {
16058  SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_SHIFT = 0x00000000,
16059  SQ_TT_INST_EXCLUDE_EXPGNT234_SHIFT       = 0x00000001,
16060  } SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT;
16061  
16062  /*
16063   * SQ_TT_TOKEN_MASK_REG_EXCLUDE enum
16064   */
16065  
16066  typedef enum SQ_TT_TOKEN_MASK_REG_EXCLUDE {
16067  SQ_TT_REG_EXCLUDE_USER_DATA_BIT          = 0x00000001,
16068  SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_BIT     = 0x00000002,
16069  SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_BIT = 0x00000004,
16070  } SQ_TT_TOKEN_MASK_REG_EXCLUDE;
16071  
16072  /*
16073   * SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT enum
16074   */
16075  
16076  typedef enum SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT {
16077  SQ_TT_REG_EXCLUDE_USER_DATA_SHIFT        = 0x00000000,
16078  SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_SHIFT   = 0x00000001,
16079  SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_SHIFT = 0x00000002,
16080  } SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT;
16081  
16082  /*
16083   * SQ_TT_TOKEN_MASK_REG_INCLUDE enum
16084   */
16085  
16086  typedef enum SQ_TT_TOKEN_MASK_REG_INCLUDE {
16087  SQ_TT_TOKEN_MASK_SQDEC_BIT               = 0x00000001,
16088  SQ_TT_TOKEN_MASK_SHDEC_BIT               = 0x00000002,
16089  SQ_TT_TOKEN_MASK_GFXUDEC_BIT             = 0x00000004,
16090  SQ_TT_TOKEN_MASK_COMP_BIT                = 0x00000008,
16091  SQ_TT_TOKEN_MASK_CONTEXT_BIT             = 0x00000010,
16092  SQ_TT_TOKEN_MASK_CONFIG_BIT              = 0x00000020,
16093  SQ_TT_TOKEN_MASK_ALL_BIT                 = 0x00000040,
16094  SQ_TT_TOKEN_MASK_RSVD_BIT                = 0x00000080,
16095  } SQ_TT_TOKEN_MASK_REG_INCLUDE;
16096  
16097  /*
16098   * SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT enum
16099   */
16100  
16101  typedef enum SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT {
16102  SQ_TT_TOKEN_MASK_SQDEC_SHIFT             = 0x00000000,
16103  SQ_TT_TOKEN_MASK_SHDEC_SHIFT             = 0x00000001,
16104  SQ_TT_TOKEN_MASK_GFXUDEC_SHIFT           = 0x00000002,
16105  SQ_TT_TOKEN_MASK_COMP_SHIFT              = 0x00000003,
16106  SQ_TT_TOKEN_MASK_CONTEXT_SHIFT           = 0x00000004,
16107  SQ_TT_TOKEN_MASK_CONFIG_SHIFT            = 0x00000005,
16108  SQ_TT_TOKEN_MASK_ALL_SHIFT               = 0x00000006,
16109  SQ_TT_TOKEN_MASK_RSVD_SHIFT              = 0x00000007,
16110  } SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT;
16111  
16112  /*
16113   * SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT enum
16114   */
16115  
16116  typedef enum SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT {
16117  SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT       = 0x00000000,
16118  SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT        = 0x00000001,
16119  SQ_TT_TOKEN_EXCLUDE_VALUINST_SHIFT       = 0x00000002,
16120  SQ_TT_TOKEN_EXCLUDE_WAVERDY_SHIFT        = 0x00000003,
16121  SQ_TT_TOKEN_EXCLUDE_WAVESTARTEND_SHIFT   = 0x00000004,
16122  SQ_TT_TOKEN_EXCLUDE_IMMEDIATE_SHIFT      = 0x00000005,
16123  SQ_TT_TOKEN_EXCLUDE_REG_SHIFT            = 0x00000006,
16124  SQ_TT_TOKEN_EXCLUDE_EVENT_SHIFT          = 0x00000007,
16125  SQ_TT_TOKEN_EXCLUDE_INST_SHIFT           = 0x00000008,
16126  SQ_TT_TOKEN_EXCLUDE_UTILCTR_SHIFT        = 0x00000009,
16127  SQ_TT_TOKEN_EXCLUDE_WAVEALLOC_SHIFT      = 0x0000000a,
16128  SQ_TT_TOKEN_EXCLUDE_PERF_SHIFT           = 0x0000000b,
16129  } SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT;
16130  
16131  /*
16132   * SQ_TT_UTIL_TIMER enum
16133   */
16134  
16135  typedef enum SQ_TT_UTIL_TIMER {
16136  SQ_TT_UTIL_TIMER_100_CLK                 = 0x00000000,
16137  SQ_TT_UTIL_TIMER_250_CLK                 = 0x00000001,
16138  } SQ_TT_UTIL_TIMER;
16139  
16140  /*
16141   * SQ_TT_WAVESTART_MODE enum
16142   */
16143  
16144  typedef enum SQ_TT_WAVESTART_MODE {
16145  SQ_TT_WAVESTART_MODE_SHORT               = 0x00000000,
16146  SQ_TT_WAVESTART_MODE_ALLOC               = 0x00000001,
16147  SQ_TT_WAVESTART_MODE_PBB_ID              = 0x00000002,
16148  } SQ_TT_WAVESTART_MODE;
16149  
16150  /*
16151   * SQ_TT_WTYPE_INCLUDE enum
16152   */
16153  
16154  typedef enum SQ_TT_WTYPE_INCLUDE {
16155  SQ_TT_WTYPE_INCLUDE_PS_BIT               = 0x00000001,
16156  SQ_TT_WTYPE_INCLUDE_RSVD0_BIT            = 0x00000002,
16157  SQ_TT_WTYPE_INCLUDE_GS_BIT               = 0x00000004,
16158  SQ_TT_WTYPE_INCLUDE_RSVD1_BIT            = 0x00000008,
16159  SQ_TT_WTYPE_INCLUDE_HS_BIT               = 0x00000010,
16160  SQ_TT_WTYPE_INCLUDE_RSVD2_BIT            = 0x00000020,
16161  SQ_TT_WTYPE_INCLUDE_CS_BIT               = 0x00000040,
16162  } SQ_TT_WTYPE_INCLUDE;
16163  
16164  /*
16165   * SQ_TT_WTYPE_INCLUDE_SHIFT enum
16166   */
16167  
16168  typedef enum SQ_TT_WTYPE_INCLUDE_SHIFT {
16169  SQ_TT_WTYPE_INCLUDE_PS_SHIFT             = 0x00000000,
16170  SQ_TT_WTYPE_INCLUDE_RSVD0_SHIFT          = 0x00000001,
16171  SQ_TT_WTYPE_INCLUDE_GS_SHIFT             = 0x00000002,
16172  SQ_TT_WTYPE_INCLUDE_RSVD1_SHIFT          = 0x00000003,
16173  SQ_TT_WTYPE_INCLUDE_HS_SHIFT             = 0x00000004,
16174  SQ_TT_WTYPE_INCLUDE_RSVD2_SHIFT          = 0x00000005,
16175  SQ_TT_WTYPE_INCLUDE_CS_SHIFT             = 0x00000006,
16176  } SQ_TT_WTYPE_INCLUDE_SHIFT;
16177  
16178  /*
16179   * SQ_WATCH_MODES enum
16180   */
16181  
16182  typedef enum SQ_WATCH_MODES {
16183  SQ_WATCH_MODE_READ                       = 0x00000000,
16184  SQ_WATCH_MODE_NONREAD                    = 0x00000001,
16185  SQ_WATCH_MODE_ATOMIC                     = 0x00000002,
16186  SQ_WATCH_MODE_ALL                        = 0x00000003,
16187  } SQ_WATCH_MODES;
16188  
16189  /*
16190   * SQ_WAVE_FWD_PROG_INTERVAL enum
16191   */
16192  
16193  typedef enum SQ_WAVE_FWD_PROG_INTERVAL {
16194  SQ_WAVE_FWD_PROG_INTERVAL_NEVER          = 0x00000000,
16195  SQ_WAVE_FWD_PROG_INTERVAL_256            = 0x00000001,
16196  SQ_WAVE_FWD_PROG_INTERVAL_1024           = 0x00000002,
16197  SQ_WAVE_FWD_PROG_INTERVAL_4096           = 0x00000003,
16198  } SQ_WAVE_FWD_PROG_INTERVAL;
16199  
16200  /*
16201   * SQ_WAVE_IB_ECC_ST enum
16202   */
16203  
16204  typedef enum SQ_WAVE_IB_ECC_ST {
16205  SQ_WAVE_IB_ECC_CLEAN                     = 0x00000000,
16206  SQ_WAVE_IB_ECC_ERR_CONTINUE              = 0x00000001,
16207  SQ_WAVE_IB_ECC_ERR_HALT                  = 0x00000002,
16208  SQ_WAVE_IB_ECC_WITH_ERR_MSG              = 0x00000003,
16209  } SQ_WAVE_IB_ECC_ST;
16210  
16211  /*
16212   * SQ_WAVE_SCHED_MODES enum
16213   */
16214  
16215  typedef enum SQ_WAVE_SCHED_MODES {
16216  SQ_WAVE_SCHED_MODE_NORMAL                = 0x00000000,
16217  SQ_WAVE_SCHED_MODE_EXPERT                = 0x00000001,
16218  SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST       = 0x00000002,
16219  } SQ_WAVE_SCHED_MODES;
16220  
16221  /*
16222   * SQ_WAVE_TYPE enum
16223   */
16224  
16225  typedef enum SQ_WAVE_TYPE {
16226  SQ_WAVE_TYPE_PS                          = 0x00000000,
16227  SQ_WAVE_TYPE_RSVD0                       = 0x00000001,
16228  SQ_WAVE_TYPE_GS                          = 0x00000002,
16229  SQ_WAVE_TYPE_RSVD1                       = 0x00000003,
16230  SQ_WAVE_TYPE_HS                          = 0x00000004,
16231  SQ_WAVE_TYPE_RSVD2                       = 0x00000005,
16232  SQ_WAVE_TYPE_CS                          = 0x00000006,
16233  SQ_WAVE_TYPE_PS1                         = 0x00000007,
16234  SQ_WAVE_TYPE_PS2                         = 0x00000008,
16235  SQ_WAVE_TYPE_PS3                         = 0x00000009,
16236  } SQ_WAVE_TYPE;
16237  
16238  /*
16239   * SQ_WAVE_TYPE value
16240   */
16241  
16242  #define SQ_WAVE_TYPE_PS0               0x00000000
16243  
16244  /*
16245   * SQIND_PARTITIONS value
16246   */
16247  
16248  #define SQIND_GLOBAL_REGS_OFFSET       0x00000000
16249  #define SQIND_GLOBAL_REGS_SIZE         0x00000008
16250  #define SQIND_LOCAL_REGS_OFFSET        0x00000008
16251  #define SQIND_LOCAL_REGS_SIZE          0x00000008
16252  #define SQIND_WAVE_HWREGS_OFFSET       0x00000100
16253  #define SQIND_WAVE_HWREGS_SIZE         0x00000100
16254  #define SQIND_WAVE_SGPRS_OFFSET        0x00000200
16255  #define SQIND_WAVE_SGPRS_SIZE          0x00000200
16256  #define SQIND_WAVE_VGPRS_OFFSET        0x00000400
16257  #define SQIND_WAVE_VGPRS_SIZE          0x00000400
16258  
16259  /*
16260   * SQ_GFXDEC value
16261   */
16262  
16263  #define SQ_GFXDEC_BEGIN                0x0000a000
16264  #define SQ_GFXDEC_END                  0x0000c000
16265  #define SQ_GFXDEC_STATE_ID_SHIFT       0x0000000a
16266  
16267  /*
16268   * SQDEC value
16269   */
16270  
16271  #define SQDEC_BEGIN                    0x00002300
16272  #define SQDEC_END                      0x000023ff
16273  
16274  /*
16275   * SQPERFSDEC value
16276   */
16277  
16278  #define SQPERFSDEC_BEGIN               0x0000d9c0
16279  #define SQPERFSDEC_END                 0x0000da40
16280  
16281  /*
16282   * SQPERFDDEC value
16283   */
16284  
16285  #define SQPERFDDEC_BEGIN               0x0000d1c0
16286  #define SQPERFDDEC_END                 0x0000d240
16287  
16288  /*
16289   * SQGFXUDEC value
16290   */
16291  
16292  #define SQGFXUDEC_BEGIN                0x0000c330
16293  #define SQGFXUDEC_END                  0x0000c380
16294  
16295  /*
16296   * SQPWRDEC value
16297   */
16298  
16299  #define SQPWRDEC_BEGIN                 0x0000f08c
16300  #define SQPWRDEC_END                   0x0000f094
16301  
16302  /*
16303   * SQ_DISPATCHER value
16304   */
16305  
16306  #define SQ_DISPATCHER_GFX_MIN          0x00000010
16307  #define SQ_DISPATCHER_GFX_CNT_PER_RING 0x00000008
16308  
16309  /*
16310   * SQ_MAX value
16311   */
16312  
16313  #define SQ_MAX_PGM_SGPRS               0x00000068
16314  #define SQ_MAX_PGM_VGPRS               0x00000100
16315  
16316  /*
16317   * SQ_EXCP_BITS value
16318   */
16319  
16320  #define SQ_EX_MODE_EXCP_VALU_BASE      0x00000000
16321  #define SQ_EX_MODE_EXCP_VALU_SIZE      0x00000007
16322  #define SQ_EX_MODE_EXCP_INVALID        0x00000000
16323  #define SQ_EX_MODE_EXCP_INPUT_DENORM   0x00000001
16324  #define SQ_EX_MODE_EXCP_DIV0           0x00000002
16325  #define SQ_EX_MODE_EXCP_OVERFLOW       0x00000003
16326  #define SQ_EX_MODE_EXCP_UNDERFLOW      0x00000004
16327  #define SQ_EX_MODE_EXCP_INEXACT        0x00000005
16328  #define SQ_EX_MODE_EXCP_INT_DIV0       0x00000006
16329  #define SQ_EX_MODE_EXCP_ADDR_WATCH0    0x00000007
16330  #define SQ_EX_MODE_EXCP_MEM_VIOL       0x00000008
16331  
16332  /*
16333   * SQ_EXCP_HI_BITS value
16334   */
16335  
16336  #define SQ_EX_MODE_EXCP_HI_ADDR_WATCH1 0x00000000
16337  #define SQ_EX_MODE_EXCP_HI_ADDR_WATCH2 0x00000001
16338  #define SQ_EX_MODE_EXCP_HI_ADDR_WATCH3 0x00000002
16339  
16340  /*
16341   * HW_INSERTED_INST_ID value
16342   */
16343  
16344  #define INST_ID_PRIV_START             0x80000000
16345  #define INST_ID_ECC_INTERRUPT_MSG      0xfffffff0
16346  #define INST_ID_TTRACE_NEW_PC_MSG      0xfffffff1
16347  #define INST_ID_HW_TRAP                0xfffffff2
16348  #define INST_ID_KILL_SEQ               0xfffffff3
16349  #define INST_ID_SPI_WREXEC             0xfffffff4
16350  #define INST_ID_HW_TRAP_GET_TBA        0xfffffff5
16351  #define INST_ID_HOST_REG_TRAP_MSG      0xfffffffe
16352  
16353  /*
16354   * SIMM16_WAITCNT_PARTITIONS value
16355   */
16356  
16357  #define SIMM16_WAITCNT_EXP_CNT_START   0x00000000
16358  #define SIMM16_WAITCNT_EXP_CNT_SIZE    0x00000003
16359  #define SIMM16_WAITCNT_LGKM_CNT_START  0x00000004
16360  #define SIMM16_WAITCNT_LGKM_CNT_SIZE   0x00000006
16361  #define SIMM16_WAITCNT_VM_CNT_START    0x0000000a
16362  #define SIMM16_WAITCNT_VM_CNT_SIZE     0x00000006
16363  #define SIMM16_WAITCNT_DEPCTR_SA_SDST_START 0x00000000
16364  #define SIMM16_WAITCNT_DEPCTR_SA_SDST_SIZE 0x00000001
16365  #define SIMM16_WAITCNT_DEPCTR_VA_VCC_START 0x00000001
16366  #define SIMM16_WAITCNT_DEPCTR_VA_VCC_SIZE 0x00000001
16367  #define SIMM16_WAITCNT_DEPCTR_VM_VSRC_START 0x00000002
16368  #define SIMM16_WAITCNT_DEPCTR_VM_VSRC_SIZE 0x00000003
16369  #define SIMM16_WAITCNT_DEPCTR_HOLD_CNT_START 0x00000006
16370  #define SIMM16_WAITCNT_DEPCTR_HOLD_CNT_SIZE 0x00000001
16371  #define SIMM16_WAITCNT_DEPCTR_VA_SSRC_START 0x00000007
16372  #define SIMM16_WAITCNT_DEPCTR_VA_SSRC_SIZE 0x00000001
16373  #define SIMM16_WAITCNT_DEPCTR_VA_SDST_START 0x00000008
16374  #define SIMM16_WAITCNT_DEPCTR_VA_SDST_SIZE 0x00000003
16375  #define SIMM16_WAITCNT_DEPCTR_VA_VDST_START 0x0000000b
16376  #define SIMM16_WAITCNT_DEPCTR_VA_VDST_SIZE 0x00000005
16377  
16378  /*
16379   * SIMM16_WAIT_EVENT_PARTITIONS value
16380   */
16381  
16382  #define SIMM16_WAIT_EVENT_EXP_RDY_START 0x00000000
16383  #define SIMM16_WAIT_EVENT_EXP_RDY_SIZE 0x00000001
16384  
16385  /*
16386   * SQ_WAVE_IB_DEP_COUNTER_SIZES value
16387   */
16388  
16389  #define SQ_WAVE_IB_DEP_SA_SDST_SIZE    0x00000004
16390  #define SQ_WAVE_IB_DEP_SA_EXEC_SIZE    0x00000002
16391  #define SQ_WAVE_IB_DEP_SA_M0_SIZE      0x00000001
16392  #define SQ_WAVE_IB_DEP_VM_VSRC_SIZE    0x00000004
16393  #define SQ_WAVE_IB_DEP_HOLD_CNT_SIZE   0x00000001
16394  #define SQ_WAVE_IB_DEP_VA_SSRC_SIZE    0x00000003
16395  #define SQ_WAVE_IB_DEP_VA_SDST_SIZE    0x00000004
16396  #define SQ_WAVE_IB_DEP_VA_VCC_SIZE     0x00000003
16397  #define SQ_WAVE_IB_DEP_VA_EXEC_SIZE    0x00000002
16398  #define SQ_WAVE_IB_DEP_VA_VDST_SIZE    0x00000005
16399  #define SQ_WAVE_IB_DEP_LDS_DIR_SIZE    0x00000003
16400  
16401  /*
16402   * SQ_EDC_FUE_CNTL_BITS value
16403   */
16404  
16405  #define SQ_EDC_FUE_CNTL_SIMD0          0x00000000
16406  #define SQ_EDC_FUE_CNTL_SIMD1          0x00000001
16407  #define SQ_EDC_FUE_CNTL_SIMD2          0x00000002
16408  #define SQ_EDC_FUE_CNTL_SIMD3          0x00000003
16409  #define SQ_EDC_FUE_CNTL_SQ             0x00000004
16410  #define SQ_EDC_FUE_CNTL_LDS            0x00000005
16411  #define SQ_EDC_FUE_CNTL_TD             0x00000006
16412  #define SQ_EDC_FUE_CNTL_TA             0x00000007
16413  #define SQ_EDC_FUE_CNTL_TCP            0x00000008
16414  
16415  /*******************************************************
16416   * COMP Enums
16417   *******************************************************/
16418  
16419  /*
16420   * CSCNTL_TYPE enum
16421   */
16422  
16423  typedef enum CSCNTL_TYPE {
16424  CSCNTL_TYPE_TG                           = 0x00000000,
16425  CSCNTL_TYPE_STATE                        = 0x00000001,
16426  CSCNTL_TYPE_EVENT                        = 0x00000002,
16427  CSCNTL_TYPE_PRIVATE                      = 0x00000003,
16428  } CSCNTL_TYPE;
16429  
16430  /*
16431   * CSDATA_TYPE enum
16432   */
16433  
16434  typedef enum CSDATA_TYPE {
16435  CSDATA_TYPE_TG                           = 0x00000000,
16436  CSDATA_TYPE_STATE                        = 0x00000001,
16437  CSDATA_TYPE_EVENT                        = 0x00000002,
16438  CSDATA_TYPE_PRIVATE                      = 0x00000003,
16439  } CSDATA_TYPE;
16440  
16441  /*
16442   * CSDATA_TYPE_WIDTH value
16443   */
16444  
16445  #define CSDATA_TYPE_WIDTH              0x00000002
16446  
16447  /*
16448   * CSDATA_ADDR_WIDTH value
16449   */
16450  
16451  #define CSDATA_ADDR_WIDTH              0x00000007
16452  
16453  /*
16454   * CSDATA_DATA_WIDTH value
16455   */
16456  
16457  #define CSDATA_DATA_WIDTH              0x00000020
16458  
16459  /*
16460   * CSCNTL_TYPE_WIDTH value
16461   */
16462  
16463  #define CSCNTL_TYPE_WIDTH              0x00000002
16464  
16465  /*
16466   * CSCNTL_ADDR_WIDTH value
16467   */
16468  
16469  #define CSCNTL_ADDR_WIDTH              0x00000007
16470  
16471  /*
16472   * CSCNTL_DATA_WIDTH value
16473   */
16474  
16475  #define CSCNTL_DATA_WIDTH              0x00000020
16476  
16477  /*******************************************************
16478   * GE Enums
16479   *******************************************************/
16480  
16481  /*
16482   * GE1_PERFCOUNT_SELECT enum
16483   */
16484  
16485  typedef enum GE1_PERFCOUNT_SELECT {
16486  ge1_assembler_busy                       = 0x00000000,
16487  ge1_assembler_stalled                    = 0x00000001,
16488  ge1_dma_busy                             = 0x00000002,
16489  ge1_dma_lat_bin_0                        = 0x00000003,
16490  ge1_dma_lat_bin_1                        = 0x00000004,
16491  ge1_dma_lat_bin_2                        = 0x00000005,
16492  ge1_dma_lat_bin_3                        = 0x00000006,
16493  ge1_dma_lat_bin_4                        = 0x00000007,
16494  ge1_dma_lat_bin_5                        = 0x00000008,
16495  ge1_dma_lat_bin_6                        = 0x00000009,
16496  ge1_dma_lat_bin_7                        = 0x0000000a,
16497  ge1_dma_return_cl0                       = 0x0000000b,
16498  ge1_dma_return_cl1                       = 0x0000000c,
16499  ge1_dma_utcl1_consecutive_retry_event    = 0x0000000d,
16500  ge1_dma_utcl1_request_event              = 0x0000000e,
16501  ge1_dma_utcl1_retry_event                = 0x0000000f,
16502  ge1_dma_utcl1_stall_event                = 0x00000010,
16503  ge1_dma_utcl1_stall_utcl2_event          = 0x00000011,
16504  ge1_dma_utcl1_translation_hit_event      = 0x00000012,
16505  ge1_dma_utcl1_translation_miss_event     = 0x00000013,
16506  ge1_assembler_dma_starved                = 0x00000014,
16507  ge1_rbiu_di_fifo_stalled_p0              = 0x00000015,
16508  ge1_rbiu_di_fifo_starved_p0              = 0x00000016,
16509  ge1_rbiu_dr_fifo_stalled_p0              = 0x00000017,
16510  ge1_rbiu_dr_fifo_starved_p0              = 0x00000018,
16511  ge1_sclk_reg_vld                         = 0x00000019,
16512  ge1_stat_busy                            = 0x0000001a,
16513  ge1_stat_no_dma_busy                     = 0x0000001b,
16514  ge1_pipe0_to_pipe1                       = 0x0000001c,
16515  ge1_pipe1_to_pipe0                       = 0x0000001d,
16516  ge1_dma_return_size_cl0                  = 0x0000001e,
16517  ge1_dma_return_size_cl1                  = 0x0000001f,
16518  ge1_small_draws_one_instance             = 0x00000020,
16519  ge1_sclk_input_vld                       = 0x00000021,
16520  ge1_prim_group_limit_hit                 = 0x00000022,
16521  ge1_unopt_multi_instance_draws           = 0x00000023,
16522  ge1_rbiu_di_fifo_stalled_p1              = 0x00000024,
16523  ge1_rbiu_di_fifo_starved_p1              = 0x00000025,
16524  ge1_rbiu_dr_fifo_stalled_p1              = 0x00000026,
16525  ge1_rbiu_dr_fifo_starved_p1              = 0x00000027,
16526  } GE1_PERFCOUNT_SELECT;
16527  
16528  /*
16529   * GE2_DIST_PERFCOUNT_SELECT enum
16530   */
16531  
16532  typedef enum GE2_DIST_PERFCOUNT_SELECT {
16533  ge_dist_hs_done                          = 0x00000000,
16534  ge_dist_hs_done_latency_se0              = 0x00000001,
16535  ge_dist_hs_done_latency_se1              = 0x00000002,
16536  ge_dist_hs_done_latency_se2              = 0x00000003,
16537  ge_dist_hs_done_latency_se3              = 0x00000004,
16538  ge_dist_hs_done_latency_se4              = 0x00000005,
16539  ge_dist_hs_done_latency_se5              = 0x00000006,
16540  ge_dist_hs_done_latency_se6              = 0x00000007,
16541  ge_dist_hs_done_latency_se7              = 0x00000008,
16542  ge_dist_inside_tf_bin_0                  = 0x00000009,
16543  ge_dist_inside_tf_bin_1                  = 0x0000000a,
16544  ge_dist_inside_tf_bin_2                  = 0x0000000b,
16545  ge_dist_inside_tf_bin_3                  = 0x0000000c,
16546  ge_dist_inside_tf_bin_4                  = 0x0000000d,
16547  ge_dist_inside_tf_bin_5                  = 0x0000000e,
16548  ge_dist_inside_tf_bin_6                  = 0x0000000f,
16549  ge_dist_inside_tf_bin_7                  = 0x00000010,
16550  ge_dist_inside_tf_bin_8                  = 0x00000011,
16551  ge_dist_null_patch                       = 0x00000012,
16552  ge_dist_sclk_core_vld                    = 0x00000013,
16553  ge_dist_sclk_wd_te11_vld                 = 0x00000014,
16554  ge_dist_tfreq_lat_bin_0                  = 0x00000015,
16555  ge_dist_tfreq_lat_bin_1                  = 0x00000016,
16556  ge_dist_tfreq_lat_bin_2                  = 0x00000017,
16557  ge_dist_tfreq_lat_bin_3                  = 0x00000018,
16558  ge_dist_tfreq_lat_bin_4                  = 0x00000019,
16559  ge_dist_tfreq_lat_bin_5                  = 0x0000001a,
16560  ge_dist_tfreq_lat_bin_6                  = 0x0000001b,
16561  ge_dist_tfreq_lat_bin_7                  = 0x0000001c,
16562  ge_dist_tfreq_utcl1_consecutive_retry_event = 0x0000001d,
16563  ge_dist_tfreq_utcl1_request_event        = 0x0000001e,
16564  ge_dist_tfreq_utcl1_retry_event          = 0x0000001f,
16565  ge_dist_tfreq_utcl1_stall_event          = 0x00000020,
16566  ge_dist_tfreq_utcl1_stall_utcl2_event    = 0x00000021,
16567  ge_dist_tfreq_utcl1_translation_hit_event = 0x00000022,
16568  ge_dist_tfreq_utcl1_translation_miss_event = 0x00000023,
16569  ge_dist_vs_pc_stall                      = 0x00000024,
16570  ge_dist_pc_feorder_fifo_full             = 0x00000025,
16571  ge_dist_pc_ge_manager_busy               = 0x00000026,
16572  ge_dist_pc_req_stall_se0                 = 0x00000027,
16573  ge_dist_pc_req_stall_se1                 = 0x00000028,
16574  ge_dist_pc_req_stall_se2                 = 0x00000029,
16575  ge_dist_pc_req_stall_se3                 = 0x0000002a,
16576  ge_dist_pc_req_stall_se4                 = 0x0000002b,
16577  ge_dist_pc_req_stall_se5                 = 0x0000002c,
16578  ge_dist_pc_req_stall_se6                 = 0x0000002d,
16579  ge_dist_pc_req_stall_se7                 = 0x0000002e,
16580  ge_dist_pc_space_zero                    = 0x0000002f,
16581  ge_dist_sclk_input_vld                   = 0x00000030,
16582  ge_dist_reserved                         = 0x00000031,
16583  ge_dist_wd_te11_busy                     = 0x00000032,
16584  ge_dist_te11_starved                     = 0x00000033,
16585  ge_dist_switch_mode_stall                = 0x00000034,
16586  ge_all_tf_eq                             = 0x00000035,
16587  ge_all_tf2                               = 0x00000036,
16588  ge_all_tf3                               = 0x00000037,
16589  ge_all_tf4                               = 0x00000038,
16590  ge_all_tf5                               = 0x00000039,
16591  ge_all_tf6                               = 0x0000003a,
16592  ge_se0_te11_starved_on_hs_done           = 0x0000003b,
16593  ge_se1_te11_starved_on_hs_done           = 0x0000003c,
16594  ge_se2_te11_starved_on_hs_done           = 0x0000003d,
16595  ge_se3_te11_starved_on_hs_done           = 0x0000003e,
16596  ge_se4_te11_starved_on_hs_done           = 0x0000003f,
16597  ge_se5_te11_starved_on_hs_done           = 0x00000040,
16598  ge_se6_te11_starved_on_hs_done           = 0x00000041,
16599  ge_se7_te11_starved_on_hs_done           = 0x00000042,
16600  ge_dist_op_fifo_full_starve              = 0x00000043,
16601  ge_dist_hs_done_se0                      = 0x00000044,
16602  ge_dist_hs_done_se1                      = 0x00000045,
16603  ge_dist_hs_done_se2                      = 0x00000046,
16604  ge_dist_hs_done_se3                      = 0x00000047,
16605  ge_dist_hs_done_se4                      = 0x00000048,
16606  ge_dist_hs_done_se5                      = 0x00000049,
16607  ge_dist_hs_done_se6                      = 0x0000004a,
16608  ge_dist_hs_done_se7                      = 0x0000004b,
16609  ge_dist_hs_done_latency                  = 0x0000004c,
16610  ge_dist_distributer_busy                 = 0x0000004d,
16611  ge_tf_ret_data_stalling_hs_done          = 0x0000004e,
16612  ge_num_of_no_dist_patches                = 0x0000004f,
16613  ge_num_of_donut_dist_patches             = 0x00000050,
16614  ge_num_of_patch_dist_patches             = 0x00000051,
16615  ge_num_of_se_switches_due_to_patch_accum = 0x00000052,
16616  ge_num_of_se_switches_due_to_donut       = 0x00000053,
16617  ge_num_of_se_switches_due_to_trap        = 0x00000054,
16618  ge_num_of_hs_alloc_events                = 0x00000055,
16619  ge_agm_gcr_req                           = 0x00000056,
16620  ge_agm_gcr_tag_stall                     = 0x00000057,
16621  ge_agm_gcr_crd_stall                     = 0x00000058,
16622  ge_agm_gcr_stall                         = 0x00000059,
16623  ge_agm_gcr_latency                       = 0x0000005a,
16624  ge_distclk_vld                           = 0x0000005b,
16625  } GE2_DIST_PERFCOUNT_SELECT;
16626  
16627  /*
16628   * GE2_SE_PERFCOUNT_SELECT enum
16629   */
16630  
16631  typedef enum GE2_SE_PERFCOUNT_SELECT {
16632  ge_se_ds_prims                           = 0x00000000,
16633  ge_se_es_thread_groups                   = 0x00000001,
16634  ge_se_esvert_stalled_gsprim              = 0x00000002,
16635  ge_se_hs_tfm_stall                       = 0x00000003,
16636  ge_se_hs_tgs_active_high_water_mark      = 0x00000004,
16637  ge_se_hs_thread_groups                   = 0x00000005,
16638  ge_se_reused_es_indices                  = 0x00000006,
16639  ge_se_sclk_ngg_vld                       = 0x00000007,
16640  ge_se_sclk_te11_vld                      = 0x00000008,
16641  ge_se_spi_esvert_eov                     = 0x00000009,
16642  ge_se_spi_esvert_stalled                 = 0x0000000a,
16643  ge_se_spi_esvert_starved_busy            = 0x0000000b,
16644  ge_se_spi_esvert_valid                   = 0x0000000c,
16645  ge_se_spi_gsprim_cont                    = 0x0000000d,
16646  ge_se_spi_gsprim_eov                     = 0x0000000e,
16647  ge_se_spi_gsprim_stalled                 = 0x0000000f,
16648  ge_se_spi_gsprim_starved_busy            = 0x00000010,
16649  ge_se_spi_gsprim_valid                   = 0x00000011,
16650  ge_se_spi_gssubgrp_is_event              = 0x00000012,
16651  ge_se_spi_gssubgrp_send                  = 0x00000013,
16652  ge_se_spi_hsvert_eov                     = 0x00000014,
16653  ge_se_spi_hsvert_stalled                 = 0x00000015,
16654  ge_se_spi_hsvert_starved_busy            = 0x00000016,
16655  ge_se_spi_hsvert_valid                   = 0x00000017,
16656  ge_se_spi_hswave_is_event                = 0x00000018,
16657  ge_se_spi_hswave_send                    = 0x00000019,
16658  ge_se_spi_lsvert_eov                     = 0x0000001a,
16659  ge_se_spi_lsvert_stalled                 = 0x0000001b,
16660  ge_se_spi_lsvert_starved_busy            = 0x0000001c,
16661  ge_se_spi_lsvert_valid                   = 0x0000001d,
16662  ge_se_spi_hsvert_fifo_full_stall         = 0x0000001e,
16663  ge_se_spi_tgrp_fifo_stall                = 0x0000001f,
16664  ge_spi_hsgrp_spi_stall                   = 0x00000020,
16665  ge_se_spi_gssubgrp_event_window_active   = 0x00000021,
16666  ge_se_hs_input_stall                     = 0x00000022,
16667  ge_se_sending_vert_or_prim               = 0x00000023,
16668  ge_se_sclk_input_vld                     = 0x00000024,
16669  ge_spi_lswave_fifo_full_stall            = 0x00000025,
16670  ge_spi_hswave_fifo_full_stall            = 0x00000026,
16671  ge_hs_tif_stall                          = 0x00000027,
16672  ge_csb_spi_bp                            = 0x00000028,
16673  ge_ngg_starving_for_pc_grant             = 0x00000029,
16674  ge_pa0_csb_eop                           = 0x0000002a,
16675  ge_pa1_csb_eop                           = 0x0000002b,
16676  ge_ngg_starved_idle                      = 0x0000002c,
16677  ge_gsprim_send                           = 0x0000002d,
16678  ge_esvert_send                           = 0x0000002e,
16679  ge_ngg_starved_after_work                = 0x0000002f,
16680  ge_ngg_subgrp_fifo_stall                 = 0x00000030,
16681  ge_ngg_ord_id_req_stall                  = 0x00000031,
16682  ge_ngg_indx_bus_stall                    = 0x00000032,
16683  ge_hs_stall_tfmm_fifo_full               = 0x00000033,
16684  ge_gs_issue_rtr_stalled                  = 0x00000034,
16685  ge_gsprim_stalled_esvert                 = 0x00000035,
16686  ge_gsthread_stalled                      = 0x00000036,
16687  ge_te11_stall_prim_funnel                = 0x00000037,
16688  ge_te11_stall_vert_funnel                = 0x00000038,
16689  ge_ngg_attr_grp_alloc                    = 0x00000039,
16690  ge_ngg_attr_discard_alloc                = 0x0000003a,
16691  ge_ngg_pc_space_not_avail                = 0x0000003b,
16692  ge_ngg_agm_req_stall                     = 0x0000003c,
16693  ge_ngg_spi_esvert_partial_eov            = 0x0000003d,
16694  ge_ngg_spi_gsprim_partial_eov            = 0x0000003e,
16695  ge_spi_gsgrp_valid                       = 0x0000003f,
16696  ge_ngg_attr_grp_latency                  = 0x00000040,
16697  ge_ngg_reuse_prim_limit_hit              = 0x00000041,
16698  ge_ngg_reuse_vert_limit_hit              = 0x00000042,
16699  ge_te11_con_stall                        = 0x00000043,
16700  ge_te11_compactor_starved                = 0x00000044,
16701  ge_ngg_stall_tess_off_tess_on            = 0x00000045,
16702  ge_ngg_stall_tess_on_tess_off            = 0x00000046,
16703  } GE2_SE_PERFCOUNT_SELECT;
16704  
16705  /*
16706   * VGT_DETECT_ONE enum
16707   */
16708  
16709  typedef enum VGT_DETECT_ONE {
16710  ENABLE_TF1_OPT                           = 0x00000000,
16711  DISABLE_TF1_OPT                          = 0x00000001,
16712  } VGT_DETECT_ONE;
16713  
16714  /*
16715   * VGT_DETECT_ZERO enum
16716   */
16717  
16718  typedef enum VGT_DETECT_ZERO {
16719  ENABLE_TF0_OPT                           = 0x00000000,
16720  DISABLE_TF0_OPT                          = 0x00000001,
16721  } VGT_DETECT_ZERO;
16722  
16723  /*
16724   * VGT_DIST_MODE enum
16725   */
16726  
16727  typedef enum VGT_DIST_MODE {
16728  NO_DIST                                  = 0x00000000,
16729  PATCHES                                  = 0x00000001,
16730  DONUTS                                   = 0x00000002,
16731  TRAPEZOIDS                               = 0x00000003,
16732  } VGT_DIST_MODE;
16733  
16734  /*
16735   * VGT_DI_INDEX_SIZE enum
16736   */
16737  
16738  typedef enum VGT_DI_INDEX_SIZE {
16739  DI_INDEX_SIZE_16_BIT                     = 0x00000000,
16740  DI_INDEX_SIZE_32_BIT                     = 0x00000001,
16741  DI_INDEX_SIZE_8_BIT                      = 0x00000002,
16742  } VGT_DI_INDEX_SIZE;
16743  
16744  /*
16745   * VGT_DI_MAJOR_MODE_SELECT enum
16746   */
16747  
16748  typedef enum VGT_DI_MAJOR_MODE_SELECT {
16749  DI_MAJOR_MODE_0                          = 0x00000000,
16750  DI_MAJOR_MODE_1                          = 0x00000001,
16751  } VGT_DI_MAJOR_MODE_SELECT;
16752  
16753  /*
16754   * VGT_DI_PRIM_TYPE enum
16755   */
16756  
16757  typedef enum VGT_DI_PRIM_TYPE {
16758  DI_PT_NONE                               = 0x00000000,
16759  DI_PT_POINTLIST                          = 0x00000001,
16760  DI_PT_LINELIST                           = 0x00000002,
16761  DI_PT_LINESTRIP                          = 0x00000003,
16762  DI_PT_TRILIST                            = 0x00000004,
16763  DI_PT_TRIFAN                             = 0x00000005,
16764  DI_PT_TRISTRIP                           = 0x00000006,
16765  DI_PT_2D_RECTANGLE                       = 0x00000007,
16766  DI_PT_UNUSED_1                           = 0x00000008,
16767  DI_PT_PATCH                              = 0x00000009,
16768  DI_PT_LINELIST_ADJ                       = 0x0000000a,
16769  DI_PT_LINESTRIP_ADJ                      = 0x0000000b,
16770  DI_PT_TRILIST_ADJ                        = 0x0000000c,
16771  DI_PT_TRISTRIP_ADJ                       = 0x0000000d,
16772  DI_PT_UNUSED_3                           = 0x0000000e,
16773  DI_PT_UNUSED_4                           = 0x0000000f,
16774  DI_PT_UNUSED_5                           = 0x00000010,
16775  DI_PT_RECTLIST                           = 0x00000011,
16776  DI_PT_LINELOOP                           = 0x00000012,
16777  DI_PT_QUADLIST                           = 0x00000013,
16778  DI_PT_QUADSTRIP                          = 0x00000014,
16779  DI_PT_POLYGON                            = 0x00000015,
16780  } VGT_DI_PRIM_TYPE;
16781  
16782  /*
16783   * VGT_DI_SOURCE_SELECT enum
16784   */
16785  
16786  typedef enum VGT_DI_SOURCE_SELECT {
16787  DI_SRC_SEL_DMA                           = 0x00000000,
16788  DI_SRC_SEL_IMMEDIATE                     = 0x00000001,
16789  DI_SRC_SEL_AUTO_INDEX                    = 0x00000002,
16790  DI_SRC_SEL_RESERVED                      = 0x00000003,
16791  } VGT_DI_SOURCE_SELECT;
16792  
16793  /*
16794   * VGT_DMA_BUF_TYPE enum
16795   */
16796  
16797  typedef enum VGT_DMA_BUF_TYPE {
16798  VGT_DMA_BUF_MEM                          = 0x00000000,
16799  VGT_DMA_BUF_RING                         = 0x00000001,
16800  VGT_DMA_BUF_SETUP                        = 0x00000002,
16801  VGT_DMA_PTR_UPDATE                       = 0x00000003,
16802  } VGT_DMA_BUF_TYPE;
16803  
16804  /*
16805   * VGT_DMA_SWAP_MODE enum
16806   */
16807  
16808  typedef enum VGT_DMA_SWAP_MODE {
16809  VGT_DMA_SWAP_NONE                        = 0x00000000,
16810  VGT_DMA_SWAP_16_BIT                      = 0x00000001,
16811  VGT_DMA_SWAP_32_BIT                      = 0x00000002,
16812  VGT_DMA_SWAP_WORD                        = 0x00000003,
16813  } VGT_DMA_SWAP_MODE;
16814  
16815  /*
16816   * VGT_EVENT_TYPE enum
16817   */
16818  
16819  typedef enum VGT_EVENT_TYPE {
16820  Reserved_0x00                            = 0x00000000,
16821  SAMPLE_STREAMOUTSTATS1                   = 0x00000001,
16822  SAMPLE_STREAMOUTSTATS2                   = 0x00000002,
16823  SAMPLE_STREAMOUTSTATS3                   = 0x00000003,
16824  CACHE_FLUSH_TS                           = 0x00000004,
16825  CONTEXT_DONE                             = 0x00000005,
16826  CACHE_FLUSH                              = 0x00000006,
16827  CS_PARTIAL_FLUSH                         = 0x00000007,
16828  VGT_STREAMOUT_SYNC                       = 0x00000008,
16829  Reserved_0x09                            = 0x00000009,
16830  VGT_STREAMOUT_RESET                      = 0x0000000a,
16831  END_OF_PIPE_INCR_DE                      = 0x0000000b,
16832  END_OF_PIPE_IB_END                       = 0x0000000c,
16833  RST_PIX_CNT                              = 0x0000000d,
16834  BREAK_BATCH                              = 0x0000000e,
16835  VS_PARTIAL_FLUSH                         = 0x0000000f,
16836  PS_PARTIAL_FLUSH                         = 0x00000010,
16837  FLUSH_HS_OUTPUT                          = 0x00000011,
16838  FLUSH_DFSM                               = 0x00000012,
16839  RESET_TO_LOWEST_VGT                      = 0x00000013,
16840  CACHE_FLUSH_AND_INV_TS_EVENT             = 0x00000014,
16841  WAIT_SYNC                                = 0x00000015,
16842  CACHE_FLUSH_AND_INV_EVENT                = 0x00000016,
16843  PERFCOUNTER_START                        = 0x00000017,
16844  PERFCOUNTER_STOP                         = 0x00000018,
16845  PIPELINESTAT_START                       = 0x00000019,
16846  PIPELINESTAT_STOP                        = 0x0000001a,
16847  PERFCOUNTER_SAMPLE                       = 0x0000001b,
16848  FLUSH_ES_OUTPUT                          = 0x0000001c,
16849  BIN_CONF_OVERRIDE_CHECK                  = 0x0000001d,
16850  SAMPLE_PIPELINESTAT                      = 0x0000001e,
16851  SO_VGTSTREAMOUT_FLUSH                    = 0x0000001f,
16852  SAMPLE_STREAMOUTSTATS                    = 0x00000020,
16853  RESET_VTX_CNT                            = 0x00000021,
16854  BLOCK_CONTEXT_DONE                       = 0x00000022,
16855  CS_CONTEXT_DONE                          = 0x00000023,
16856  VGT_FLUSH                                = 0x00000024,
16857  TGID_ROLLOVER                            = 0x00000025,
16858  SQ_NON_EVENT                             = 0x00000026,
16859  SC_SEND_DB_VPZ                           = 0x00000027,
16860  BOTTOM_OF_PIPE_TS                        = 0x00000028,
16861  FLUSH_SX_TS                              = 0x00000029,
16862  DB_CACHE_FLUSH_AND_INV                   = 0x0000002a,
16863  FLUSH_AND_INV_DB_DATA_TS                 = 0x0000002b,
16864  FLUSH_AND_INV_DB_META                    = 0x0000002c,
16865  FLUSH_AND_INV_CB_DATA_TS                 = 0x0000002d,
16866  FLUSH_AND_INV_CB_META                    = 0x0000002e,
16867  CS_DONE                                  = 0x0000002f,
16868  PS_DONE                                  = 0x00000030,
16869  FLUSH_AND_INV_CB_PIXEL_DATA              = 0x00000031,
16870  SX_CB_RAT_ACK_REQUEST                    = 0x00000032,
16871  THREAD_TRACE_START                       = 0x00000033,
16872  THREAD_TRACE_STOP                        = 0x00000034,
16873  THREAD_TRACE_MARKER                      = 0x00000035,
16874  THREAD_TRACE_DRAW                        = 0x00000036,
16875  THREAD_TRACE_FINISH                      = 0x00000037,
16876  PIXEL_PIPE_STAT_CONTROL                  = 0x00000038,
16877  PIXEL_PIPE_STAT_DUMP                     = 0x00000039,
16878  PIXEL_PIPE_STAT_RESET                    = 0x0000003a,
16879  CONTEXT_SUSPEND                          = 0x0000003b,
16880  OFFCHIP_HS_DEALLOC                       = 0x0000003c,
16881  ENABLE_NGG_PIPELINE                      = 0x0000003d,
16882  ENABLE_LEGACY_PIPELINE                   = 0x0000003e,
16883  DRAW_DONE                                = 0x0000003f,
16884  } VGT_EVENT_TYPE;
16885  
16886  /*
16887   * VGT_GROUP_CONV_SEL enum
16888   */
16889  
16890  typedef enum VGT_GROUP_CONV_SEL {
16891  VGT_GRP_INDEX_16                         = 0x00000000,
16892  VGT_GRP_INDEX_32                         = 0x00000001,
16893  VGT_GRP_UINT_16                          = 0x00000002,
16894  VGT_GRP_UINT_32                          = 0x00000003,
16895  VGT_GRP_SINT_16                          = 0x00000004,
16896  VGT_GRP_SINT_32                          = 0x00000005,
16897  VGT_GRP_FLOAT_32                         = 0x00000006,
16898  VGT_GRP_AUTO_PRIM                        = 0x00000007,
16899  VGT_GRP_FIX_1_23_TO_FLOAT                = 0x00000008,
16900  } VGT_GROUP_CONV_SEL;
16901  
16902  /*
16903   * VGT_GS_MODE_TYPE enum
16904   */
16905  
16906  typedef enum VGT_GS_MODE_TYPE {
16907  GS_OFF                                   = 0x00000000,
16908  GS_SCENARIO_A                            = 0x00000001,
16909  GS_SCENARIO_B                            = 0x00000002,
16910  GS_SCENARIO_G                            = 0x00000003,
16911  GS_SCENARIO_C                            = 0x00000004,
16912  SPRITE_EN                                = 0x00000005,
16913  } VGT_GS_MODE_TYPE;
16914  
16915  /*
16916   * VGT_GS_OUTPRIM_TYPE enum
16917   */
16918  
16919  typedef enum VGT_GS_OUTPRIM_TYPE {
16920  POINTLIST                                = 0x00000000,
16921  LINESTRIP                                = 0x00000001,
16922  TRISTRIP                                 = 0x00000002,
16923  RECT_2D                                  = 0x00000003,
16924  RECTLIST                                 = 0x00000004,
16925  } VGT_GS_OUTPRIM_TYPE;
16926  
16927  /*
16928   * VGT_INDEX_TYPE_MODE enum
16929   */
16930  
16931  typedef enum VGT_INDEX_TYPE_MODE {
16932  VGT_INDEX_16                             = 0x00000000,
16933  VGT_INDEX_32                             = 0x00000001,
16934  VGT_INDEX_8                              = 0x00000002,
16935  } VGT_INDEX_TYPE_MODE;
16936  
16937  /*
16938   * VGT_OUTPATH_SELECT enum
16939   */
16940  
16941  typedef enum VGT_OUTPATH_SELECT {
16942  VGT_OUTPATH_VTX_REUSE                    = 0x00000000,
16943  VGT_OUTPATH_GS_BLOCK                     = 0x00000001,
16944  VGT_OUTPATH_HS_BLOCK                     = 0x00000002,
16945  VGT_OUTPATH_PRIM_GEN                     = 0x00000003,
16946  VGT_OUTPATH_TE_PRIM_GEN                  = 0x00000004,
16947  VGT_OUTPATH_TE_GS_BLOCK                  = 0x00000005,
16948  VGT_OUTPATH_TE_OUTPUT                    = 0x00000006,
16949  } VGT_OUTPATH_SELECT;
16950  
16951  /*
16952   * VGT_OUT_PRIM_TYPE enum
16953   */
16954  
16955  typedef enum VGT_OUT_PRIM_TYPE {
16956  VGT_OUT_POINT                            = 0x00000000,
16957  VGT_OUT_LINE                             = 0x00000001,
16958  VGT_OUT_TRI                              = 0x00000002,
16959  VGT_OUT_RECT_V0                          = 0x00000003,
16960  VGT_OUT_RECT_V1                          = 0x00000004,
16961  VGT_OUT_RECT_V2                          = 0x00000005,
16962  VGT_OUT_RECT_V3                          = 0x00000006,
16963  VGT_OUT_2D_RECT                          = 0x00000007,
16964  VGT_TE_QUAD                              = 0x00000008,
16965  VGT_TE_PRIM_INDEX_LINE                   = 0x00000009,
16966  VGT_TE_PRIM_INDEX_TRI                    = 0x0000000a,
16967  VGT_TE_PRIM_INDEX_QUAD                   = 0x0000000b,
16968  VGT_OUT_LINE_ADJ                         = 0x0000000c,
16969  VGT_OUT_TRI_ADJ                          = 0x0000000d,
16970  VGT_OUT_PATCH                            = 0x0000000e,
16971  } VGT_OUT_PRIM_TYPE;
16972  
16973  /*
16974   * VGT_RDREQ_POLICY enum
16975   */
16976  
16977  typedef enum VGT_RDREQ_POLICY {
16978  VGT_POLICY_LRU                           = 0x00000000,
16979  VGT_POLICY_STREAM                        = 0x00000001,
16980  VGT_POLICY_BYPASS                        = 0x00000002,
16981  } VGT_RDREQ_POLICY;
16982  
16983  /*
16984   * VGT_STAGES_ES_EN enum
16985   */
16986  
16987  typedef enum VGT_STAGES_ES_EN {
16988  ES_STAGE_OFF                             = 0x00000000,
16989  ES_STAGE_DS                              = 0x00000001,
16990  ES_STAGE_REAL                            = 0x00000002,
16991  RESERVED_ES                              = 0x00000003,
16992  } VGT_STAGES_ES_EN;
16993  
16994  /*
16995   * VGT_STAGES_GS_EN enum
16996   */
16997  
16998  typedef enum VGT_STAGES_GS_EN {
16999  GS_STAGE_OFF                             = 0x00000000,
17000  GS_STAGE_ON                              = 0x00000001,
17001  } VGT_STAGES_GS_EN;
17002  
17003  /*
17004   * VGT_STAGES_HS_EN enum
17005   */
17006  
17007  typedef enum VGT_STAGES_HS_EN {
17008  HS_STAGE_OFF                             = 0x00000000,
17009  HS_STAGE_ON                              = 0x00000001,
17010  } VGT_STAGES_HS_EN;
17011  
17012  /*
17013   * VGT_STAGES_LS_EN enum
17014   */
17015  
17016  typedef enum VGT_STAGES_LS_EN {
17017  LS_STAGE_OFF                             = 0x00000000,
17018  LS_STAGE_ON                              = 0x00000001,
17019  CS_STAGE_ON                              = 0x00000002,
17020  RESERVED_LS                              = 0x00000003,
17021  } VGT_STAGES_LS_EN;
17022  
17023  /*
17024   * VGT_STAGES_VS_EN enum
17025   */
17026  
17027  typedef enum VGT_STAGES_VS_EN {
17028  VS_STAGE_REAL                            = 0x00000000,
17029  VS_STAGE_DS                              = 0x00000001,
17030  VS_STAGE_COPY_SHADER                     = 0x00000002,
17031  RESERVED_VS                              = 0x00000003,
17032  } VGT_STAGES_VS_EN;
17033  
17034  /*
17035   * VGT_TESS_PARTITION enum
17036   */
17037  
17038  typedef enum VGT_TESS_PARTITION {
17039  PART_INTEGER                             = 0x00000000,
17040  PART_POW2                                = 0x00000001,
17041  PART_FRAC_ODD                            = 0x00000002,
17042  PART_FRAC_EVEN                           = 0x00000003,
17043  } VGT_TESS_PARTITION;
17044  
17045  /*
17046   * VGT_TESS_TOPOLOGY enum
17047   */
17048  
17049  typedef enum VGT_TESS_TOPOLOGY {
17050  OUTPUT_POINT                             = 0x00000000,
17051  OUTPUT_LINE                              = 0x00000001,
17052  OUTPUT_TRIANGLE_CW                       = 0x00000002,
17053  OUTPUT_TRIANGLE_CCW                      = 0x00000003,
17054  } VGT_TESS_TOPOLOGY;
17055  
17056  /*
17057   * VGT_TESS_TYPE enum
17058   */
17059  
17060  typedef enum VGT_TESS_TYPE {
17061  TESS_ISOLINE                             = 0x00000000,
17062  TESS_TRIANGLE                            = 0x00000001,
17063  TESS_QUAD                                = 0x00000002,
17064  } VGT_TESS_TYPE;
17065  
17066  /*
17067   * WD_IA_DRAW_REG_XFER enum
17068   */
17069  
17070  typedef enum WD_IA_DRAW_REG_XFER {
17071  WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM   = 0x00000000,
17072  WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN = 0x00000001,
17073  WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID = 0x00000002,
17074  WD_IA_DRAW_REG_XFER_GE_CNTL              = 0x00000003,
17075  WD_IA_DRAW_REG_XFER_GE_USER_VGPR_EN      = 0x00000004,
17076  WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM         = 0x00000005,
17077  WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM_1       = 0x00000006,
17078  WD_IA_DRAW_REG_XFER_FL_MS_TG_SIZE        = 0x00000007,
17079  WD_IA_DRAW_REG_XFER_FL_MS_EXP_ALLOC      = 0x00000008,
17080  } WD_IA_DRAW_REG_XFER;
17081  
17082  /*
17083   * WD_IA_DRAW_SOURCE enum
17084   */
17085  
17086  typedef enum WD_IA_DRAW_SOURCE {
17087  WD_IA_DRAW_SOURCE_DMA                    = 0x00000000,
17088  WD_IA_DRAW_SOURCE_IMMD                   = 0x00000001,
17089  WD_IA_DRAW_SOURCE_AUTO                   = 0x00000002,
17090  WD_IA_DRAW_SOURCE_OPAQ                   = 0x00000003,
17091  } WD_IA_DRAW_SOURCE;
17092  
17093  /*
17094   * WD_IA_DRAW_TYPE enum
17095   */
17096  
17097  typedef enum WD_IA_DRAW_TYPE {
17098  WD_IA_DRAW_TYPE_DI_MM0                   = 0x00000000,
17099  WD_IA_DRAW_TYPE_REG_XFER                 = 0x00000001,
17100  WD_IA_DRAW_TYPE_EVENT_INIT               = 0x00000002,
17101  WD_IA_DRAW_TYPE_EVENT_ADDR               = 0x00000003,
17102  WD_IA_DRAW_TYPE_MIN_INDX                 = 0x00000004,
17103  WD_IA_DRAW_TYPE_MAX_INDX                 = 0x00000005,
17104  WD_IA_DRAW_TYPE_INDX_OFF                 = 0x00000006,
17105  WD_IA_DRAW_TYPE_IMM_DATA                 = 0x00000007,
17106  } WD_IA_DRAW_TYPE;
17107  
17108  /*
17109   * GS_THREADID_SIZE value
17110   */
17111  
17112  #define GSTHREADID_SIZE                0x00000002
17113  
17114  /*******************************************************
17115   * GB Enums
17116   *******************************************************/
17117  
17118  /*
17119   * GB_EDC_DED_MODE enum
17120   */
17121  
17122  typedef enum GB_EDC_DED_MODE {
17123  GB_EDC_DED_MODE_LOG                      = 0x00000000,
17124  GB_EDC_DED_MODE_HALT                     = 0x00000001,
17125  GB_EDC_DED_MODE_INT_HALT                 = 0x00000002,
17126  } GB_EDC_DED_MODE;
17127  
17128  /*
17129   * VALUE_GB_TILING_CONFIG_TABLE_SIZE value
17130   */
17131  
17132  #define GB_TILING_CONFIG_TABLE_SIZE    0x00000020
17133  
17134  /*
17135   * VALUE_GB_TILING_CONFIG_MACROTABLE_SIZE value
17136   */
17137  
17138  #define GB_TILING_CONFIG_MACROTABLE_SIZE 0x00000010
17139  
17140  /*******************************************************
17141   * GLX Enums
17142   *******************************************************/
17143  
17144  /*
17145   * CHA_PERF_SEL enum
17146   */
17147  
17148  typedef enum CHA_PERF_SEL {
17149  CHA_PERF_SEL_BUSY                        = 0x00000000,
17150  CHA_PERF_SEL_STALL_CHC0                  = 0x00000001,
17151  CHA_PERF_SEL_STALL_CHC1                  = 0x00000002,
17152  CHA_PERF_SEL_STALL_CHC2                  = 0x00000003,
17153  CHA_PERF_SEL_STALL_CHC3                  = 0x00000004,
17154  CHA_PERF_SEL_STALL_CHC4                  = 0x00000005,
17155  CHA_PERF_SEL_STALL_CHC5                  = 0x00000006,
17156  CHA_PERF_SEL_REQUEST_CHC0                = 0x00000007,
17157  CHA_PERF_SEL_REQUEST_CHC1                = 0x00000008,
17158  CHA_PERF_SEL_REQUEST_CHC2                = 0x00000009,
17159  CHA_PERF_SEL_REQUEST_CHC3                = 0x0000000a,
17160  CHA_PERF_SEL_REQUEST_CHC4                = 0x0000000b,
17161  CHA_PERF_SEL_MEM_32B_WDS_CHC0            = 0x0000000c,
17162  CHA_PERF_SEL_MEM_32B_WDS_CHC1            = 0x0000000d,
17163  CHA_PERF_SEL_MEM_32B_WDS_CHC2            = 0x0000000e,
17164  CHA_PERF_SEL_MEM_32B_WDS_CHC3            = 0x0000000f,
17165  CHA_PERF_SEL_MEM_32B_WDS_CHC4            = 0x00000010,
17166  CHA_PERF_SEL_IO_32B_WDS_CHC0             = 0x00000011,
17167  CHA_PERF_SEL_IO_32B_WDS_CHC1             = 0x00000012,
17168  CHA_PERF_SEL_IO_32B_WDS_CHC2             = 0x00000013,
17169  CHA_PERF_SEL_IO_32B_WDS_CHC3             = 0x00000014,
17170  CHA_PERF_SEL_IO_32B_WDS_CHC4             = 0x00000015,
17171  CHA_PERF_SEL_MEM_BURST_COUNT_CHC0        = 0x00000016,
17172  CHA_PERF_SEL_MEM_BURST_COUNT_CHC1        = 0x00000017,
17173  CHA_PERF_SEL_MEM_BURST_COUNT_CHC2        = 0x00000018,
17174  CHA_PERF_SEL_MEM_BURST_COUNT_CHC3        = 0x00000019,
17175  CHA_PERF_SEL_MEM_BURST_COUNT_CHC4        = 0x0000001a,
17176  CHA_PERF_SEL_IO_BURST_COUNT_CHC0         = 0x0000001b,
17177  CHA_PERF_SEL_IO_BURST_COUNT_CHC1         = 0x0000001c,
17178  CHA_PERF_SEL_IO_BURST_COUNT_CHC2         = 0x0000001d,
17179  CHA_PERF_SEL_IO_BURST_COUNT_CHC3         = 0x0000001e,
17180  CHA_PERF_SEL_IO_BURST_COUNT_CHC4         = 0x0000001f,
17181  CHA_PERF_SEL_ARB_REQUESTS                = 0x00000020,
17182  CHA_PERF_SEL_REQ_INFLIGHT_LEVEL          = 0x00000021,
17183  CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0     = 0x00000022,
17184  CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1     = 0x00000023,
17185  CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2     = 0x00000024,
17186  CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3     = 0x00000025,
17187  CHA_PERF_SEL_STALL_RET_CONFLICT_CHC4     = 0x00000026,
17188  CHA_PERF_SEL_CYCLE                       = 0x00000027,
17189  } CHA_PERF_SEL;
17190  
17191  /*
17192   * CHCG_PERF_SEL enum
17193   */
17194  
17195  typedef enum CHCG_PERF_SEL {
17196  CHCG_PERF_SEL_CYCLE                      = 0x00000000,
17197  CHCG_PERF_SEL_BUSY                       = 0x00000001,
17198  CHCG_PERF_SEL_STARVE                     = 0x00000002,
17199  CHCG_PERF_SEL_ARB_RET_LEVEL              = 0x00000003,
17200  CHCG_PERF_SEL_GL2_REQ_READ_LATENCY       = 0x00000004,
17201  CHCG_PERF_SEL_GL2_REQ_WRITE_LATENCY      = 0x00000005,
17202  CHCG_PERF_SEL_REQ                        = 0x00000006,
17203  CHCG_PERF_SEL_REQ_ATOMIC_WITH_RET        = 0x00000007,
17204  CHCG_PERF_SEL_REQ_ATOMIC_WITHOUT_RET     = 0x00000008,
17205  CHCG_PERF_SEL_REQ_NOP_ACK                = 0x00000009,
17206  CHCG_PERF_SEL_REQ_NOP_RTN0               = 0x0000000a,
17207  CHCG_PERF_SEL_REQ_READ                   = 0x0000000b,
17208  CHCG_PERF_SEL_REQ_READ_128B              = 0x0000000c,
17209  CHCG_PERF_SEL_REQ_READ_32B               = 0x0000000d,
17210  CHCG_PERF_SEL_REQ_READ_64B               = 0x0000000e,
17211  CHCG_PERF_SEL_REQ_WRITE                  = 0x0000000f,
17212  CHCG_PERF_SEL_REQ_WRITE_32B              = 0x00000010,
17213  CHCG_PERF_SEL_REQ_WRITE_64B              = 0x00000011,
17214  CHCG_PERF_SEL_STALL_GUS_GL1              = 0x00000012,
17215  CHCG_PERF_SEL_STALL_BUFFER_FULL          = 0x00000013,
17216  CHCG_PERF_SEL_REQ_CLIENT0                = 0x00000014,
17217  CHCG_PERF_SEL_REQ_CLIENT1                = 0x00000015,
17218  CHCG_PERF_SEL_REQ_CLIENT2                = 0x00000016,
17219  CHCG_PERF_SEL_REQ_CLIENT3                = 0x00000017,
17220  CHCG_PERF_SEL_REQ_CLIENT4                = 0x00000018,
17221  CHCG_PERF_SEL_REQ_CLIENT5                = 0x00000019,
17222  CHCG_PERF_SEL_REQ_CLIENT6                = 0x0000001a,
17223  CHCG_PERF_SEL_REQ_CLIENT7                = 0x0000001b,
17224  CHCG_PERF_SEL_REQ_CLIENT8                = 0x0000001c,
17225  CHCG_PERF_SEL_REQ_CLIENT9                = 0x0000001d,
17226  CHCG_PERF_SEL_REQ_CLIENT10               = 0x0000001e,
17227  CHCG_PERF_SEL_REQ_CLIENT11               = 0x0000001f,
17228  CHCG_PERF_SEL_REQ_CLIENT12               = 0x00000020,
17229  CHCG_PERF_SEL_REQ_CLIENT13               = 0x00000021,
17230  CHCG_PERF_SEL_REQ_CLIENT14               = 0x00000022,
17231  CHCG_PERF_SEL_REQ_CLIENT15               = 0x00000023,
17232  CHCG_PERF_SEL_REQ_CLIENT16               = 0x00000024,
17233  CHCG_PERF_SEL_REQ_CLIENT17               = 0x00000025,
17234  CHCG_PERF_SEL_REQ_CLIENT18               = 0x00000026,
17235  CHCG_PERF_SEL_REQ_CLIENT19               = 0x00000027,
17236  CHCG_PERF_SEL_REQ_CLIENT20               = 0x00000028,
17237  CHCG_PERF_SEL_REQ_CLIENT21               = 0x00000029,
17238  CHCG_PERF_SEL_REQ_CLIENT22               = 0x0000002a,
17239  CHCG_PERF_SEL_REQ_CLIENT23               = 0x0000002b,
17240  } CHCG_PERF_SEL;
17241  
17242  /*
17243   * CHC_PERF_SEL enum
17244   */
17245  
17246  typedef enum CHC_PERF_SEL {
17247  CHC_PERF_SEL_CYCLE                       = 0x00000000,
17248  CHC_PERF_SEL_BUSY                        = 0x00000001,
17249  CHC_PERF_SEL_STARVE                      = 0x00000002,
17250  CHC_PERF_SEL_ARB_RET_LEVEL               = 0x00000003,
17251  CHC_PERF_SEL_GL2_REQ_READ_LATENCY        = 0x00000004,
17252  CHC_PERF_SEL_GL2_REQ_WRITE_LATENCY       = 0x00000005,
17253  CHC_PERF_SEL_REQ                         = 0x00000006,
17254  CHC_PERF_SEL_REQ_ATOMIC_WITH_RET         = 0x00000007,
17255  CHC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET      = 0x00000008,
17256  CHC_PERF_SEL_REQ_NOP_ACK                 = 0x00000009,
17257  CHC_PERF_SEL_REQ_NOP_RTN0                = 0x0000000a,
17258  CHC_PERF_SEL_REQ_READ                    = 0x0000000b,
17259  CHC_PERF_SEL_REQ_READ_128B               = 0x0000000c,
17260  CHC_PERF_SEL_REQ_READ_32B                = 0x0000000d,
17261  CHC_PERF_SEL_REQ_READ_64B                = 0x0000000e,
17262  CHC_PERF_SEL_REQ_WRITE                   = 0x0000000f,
17263  CHC_PERF_SEL_REQ_WRITE_32B               = 0x00000010,
17264  CHC_PERF_SEL_REQ_WRITE_64B               = 0x00000011,
17265  CHC_PERF_SEL_STALL_GL2_GL1               = 0x00000012,
17266  CHC_PERF_SEL_STALL_BUFFER_FULL           = 0x00000013,
17267  CHC_PERF_SEL_REQ_CLIENT0                 = 0x00000014,
17268  CHC_PERF_SEL_REQ_CLIENT1                 = 0x00000015,
17269  CHC_PERF_SEL_REQ_CLIENT2                 = 0x00000016,
17270  CHC_PERF_SEL_REQ_CLIENT3                 = 0x00000017,
17271  CHC_PERF_SEL_REQ_CLIENT4                 = 0x00000018,
17272  CHC_PERF_SEL_REQ_CLIENT5                 = 0x00000019,
17273  CHC_PERF_SEL_REQ_CLIENT6                 = 0x0000001a,
17274  CHC_PERF_SEL_REQ_CLIENT7                 = 0x0000001b,
17275  CHC_PERF_SEL_REQ_CLIENT8                 = 0x0000001c,
17276  CHC_PERF_SEL_REQ_CLIENT9                 = 0x0000001d,
17277  CHC_PERF_SEL_REQ_CLIENT10                = 0x0000001e,
17278  CHC_PERF_SEL_REQ_CLIENT11                = 0x0000001f,
17279  CHC_PERF_SEL_REQ_CLIENT12                = 0x00000020,
17280  CHC_PERF_SEL_REQ_CLIENT13                = 0x00000021,
17281  CHC_PERF_SEL_REQ_CLIENT14                = 0x00000022,
17282  CHC_PERF_SEL_REQ_CLIENT15                = 0x00000023,
17283  CHC_PERF_SEL_REQ_CLIENT16                = 0x00000024,
17284  CHC_PERF_SEL_REQ_CLIENT17                = 0x00000025,
17285  CHC_PERF_SEL_REQ_CLIENT18                = 0x00000026,
17286  CHC_PERF_SEL_REQ_CLIENT19                = 0x00000027,
17287  CHC_PERF_SEL_REQ_CLIENT20                = 0x00000028,
17288  CHC_PERF_SEL_REQ_CLIENT21                = 0x00000029,
17289  CHC_PERF_SEL_REQ_CLIENT22                = 0x0000002a,
17290  CHC_PERF_SEL_REQ_CLIENT23                = 0x0000002b,
17291  } CHC_PERF_SEL;
17292  
17293  /*
17294   * GL1A_PERF_SEL enum
17295   */
17296  
17297  typedef enum GL1A_PERF_SEL {
17298  GL1A_PERF_SEL_BUSY                       = 0x00000000,
17299  GL1A_PERF_SEL_STALL_GL1C0                = 0x00000001,
17300  GL1A_PERF_SEL_STALL_GL1C1                = 0x00000002,
17301  GL1A_PERF_SEL_STALL_GL1C2                = 0x00000003,
17302  GL1A_PERF_SEL_STALL_GL1C3                = 0x00000004,
17303  GL1A_PERF_SEL_REQUEST_GL1C0              = 0x00000005,
17304  GL1A_PERF_SEL_REQUEST_GL1C1              = 0x00000006,
17305  GL1A_PERF_SEL_REQUEST_GL1C2              = 0x00000007,
17306  GL1A_PERF_SEL_REQUEST_GL1C3              = 0x00000008,
17307  GL1A_PERF_SEL_WDS_32B_GL1C0              = 0x00000009,
17308  GL1A_PERF_SEL_WDS_32B_GL1C1              = 0x0000000a,
17309  GL1A_PERF_SEL_WDS_32B_GL1C2              = 0x0000000b,
17310  GL1A_PERF_SEL_WDS_32B_GL1C3              = 0x0000000c,
17311  GL1A_PERF_SEL_BURST_COUNT_GL1C0          = 0x0000000d,
17312  GL1A_PERF_SEL_BURST_COUNT_GL1C1          = 0x0000000e,
17313  GL1A_PERF_SEL_BURST_COUNT_GL1C2          = 0x0000000f,
17314  GL1A_PERF_SEL_BURST_COUNT_GL1C3          = 0x00000010,
17315  GL1A_PERF_SEL_ARB_REQUESTS               = 0x00000011,
17316  GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL         = 0x00000012,
17317  GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0   = 0x00000013,
17318  GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1   = 0x00000014,
17319  GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2   = 0x00000015,
17320  GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3   = 0x00000016,
17321  GL1A_PERF_SEL_CYCLE                      = 0x00000017,
17322  } GL1A_PERF_SEL;
17323  
17324  /*
17325   * GL1C_PERF_SEL enum
17326   */
17327  
17328  typedef enum GL1C_PERF_SEL {
17329  GL1C_PERF_SEL_CYCLE                      = 0x00000000,
17330  GL1C_PERF_SEL_BUSY                       = 0x00000001,
17331  GL1C_PERF_SEL_STARVE                     = 0x00000002,
17332  GL1C_PERF_SEL_ARB_RET_LEVEL              = 0x00000003,
17333  GL1C_PERF_SEL_GL2_REQ_READ               = 0x00000004,
17334  GL1C_PERF_SEL_GL2_REQ_READ_128B          = 0x00000005,
17335  GL1C_PERF_SEL_GL2_REQ_READ_32B           = 0x00000006,
17336  GL1C_PERF_SEL_GL2_REQ_READ_64B           = 0x00000007,
17337  GL1C_PERF_SEL_GL2_REQ_READ_LATENCY       = 0x00000008,
17338  GL1C_PERF_SEL_GL2_REQ_WRITE              = 0x00000009,
17339  GL1C_PERF_SEL_GL2_REQ_WRITE_32B          = 0x0000000a,
17340  GL1C_PERF_SEL_GL2_REQ_WRITE_64B          = 0x0000000b,
17341  GL1C_PERF_SEL_GL2_REQ_WRITE_LATENCY      = 0x0000000c,
17342  GL1C_PERF_SEL_GL2_REQ_PREFETCH           = 0x0000000d,
17343  GL1C_PERF_SEL_REQ                        = 0x0000000e,
17344  GL1C_PERF_SEL_REQ_ATOMIC_WITH_RET        = 0x0000000f,
17345  GL1C_PERF_SEL_REQ_ATOMIC_WITHOUT_RET     = 0x00000010,
17346  GL1C_PERF_SEL_REQ_SHADER_INV             = 0x00000011,
17347  GL1C_PERF_SEL_REQ_MISS                   = 0x00000012,
17348  GL1C_PERF_SEL_REQ_NOP_ACK                = 0x00000013,
17349  GL1C_PERF_SEL_REQ_NOP_RTN0               = 0x00000014,
17350  GL1C_PERF_SEL_REQ_READ                   = 0x00000015,
17351  GL1C_PERF_SEL_REQ_READ_128B              = 0x00000016,
17352  GL1C_PERF_SEL_REQ_READ_32B               = 0x00000017,
17353  GL1C_PERF_SEL_REQ_READ_64B               = 0x00000018,
17354  GL1C_PERF_SEL_REQ_READ_POLICY_HIT_EVICT  = 0x00000019,
17355  GL1C_PERF_SEL_REQ_READ_POLICY_HIT_LRU    = 0x0000001a,
17356  GL1C_PERF_SEL_REQ_READ_POLICY_MISS_EVICT = 0x0000001b,
17357  GL1C_PERF_SEL_REQ_WRITE                  = 0x0000001c,
17358  GL1C_PERF_SEL_REQ_WRITE_32B              = 0x0000001d,
17359  GL1C_PERF_SEL_REQ_WRITE_64B              = 0x0000001e,
17360  GL1C_PERF_SEL_STALL_GL2_GL1              = 0x0000001f,
17361  GL1C_PERF_SEL_STALL_LFIFO_FULL           = 0x00000020,
17362  GL1C_PERF_SEL_STALL_NO_AVAILABLE_ACK_ALLOC = 0x00000021,
17363  GL1C_PERF_SEL_STALL_NOTHING_REPLACEABLE  = 0x00000022,
17364  GL1C_PERF_SEL_STALL_GCR_INV              = 0x00000023,
17365  GL1C_PERF_SEL_STALL_VM                   = 0x00000024,
17366  GL1C_PERF_SEL_REQ_CLIENT0                = 0x00000025,
17367  GL1C_PERF_SEL_REQ_CLIENT1                = 0x00000026,
17368  GL1C_PERF_SEL_REQ_CLIENT2                = 0x00000027,
17369  GL1C_PERF_SEL_REQ_CLIENT3                = 0x00000028,
17370  GL1C_PERF_SEL_REQ_CLIENT4                = 0x00000029,
17371  GL1C_PERF_SEL_REQ_CLIENT5                = 0x0000002a,
17372  GL1C_PERF_SEL_REQ_CLIENT6                = 0x0000002b,
17373  GL1C_PERF_SEL_REQ_CLIENT7                = 0x0000002c,
17374  GL1C_PERF_SEL_REQ_CLIENT8                = 0x0000002d,
17375  GL1C_PERF_SEL_REQ_CLIENT9                = 0x0000002e,
17376  GL1C_PERF_SEL_REQ_CLIENT10               = 0x0000002f,
17377  GL1C_PERF_SEL_REQ_CLIENT11               = 0x00000030,
17378  GL1C_PERF_SEL_REQ_CLIENT12               = 0x00000031,
17379  GL1C_PERF_SEL_REQ_CLIENT13               = 0x00000032,
17380  GL1C_PERF_SEL_REQ_CLIENT14               = 0x00000033,
17381  GL1C_PERF_SEL_REQ_CLIENT15               = 0x00000034,
17382  GL1C_PERF_SEL_REQ_CLIENT16               = 0x00000035,
17383  GL1C_PERF_SEL_REQ_CLIENT17               = 0x00000036,
17384  GL1C_PERF_SEL_REQ_CLIENT18               = 0x00000037,
17385  GL1C_PERF_SEL_REQ_CLIENT19               = 0x00000038,
17386  GL1C_PERF_SEL_REQ_CLIENT20               = 0x00000039,
17387  GL1C_PERF_SEL_REQ_CLIENT21               = 0x0000003a,
17388  GL1C_PERF_SEL_REQ_CLIENT22               = 0x0000003b,
17389  GL1C_PERF_SEL_REQ_CLIENT23               = 0x0000003c,
17390  GL1C_PERF_SEL_REQ_CLIENT24               = 0x0000003d,
17391  GL1C_PERF_SEL_REQ_CLIENT25               = 0x0000003e,
17392  GL1C_PERF_SEL_REQ_CLIENT26               = 0x0000003f,
17393  GL1C_PERF_SEL_REQ_CLIENT27               = 0x00000040,
17394  GL1C_PERF_SEL_UTCL0_REQUEST              = 0x00000041,
17395  GL1C_PERF_SEL_UTCL0_TRANSLATION_HIT      = 0x00000042,
17396  GL1C_PERF_SEL_UTCL0_TRANSLATION_MISS     = 0x00000043,
17397  GL1C_PERF_SEL_UTCL0_PERMISSION_MISS      = 0x00000044,
17398  GL1C_PERF_SEL_UTCL0_MISS_UNDER_MISS      = 0x00000045,
17399  GL1C_PERF_SEL_UTCL0_LFIFO_FULL           = 0x00000046,
17400  GL1C_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX   = 0x00000047,
17401  GL1C_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES  = 0x00000048,
17402  GL1C_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT   = 0x00000049,
17403  GL1C_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL  = 0x0000004a,
17404  GL1C_PERF_SEL_UTCL0_STALL_MULTI_MISS     = 0x0000004b,
17405  GL1C_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS = 0x0000004c,
17406  GL1C_PERF_SEL_UTCL0_UTCL1_PERM_FAULT     = 0x0000004d,
17407  GL1C_PERF_SEL_CLIENT_UTCL0_INFLIGHT      = 0x0000004e,
17408  GL1C_PERF_SEL_UTCL0_UTCL1_INFLIGHT       = 0x0000004f,
17409  GL1C_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ   = 0x00000050,
17410  GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT = 0x00000051,
17411  GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT = 0x00000052,
17412  GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT = 0x00000053,
17413  } GL1C_PERF_SEL;
17414  
17415  /*******************************************************
17416   * GL1H Enums
17417   *******************************************************/
17418  
17419  /*
17420   * GL1H_REQ_PERF_SEL enum
17421   */
17422  
17423  typedef enum GL1H_REQ_PERF_SEL {
17424  GL1H_REQ_PERF_SEL_BUSY                   = 0x00000000,
17425  GL1H_REQ_PERF_SEL_STALL_GL1_0            = 0x00000001,
17426  GL1H_REQ_PERF_SEL_STALL_GL1_1            = 0x00000002,
17427  GL1H_REQ_PERF_SEL_REQUEST_GL1_0          = 0x00000003,
17428  GL1H_REQ_PERF_SEL_REQUEST_GL1_1          = 0x00000004,
17429  GL1H_REQ_PERF_SEL_WDS_32B_GL1_0          = 0x00000005,
17430  GL1H_REQ_PERF_SEL_WDS_32B_GL1_1          = 0x00000006,
17431  GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_0      = 0x00000007,
17432  GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_1      = 0x00000008,
17433  GL1H_REQ_PERF_SEL_ARB_REQUESTS           = 0x00000009,
17434  GL1H_REQ_PERF_SEL_REQ_INFLIGHT_LEVEL     = 0x0000000a,
17435  GL1H_REQ_PERF_SEL_CYCLE                  = 0x0000000b,
17436  } GL1H_REQ_PERF_SEL;
17437  
17438  /*******************************************************
17439   * TA Enums
17440   *******************************************************/
17441  
17442  /*
17443   * TA_PERFCOUNT_SEL enum
17444   */
17445  
17446  typedef enum TA_PERFCOUNT_SEL {
17447  TA_PERF_SEL_NULL                         = 0x00000000,
17448  TA_PERF_SEL_image_sampler_has_offset_instructions = 0x00000001,
17449  TA_PERF_SEL_image_sampler_has_bias_instructions = 0x00000002,
17450  TA_PERF_SEL_image_sampler_has_reference_instructions = 0x00000003,
17451  TA_PERF_SEL_image_sampler_has_ds_instructions = 0x00000004,
17452  TA_PERF_SEL_image_sampler_has_dt_instructions = 0x00000005,
17453  TA_PERF_SEL_image_sampler_has_dr_instructions = 0x00000006,
17454  TA_PERF_SEL_gradient_busy                = 0x00000007,
17455  TA_PERF_SEL_gradient_fifo_busy           = 0x00000008,
17456  TA_PERF_SEL_lod_busy                     = 0x00000009,
17457  TA_PERF_SEL_lod_fifo_busy                = 0x0000000a,
17458  TA_PERF_SEL_addresser_busy               = 0x0000000b,
17459  TA_PERF_SEL_addresser_fifo_busy          = 0x0000000c,
17460  TA_PERF_SEL_aligner_busy                 = 0x0000000d,
17461  TA_PERF_SEL_write_path_busy              = 0x0000000e,
17462  TA_PERF_SEL_ta_busy                      = 0x0000000f,
17463  TA_PERF_SEL_image_sampler_1_input_vgpr_instructions = 0x00000010,
17464  TA_PERF_SEL_image_sampler_2_input_vgpr_instructions = 0x00000011,
17465  TA_PERF_SEL_image_sampler_3_input_vgpr_instructions = 0x00000012,
17466  TA_PERF_SEL_image_sampler_4_input_vgpr_instructions = 0x00000013,
17467  TA_PERF_SEL_image_sampler_5_input_vgpr_instructions = 0x00000014,
17468  TA_PERF_SEL_image_sampler_6_input_vgpr_instructions = 0x00000015,
17469  TA_PERF_SEL_image_sampler_7_input_vgpr_instructions = 0x00000016,
17470  TA_PERF_SEL_image_sampler_8_input_vgpr_instructions = 0x00000017,
17471  TA_PERF_SEL_image_sampler_9_input_vgpr_instructions = 0x00000018,
17472  TA_PERF_SEL_image_sampler_10_input_vgpr_instructions = 0x00000019,
17473  TA_PERF_SEL_image_sampler_11_input_vgpr_instructions = 0x0000001a,
17474  TA_PERF_SEL_image_sampler_12_input_vgpr_instructions = 0x0000001b,
17475  TA_PERF_SEL_image_sampler_has_t_instructions = 0x0000001c,
17476  TA_PERF_SEL_image_sampler_has_r_instructions = 0x0000001d,
17477  TA_PERF_SEL_image_sampler_has_q_instructions = 0x0000001e,
17478  TA_PERF_SEL_total_wavefronts             = 0x00000020,
17479  TA_PERF_SEL_gradient_cycles              = 0x00000021,
17480  TA_PERF_SEL_walker_cycles                = 0x00000022,
17481  TA_PERF_SEL_aligner_cycles               = 0x00000023,
17482  TA_PERF_SEL_image_wavefronts             = 0x00000024,
17483  TA_PERF_SEL_image_read_wavefronts        = 0x00000025,
17484  TA_PERF_SEL_image_store_wavefronts       = 0x00000026,
17485  TA_PERF_SEL_image_atomic_wavefronts      = 0x00000027,
17486  TA_PERF_SEL_image_sampler_total_cycles   = 0x00000028,
17487  TA_PERF_SEL_image_nosampler_total_cycles = 0x00000029,
17488  TA_PERF_SEL_flat_total_cycles            = 0x0000002a,
17489  TA_PERF_SEL_bvh_total_cycles             = 0x0000002b,
17490  TA_PERF_SEL_buffer_wavefronts            = 0x0000002c,
17491  TA_PERF_SEL_buffer_load_wavefronts       = 0x0000002d,
17492  TA_PERF_SEL_buffer_store_wavefronts      = 0x0000002e,
17493  TA_PERF_SEL_buffer_atomic_wavefronts     = 0x0000002f,
17494  TA_PERF_SEL_buffer_total_cycles          = 0x00000031,
17495  TA_PERF_SEL_buffer_1_address_input_vgpr_instructions = 0x00000032,
17496  TA_PERF_SEL_buffer_2_address_input_vgpr_instructions = 0x00000033,
17497  TA_PERF_SEL_buffer_has_index_instructions = 0x00000034,
17498  TA_PERF_SEL_buffer_has_offset_instructions = 0x00000035,
17499  TA_PERF_SEL_addr_stalled_by_tc_cycles    = 0x00000036,
17500  TA_PERF_SEL_addr_stalled_by_td_cycles    = 0x00000037,
17501  TA_PERF_SEL_image_sampler_wavefronts     = 0x00000038,
17502  TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles = 0x00000039,
17503  TA_PERF_SEL_addresser_stalled_cycles     = 0x0000003a,
17504  TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles = 0x0000003b,
17505  TA_PERF_SEL_aniso_stalled_cycles         = 0x0000003c,
17506  TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 0x0000003d,
17507  TA_PERF_SEL_deriv_stalled_cycles         = 0x0000003e,
17508  TA_PERF_SEL_aniso_gt1_cycle_quads        = 0x0000003f,
17509  TA_PERF_SEL_color_1_cycle_quads          = 0x00000040,
17510  TA_PERF_SEL_color_2_cycle_quads          = 0x00000041,
17511  TA_PERF_SEL_color_3_cycle_quads          = 0x00000042,
17512  TA_PERF_SEL_mip_1_cycle_quads            = 0x00000044,
17513  TA_PERF_SEL_mip_2_cycle_quads            = 0x00000045,
17514  TA_PERF_SEL_vol_1_cycle_quads            = 0x00000046,
17515  TA_PERF_SEL_vol_2_cycle_quads            = 0x00000047,
17516  TA_PERF_SEL_sampler_op_quads             = 0x00000048,
17517  TA_PERF_SEL_mipmap_lod_0_samples         = 0x00000049,
17518  TA_PERF_SEL_mipmap_lod_1_samples         = 0x0000004a,
17519  TA_PERF_SEL_mipmap_lod_2_samples         = 0x0000004b,
17520  TA_PERF_SEL_mipmap_lod_3_samples         = 0x0000004c,
17521  TA_PERF_SEL_mipmap_lod_4_samples         = 0x0000004d,
17522  TA_PERF_SEL_mipmap_lod_5_samples         = 0x0000004e,
17523  TA_PERF_SEL_mipmap_lod_6_samples         = 0x0000004f,
17524  TA_PERF_SEL_mipmap_lod_7_samples         = 0x00000050,
17525  TA_PERF_SEL_mipmap_lod_8_samples         = 0x00000051,
17526  TA_PERF_SEL_mipmap_lod_9_samples         = 0x00000052,
17527  TA_PERF_SEL_mipmap_lod_10_samples        = 0x00000053,
17528  TA_PERF_SEL_mipmap_lod_11_samples        = 0x00000054,
17529  TA_PERF_SEL_mipmap_lod_12_samples        = 0x00000055,
17530  TA_PERF_SEL_mipmap_lod_13_samples        = 0x00000056,
17531  TA_PERF_SEL_mipmap_lod_14_samples        = 0x00000057,
17532  TA_PERF_SEL_mipmap_invalid_samples       = 0x00000058,
17533  TA_PERF_SEL_aniso_1_cycle_quads          = 0x00000059,
17534  TA_PERF_SEL_aniso_2_cycle_quads          = 0x0000005a,
17535  TA_PERF_SEL_aniso_4_cycle_quads          = 0x0000005b,
17536  TA_PERF_SEL_aniso_6_cycle_quads          = 0x0000005c,
17537  TA_PERF_SEL_aniso_8_cycle_quads          = 0x0000005d,
17538  TA_PERF_SEL_aniso_10_cycle_quads         = 0x0000005e,
17539  TA_PERF_SEL_aniso_12_cycle_quads         = 0x0000005f,
17540  TA_PERF_SEL_aniso_14_cycle_quads         = 0x00000060,
17541  TA_PERF_SEL_aniso_16_cycle_quads         = 0x00000061,
17542  TA_PERF_SEL_store_write_data_input_cycles = 0x00000062,
17543  TA_PERF_SEL_store_write_data_output_cycles = 0x00000063,
17544  TA_PERF_SEL_flat_wavefronts              = 0x00000064,
17545  TA_PERF_SEL_flat_load_wavefronts         = 0x00000065,
17546  TA_PERF_SEL_flat_store_wavefronts        = 0x00000066,
17547  TA_PERF_SEL_flat_atomic_wavefronts       = 0x00000067,
17548  TA_PERF_SEL_flat_1_address_input_vgpr_instructions = 0x00000068,
17549  TA_PERF_SEL_register_clk_valid_cycles    = 0x00000069,
17550  TA_PERF_SEL_non_harvestable_clk_enabled_cycles = 0x0000006a,
17551  TA_PERF_SEL_harvestable_clk_enabled_cycles = 0x0000006b,
17552  TA_PERF_SEL_harvestable_register_clk_enabled_cycles = 0x0000006c,
17553  TA_PERF_SEL_boundary_non_harvestable_clk_enabled_cycles = 0x0000006d,
17554  TA_PERF_SEL_boundary_harvestable_clk_enabled_cycles = 0x0000006e,
17555  TA_PERF_SEL_store_2_write_data_vgpr_instructions = 0x00000072,
17556  TA_PERF_SEL_store_3_write_data_vgpr_instructions = 0x00000073,
17557  TA_PERF_SEL_store_4_write_data_vgpr_instructions = 0x00000074,
17558  TA_PERF_SEL_store_has_x_instructions     = 0x00000075,
17559  TA_PERF_SEL_store_has_y_instructions     = 0x00000076,
17560  TA_PERF_SEL_store_has_z_instructions     = 0x00000077,
17561  TA_PERF_SEL_store_has_w_instructions     = 0x00000078,
17562  TA_PERF_SEL_image_nosampler_has_t_instructions = 0x00000079,
17563  TA_PERF_SEL_image_nosampler_has_r_instructions = 0x0000007a,
17564  TA_PERF_SEL_image_nosampler_has_q_instructions = 0x0000007b,
17565  TA_PERF_SEL_image_nosampler_1_address_input_vgpr_instructions = 0x0000007c,
17566  TA_PERF_SEL_image_nosampler_2_address_input_vgpr_instructions = 0x0000007d,
17567  TA_PERF_SEL_image_nosampler_3_address_input_vgpr_instructions = 0x0000007e,
17568  TA_PERF_SEL_image_nosampler_4_address_input_vgpr_instructions = 0x0000007f,
17569  TA_PERF_SEL_in_busy                      = 0x00000080,
17570  TA_PERF_SEL_in_fifos_busy                = 0x00000081,
17571  TA_PERF_SEL_in_cfifo_busy                = 0x00000082,
17572  TA_PERF_SEL_in_qfifo_busy                = 0x00000083,
17573  TA_PERF_SEL_in_wfifo_busy                = 0x00000084,
17574  TA_PERF_SEL_in_rfifo_busy                = 0x00000085,
17575  TA_PERF_SEL_bf_busy                      = 0x00000086,
17576  TA_PERF_SEL_ns_busy                      = 0x00000087,
17577  TA_PERF_SEL_smp_busy_ns_idle             = 0x00000088,
17578  TA_PERF_SEL_smp_idle_ns_busy             = 0x00000089,
17579  TA_PERF_SEL_vmemcmd_cycles               = 0x00000090,
17580  TA_PERF_SEL_vmemreq_cycles               = 0x00000091,
17581  TA_PERF_SEL_in_waiting_on_req_cycles     = 0x00000092,
17582  TA_PERF_SEL_in_addr_cycles               = 0x00000096,
17583  TA_PERF_SEL_in_data_cycles               = 0x00000097,
17584  TA_PERF_SEL_latency_ram_weights_written_cycles = 0x0000009a,
17585  TA_PERF_SEL_latency_ram_ws_required_quads = 0x0000009b,
17586  TA_PERF_SEL_latency_ram_whv_required_quads = 0x0000009c,
17587  TA_PERF_SEL_latency_ram_ws_required_instructions = 0x0000009d,
17588  TA_PERF_SEL_latency_ram_whv_required_instructions = 0x0000009e,
17589  TA_PERF_SEL_latency_ram_ref_required_instructions = 0x0000009f,
17590  TA_PERF_SEL_point_sampled_quads          = 0x000000a0,
17591  TA_PERF_SEL_atomic_2_write_data_vgpr_instructions = 0x000000a2,
17592  TA_PERF_SEL_atomic_4_write_data_vgpr_instructions = 0x000000a3,
17593  TA_PERF_SEL_atomic_write_data_input_cycles = 0x000000a4,
17594  TA_PERF_SEL_atomic_write_data_output_cycles = 0x000000a5,
17595  TA_PERF_SEL_num_unlit_nodes_ta_opt       = 0x000000ad,
17596  TA_PERF_SEL_num_nodes_invalidated_due_to_bad_input = 0x000000ae,
17597  TA_PERF_SEL_num_nodes_invalidated_due_to_oob = 0x000000af,
17598  TA_PERF_SEL_num_of_bvh_valid_first_tri   = 0x000000b0,
17599  TA_PERF_SEL_num_of_bvh_valid_second_tri  = 0x000000b1,
17600  TA_PERF_SEL_num_of_bvh_valid_third_tri   = 0x000000b2,
17601  TA_PERF_SEL_num_of_bvh_valid_fourth_tri  = 0x000000b3,
17602  TA_PERF_SEL_num_of_bvh_valid_fp16_box    = 0x000000b4,
17603  TA_PERF_SEL_num_of_bvh_valid_fp32_box    = 0x000000b5,
17604  TA_PERF_SEL_num_of_bvh_invalidated_first_tri = 0x000000b6,
17605  TA_PERF_SEL_num_of_bvh_invalidated_second_tri = 0x000000b7,
17606  TA_PERF_SEL_num_of_bvh_invalidated_third_tri = 0x000000b8,
17607  TA_PERF_SEL_num_of_bvh_invalidated_fourth_tri = 0x000000b9,
17608  TA_PERF_SEL_num_of_bvh_invalidated_fp16_box = 0x000000ba,
17609  TA_PERF_SEL_num_of_bvh_invalidated_fp32_box = 0x000000bb,
17610  TA_PERF_SEL_image_bvh_8_input_vgpr_instructions = 0x000000bc,
17611  TA_PERF_SEL_image_bvh_9_input_vgpr_instructions = 0x000000bd,
17612  TA_PERF_SEL_image_bvh_11_input_vgpr_instructions = 0x000000be,
17613  TA_PERF_SEL_image_bvh_12_input_vgpr_instructions = 0x000000bf,
17614  TA_PERF_SEL_image_sampler_1_op_burst     = 0x000000c0,
17615  TA_PERF_SEL_image_sampler_2to3_op_burst  = 0x000000c1,
17616  TA_PERF_SEL_image_sampler_4to7_op_burst  = 0x000000c2,
17617  TA_PERF_SEL_image_sampler_ge8_op_burst   = 0x000000c3,
17618  TA_PERF_SEL_image_linked_1_op_burst      = 0x000000c4,
17619  TA_PERF_SEL_image_linked_2to3_op_burst   = 0x000000c5,
17620  TA_PERF_SEL_image_linked_4to7_op_burst   = 0x000000c6,
17621  TA_PERF_SEL_image_linked_ge8_op_burst    = 0x000000c7,
17622  TA_PERF_SEL_image_bvh_1_op_burst         = 0x000000c8,
17623  TA_PERF_SEL_image_bvh_2to3_op_burst      = 0x000000c9,
17624  TA_PERF_SEL_image_bvh_4to7_op_burst      = 0x000000ca,
17625  TA_PERF_SEL_image_bvh_ge8_op_burst       = 0x000000cb,
17626  TA_PERF_SEL_image_nosampler_1_op_burst   = 0x000000cc,
17627  TA_PERF_SEL_image_nosampler_2to3_op_burst = 0x000000cd,
17628  TA_PERF_SEL_image_nosampler_4to31_op_burst = 0x000000ce,
17629  TA_PERF_SEL_image_nosampler_ge32_op_burst = 0x000000cf,
17630  TA_PERF_SEL_buffer_flat_1_op_burst       = 0x000000d0,
17631  TA_PERF_SEL_buffer_flat_2to3_op_burst    = 0x000000d1,
17632  TA_PERF_SEL_buffer_flat_4to31_op_burst   = 0x000000d2,
17633  TA_PERF_SEL_buffer_flat_ge32_op_burst    = 0x000000d3,
17634  TA_PERF_SEL_write_1_op_burst             = 0x000000d4,
17635  TA_PERF_SEL_write_2to3_op_burst          = 0x000000d5,
17636  TA_PERF_SEL_write_4to31_op_burst         = 0x000000d6,
17637  TA_PERF_SEL_write_ge32_op_burst          = 0x000000d7,
17638  TA_PERF_SEL_ibubble_1_cycle_burst        = 0x000000d8,
17639  TA_PERF_SEL_ibubble_2to3_cycle_burst     = 0x000000d9,
17640  TA_PERF_SEL_ibubble_4to15_cycle_burst    = 0x000000da,
17641  TA_PERF_SEL_ibubble_16to31_cycle_burst   = 0x000000db,
17642  TA_PERF_SEL_ibubble_32to63_cycle_burst   = 0x000000dc,
17643  TA_PERF_SEL_ibubble_ge64_cycle_burst     = 0x000000dd,
17644  TA_PERF_SEL_sampler_clk_valid_cycles     = 0x000000e0,
17645  TA_PERF_SEL_nonsampler_clk_valid_cycles  = 0x000000e1,
17646  TA_PERF_SEL_buffer_flat_clk_valid_cycles = 0x000000e2,
17647  TA_PERF_SEL_write_data_clk_valid_cycles  = 0x000000e3,
17648  TA_PERF_SEL_gradient_clk_valid_cycles    = 0x000000e4,
17649  TA_PERF_SEL_lod_aniso_clk_valid_cycles   = 0x000000e5,
17650  TA_PERF_SEL_sampler_addressing_clk_valid_cycles = 0x000000e6,
17651  TA_PERF_SEL_sync_sampler_sstate_fifo_clk_valid_cycles = 0x000000e7,
17652  TA_PERF_SEL_sync_sampler_cstate_fifo_clk_valid_cycles = 0x000000e8,
17653  TA_PERF_SEL_sync_nonsampler_fifo_clk_valid_cycles = 0x000000e9,
17654  TA_PERF_SEL_aligner_clk_valid_cycles     = 0x000000ea,
17655  TA_PERF_SEL_tcreq_clk_valid_cycles       = 0x000000eb,
17656  } TA_PERFCOUNT_SEL;
17657  
17658  /*
17659   * TEX_BC_SWIZZLE enum
17660   */
17661  
17662  typedef enum TEX_BC_SWIZZLE {
17663  TEX_BC_Swizzle_XYZW                      = 0x00000000,
17664  TEX_BC_Swizzle_XWYZ                      = 0x00000001,
17665  TEX_BC_Swizzle_WZYX                      = 0x00000002,
17666  TEX_BC_Swizzle_WXYZ                      = 0x00000003,
17667  TEX_BC_Swizzle_ZYXW                      = 0x00000004,
17668  TEX_BC_Swizzle_YXWZ                      = 0x00000005,
17669  } TEX_BC_SWIZZLE;
17670  
17671  /*
17672   * TEX_BORDER_COLOR_TYPE enum
17673   */
17674  
17675  typedef enum TEX_BORDER_COLOR_TYPE {
17676  TEX_BorderColor_TransparentBlack         = 0x00000000,
17677  TEX_BorderColor_OpaqueBlack              = 0x00000001,
17678  TEX_BorderColor_OpaqueWhite              = 0x00000002,
17679  TEX_BorderColor_Register                 = 0x00000003,
17680  } TEX_BORDER_COLOR_TYPE;
17681  
17682  /*
17683   * TEX_CHROMA_KEY enum
17684   */
17685  
17686  typedef enum TEX_CHROMA_KEY {
17687  TEX_ChromaKey_Disabled                   = 0x00000000,
17688  TEX_ChromaKey_Kill                       = 0x00000001,
17689  TEX_ChromaKey_Blend                      = 0x00000002,
17690  TEX_ChromaKey_RESERVED_3                 = 0x00000003,
17691  } TEX_CHROMA_KEY;
17692  
17693  /*
17694   * TEX_CLAMP enum
17695   */
17696  
17697  typedef enum TEX_CLAMP {
17698  TEX_Clamp_Repeat                         = 0x00000000,
17699  TEX_Clamp_Mirror                         = 0x00000001,
17700  TEX_Clamp_ClampToLast                    = 0x00000002,
17701  TEX_Clamp_MirrorOnceToLast               = 0x00000003,
17702  TEX_Clamp_ClampHalfToBorder              = 0x00000004,
17703  TEX_Clamp_MirrorOnceHalfToBorder         = 0x00000005,
17704  TEX_Clamp_ClampToBorder                  = 0x00000006,
17705  TEX_Clamp_MirrorOnceToBorder             = 0x00000007,
17706  } TEX_CLAMP;
17707  
17708  /*
17709   * TEX_COORD_TYPE enum
17710   */
17711  
17712  typedef enum TEX_COORD_TYPE {
17713  TEX_CoordType_Unnormalized               = 0x00000000,
17714  TEX_CoordType_Normalized                 = 0x00000001,
17715  } TEX_COORD_TYPE;
17716  
17717  /*
17718   * TEX_DEPTH_COMPARE_FUNCTION enum
17719   */
17720  
17721  typedef enum TEX_DEPTH_COMPARE_FUNCTION {
17722  TEX_DepthCompareFunction_Never           = 0x00000000,
17723  TEX_DepthCompareFunction_Less            = 0x00000001,
17724  TEX_DepthCompareFunction_Equal           = 0x00000002,
17725  TEX_DepthCompareFunction_LessEqual       = 0x00000003,
17726  TEX_DepthCompareFunction_Greater         = 0x00000004,
17727  TEX_DepthCompareFunction_NotEqual        = 0x00000005,
17728  TEX_DepthCompareFunction_GreaterEqual    = 0x00000006,
17729  TEX_DepthCompareFunction_Always          = 0x00000007,
17730  } TEX_DEPTH_COMPARE_FUNCTION;
17731  
17732  /*
17733   * TEX_FORMAT_COMP enum
17734   */
17735  
17736  typedef enum TEX_FORMAT_COMP {
17737  TEX_FormatComp_Unsigned                  = 0x00000000,
17738  TEX_FormatComp_Signed                    = 0x00000001,
17739  TEX_FormatComp_UnsignedBiased            = 0x00000002,
17740  TEX_FormatComp_RESERVED_3                = 0x00000003,
17741  } TEX_FORMAT_COMP;
17742  
17743  /*
17744   * TEX_MAX_ANISO_RATIO enum
17745   */
17746  
17747  typedef enum TEX_MAX_ANISO_RATIO {
17748  TEX_MaxAnisoRatio_1to1                   = 0x00000000,
17749  TEX_MaxAnisoRatio_2to1                   = 0x00000001,
17750  TEX_MaxAnisoRatio_4to1                   = 0x00000002,
17751  TEX_MaxAnisoRatio_8to1                   = 0x00000003,
17752  TEX_MaxAnisoRatio_16to1                  = 0x00000004,
17753  TEX_MaxAnisoRatio_RESERVED_5             = 0x00000005,
17754  TEX_MaxAnisoRatio_RESERVED_6             = 0x00000006,
17755  TEX_MaxAnisoRatio_RESERVED_7             = 0x00000007,
17756  } TEX_MAX_ANISO_RATIO;
17757  
17758  /*
17759   * TEX_MIP_FILTER enum
17760   */
17761  
17762  typedef enum TEX_MIP_FILTER {
17763  TEX_MipFilter_None                       = 0x00000000,
17764  TEX_MipFilter_Point                      = 0x00000001,
17765  TEX_MipFilter_Linear                     = 0x00000002,
17766  TEX_MipFilter_Point_Aniso_Adj            = 0x00000003,
17767  } TEX_MIP_FILTER;
17768  
17769  /*
17770   * TEX_REQUEST_SIZE enum
17771   */
17772  
17773  typedef enum TEX_REQUEST_SIZE {
17774  TEX_RequestSize_32B                      = 0x00000000,
17775  TEX_RequestSize_64B                      = 0x00000001,
17776  TEX_RequestSize_128B                     = 0x00000002,
17777  TEX_RequestSize_2X64B                    = 0x00000003,
17778  } TEX_REQUEST_SIZE;
17779  
17780  /*
17781   * TEX_SAMPLER_TYPE enum
17782   */
17783  
17784  typedef enum TEX_SAMPLER_TYPE {
17785  TEX_SamplerType_Invalid                  = 0x00000000,
17786  TEX_SamplerType_Valid                    = 0x00000001,
17787  } TEX_SAMPLER_TYPE;
17788  
17789  /*
17790   * TEX_XY_FILTER enum
17791   */
17792  
17793  typedef enum TEX_XY_FILTER {
17794  TEX_XYFilter_Point                       = 0x00000000,
17795  TEX_XYFilter_Linear                      = 0x00000001,
17796  TEX_XYFilter_AnisoPoint                  = 0x00000002,
17797  TEX_XYFilter_AnisoLinear                 = 0x00000003,
17798  } TEX_XY_FILTER;
17799  
17800  /*
17801   * TEX_Z_FILTER enum
17802   */
17803  
17804  typedef enum TEX_Z_FILTER {
17805  TEX_ZFilter_None                         = 0x00000000,
17806  TEX_ZFilter_Point                        = 0x00000001,
17807  TEX_ZFilter_Linear                       = 0x00000002,
17808  TEX_ZFilter_RESERVED_3                   = 0x00000003,
17809  } TEX_Z_FILTER;
17810  
17811  /*
17812   * TVX_TYPE enum
17813   */
17814  
17815  typedef enum TVX_TYPE {
17816  TVX_Type_InvalidTextureResource          = 0x00000000,
17817  TVX_Type_InvalidVertexBuffer             = 0x00000001,
17818  TVX_Type_ValidTextureResource            = 0x00000002,
17819  TVX_Type_ValidVertexBuffer               = 0x00000003,
17820  } TVX_TYPE;
17821  
17822  /*******************************************************
17823   * TCP Enums
17824   *******************************************************/
17825  
17826  /*
17827   * TA_TC_ADDR_MODES enum
17828   */
17829  
17830  typedef enum TA_TC_ADDR_MODES {
17831  TA_TC_ADDR_MODE_DEFAULT                  = 0x00000000,
17832  TA_TC_ADDR_MODE_COMP0                    = 0x00000001,
17833  TA_TC_ADDR_MODE_COMP1                    = 0x00000002,
17834  TA_TC_ADDR_MODE_COMP2                    = 0x00000003,
17835  TA_TC_ADDR_MODE_COMP3                    = 0x00000004,
17836  TA_TC_ADDR_MODE_UNALIGNED                = 0x00000005,
17837  TA_TC_ADDR_MODE_BORDER_COLOR             = 0x00000006,
17838  } TA_TC_ADDR_MODES;
17839  
17840  /*
17841   * TA_TC_REQ_MODES enum
17842   */
17843  
17844  typedef enum TA_TC_REQ_MODES {
17845  TA_TC_REQ_MODE_BORDER                    = 0x00000000,
17846  TA_TC_REQ_MODE_TEX2                      = 0x00000001,
17847  TA_TC_REQ_MODE_TEX1                      = 0x00000002,
17848  TA_TC_REQ_MODE_TEX0                      = 0x00000003,
17849  TA_TC_REQ_MODE_NORMAL                    = 0x00000004,
17850  TA_TC_REQ_MODE_DWORD                     = 0x00000005,
17851  TA_TC_REQ_MODE_BYTE                      = 0x00000006,
17852  TA_TC_REQ_MODE_BYTE_NV                   = 0x00000007,
17853  } TA_TC_REQ_MODES;
17854  
17855  /*
17856   * TCP_CACHE_POLICIES enum
17857   */
17858  
17859  typedef enum TCP_CACHE_POLICIES {
17860  TCP_CACHE_POLICY_MISS_LRU                = 0x00000000,
17861  TCP_CACHE_POLICY_MISS_EVICT              = 0x00000001,
17862  TCP_CACHE_POLICY_HIT_LRU                 = 0x00000002,
17863  TCP_CACHE_POLICY_HIT_EVICT               = 0x00000003,
17864  } TCP_CACHE_POLICIES;
17865  
17866  /*
17867   * TCP_CACHE_STORE_POLICIES enum
17868   */
17869  
17870  typedef enum TCP_CACHE_STORE_POLICIES {
17871  TCP_CACHE_STORE_POLICY_WT_LRU            = 0x00000000,
17872  TCP_CACHE_STORE_POLICY_WT_EVICT          = 0x00000001,
17873  } TCP_CACHE_STORE_POLICIES;
17874  
17875  /*
17876   * TCP_DSM_DATA_SEL enum
17877   */
17878  
17879  typedef enum TCP_DSM_DATA_SEL {
17880  TCP_DSM_DISABLE                          = 0x00000000,
17881  TCP_DSM_SEL0                             = 0x00000001,
17882  TCP_DSM_SEL1                             = 0x00000002,
17883  TCP_DSM_SEL_BOTH                         = 0x00000003,
17884  } TCP_DSM_DATA_SEL;
17885  
17886  /*
17887   * TCP_DSM_INJECT_SEL enum
17888   */
17889  
17890  typedef enum TCP_DSM_INJECT_SEL {
17891  TCP_DSM_INJECT_SEL0                      = 0x00000000,
17892  TCP_DSM_INJECT_SEL1                      = 0x00000001,
17893  TCP_DSM_INJECT_SEL2                      = 0x00000002,
17894  TCP_DSM_INJECT_SEL3                      = 0x00000003,
17895  } TCP_DSM_INJECT_SEL;
17896  
17897  /*
17898   * TCP_DSM_SINGLE_WRITE enum
17899   */
17900  
17901  typedef enum TCP_DSM_SINGLE_WRITE {
17902  TCP_DSM_SINGLE_WRITE_DIS                 = 0x00000000,
17903  TCP_DSM_SINGLE_WRITE_EN                  = 0x00000001,
17904  } TCP_DSM_SINGLE_WRITE;
17905  
17906  /*
17907   * TCP_OPCODE_TYPE enum
17908   */
17909  
17910  typedef enum TCP_OPCODE_TYPE {
17911  TCP_OPCODE_READ                          = 0x00000000,
17912  TCP_OPCODE_WRITE                         = 0x00000001,
17913  TCP_OPCODE_ATOMIC                        = 0x00000002,
17914  TCP_OPCODE_INV                           = 0x00000003,
17915  TCP_OPCODE_ATOMIC_CMPSWAP                = 0x00000004,
17916  TCP_OPCODE_SAMPLER                       = 0x00000005,
17917  TCP_OPCODE_LOAD                          = 0x00000006,
17918  TCP_OPCODE_GATHERH                       = 0x00000007,
17919  } TCP_OPCODE_TYPE;
17920  
17921  /*
17922   * TCP_PERFCOUNT_SELECT enum
17923   */
17924  
17925  typedef enum TCP_PERFCOUNT_SELECT {
17926  TCP_PERF_SEL_GATE_EN1                    = 0x00000000,
17927  TCP_PERF_SEL_GATE_EN2                    = 0x00000001,
17928  TCP_PERF_SEL_TA_REQ                      = 0x00000002,
17929  TCP_PERF_SEL_TA_REQ_STATE_READ           = 0x00000003,
17930  TCP_PERF_SEL_TA_REQ_READ                 = 0x00000004,
17931  TCP_PERF_SEL_TA_REQ_WRITE                = 0x00000005,
17932  TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET      = 0x00000006,
17933  TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET   = 0x00000007,
17934  TCP_PERF_SEL_TA_REQ_GL0_INV              = 0x00000008,
17935  TCP_PERF_SEL_REQ                         = 0x00000009,
17936  TCP_PERF_SEL_REQ_READ                    = 0x0000000a,
17937  TCP_PERF_SEL_REQ_READ_HIT_EVICT          = 0x0000000b,
17938  TCP_PERF_SEL_REQ_READ_HIT_LRU            = 0x0000000c,
17939  TCP_PERF_SEL_REQ_READ_MISS_EVICT         = 0x0000000d,
17940  TCP_PERF_SEL_REQ_WRITE                   = 0x0000000e,
17941  TCP_PERF_SEL_REQ_WRITE_MISS_EVICT        = 0x0000000f,
17942  TCP_PERF_SEL_REQ_WRITE_MISS_LRU          = 0x00000010,
17943  TCP_PERF_SEL_REQ_NON_READ                = 0x00000011,
17944  TCP_PERF_SEL_REQ_MISS                    = 0x00000012,
17945  TCP_PERF_SEL_REQ_TAGBANK0_SET0           = 0x00000013,
17946  TCP_PERF_SEL_REQ_TAGBANK0_SET1           = 0x00000014,
17947  TCP_PERF_SEL_REQ_TAGBANK1_SET0           = 0x00000015,
17948  TCP_PERF_SEL_REQ_TAGBANK1_SET1           = 0x00000016,
17949  TCP_PERF_SEL_REQ_TAGBANK2_SET0           = 0x00000017,
17950  TCP_PERF_SEL_REQ_TAGBANK2_SET1           = 0x00000018,
17951  TCP_PERF_SEL_REQ_TAGBANK3_SET0           = 0x00000019,
17952  TCP_PERF_SEL_REQ_TAGBANK3_SET1           = 0x0000001a,
17953  TCP_PERF_SEL_REQ_MISS_TAGBANK0           = 0x0000001b,
17954  TCP_PERF_SEL_REQ_MISS_TAGBANK1           = 0x0000001c,
17955  TCP_PERF_SEL_REQ_MISS_TAGBANK2           = 0x0000001d,
17956  TCP_PERF_SEL_REQ_MISS_TAGBANK3           = 0x0000001e,
17957  TCP_PERF_SEL_GL1_REQ_READ                = 0x0000001f,
17958  TCP_PERF_SEL_GL1_REQ_READ_128B           = 0x00000020,
17959  TCP_PERF_SEL_GL1_REQ_READ_64B            = 0x00000021,
17960  TCP_PERF_SEL_GL1_REQ_WRITE               = 0x00000022,
17961  TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET     = 0x00000023,
17962  TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET  = 0x00000024,
17963  TCP_PERF_SEL_GL1_READ_LATENCY            = 0x00000025,
17964  TCP_PERF_SEL_GL1_WRITE_LATENCY           = 0x00000026,
17965  TCP_PERF_SEL_TCP_LATENCY                 = 0x00000027,
17966  TCP_PERF_SEL_TCP_TA_REQ_STALL            = 0x00000028,
17967  TCP_PERF_SEL_TA_TCP_REQ_STARVE           = 0x00000029,
17968  TCP_PERF_SEL_DATA_FIFO_STALL             = 0x0000002a,
17969  TCP_PERF_SEL_LOD_STALL                   = 0x0000002b,
17970  TCP_PERF_SEL_POWER_STALL                 = 0x0000002c,
17971  TCP_PERF_SEL_ALLOC_STALL                 = 0x0000002d,
17972  TCP_PERF_SEL_UNORDERED_MTYPE_STALL       = 0x0000002e,
17973  TCP_PERF_SEL_READ_TAGCONFLICT_STALL      = 0x0000002f,
17974  TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL     = 0x00000030,
17975  TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL    = 0x00000031,
17976  TCP_PERF_SEL_LFIFO_STALL                 = 0x00000032,
17977  TCP_PERF_SEL_MEM_REQ_FIFO_STALL          = 0x00000033,
17978  TCP_PERF_SEL_GL1_TCP_BACK_PRESSURE       = 0x00000034,
17979  TCP_PERF_SEL_GL1_TCP_RDRET_STALL         = 0x00000035,
17980  TCP_PERF_SEL_GL1_GRANT_READ_STALL        = 0x00000036,
17981  TCP_PERF_SEL_GL1_PENDING_STALL           = 0x00000037,
17982  TCP_PERF_SEL_OFIFO_INCOMPLETE_STALL      = 0x00000038,
17983  TCP_PERF_SEL_OFIFO_AGE_ORDER_STALL       = 0x00000039,
17984  TCP_PERF_SEL_TD_DATA_CYCLE_STALL         = 0x0000003a,
17985  TCP_PERF_SEL_COMP_TEX_LOAD_STALL         = 0x0000003b,
17986  TCP_PERF_SEL_READ_DATACONFLICT_STALL     = 0x0000003c,
17987  TCP_PERF_SEL_WRITE_DATACONFLICT_STALL    = 0x0000003d,
17988  TCP_PERF_SEL_TD_TCP_STALL                = 0x0000003e,
17989  } TCP_PERFCOUNT_SELECT;
17990  
17991  /*
17992   * TCP_WATCH_MODES enum
17993   */
17994  
17995  typedef enum TCP_WATCH_MODES {
17996  TCP_WATCH_MODE_READ                      = 0x00000000,
17997  TCP_WATCH_MODE_NONREAD                   = 0x00000001,
17998  TCP_WATCH_MODE_ATOMIC                    = 0x00000002,
17999  TCP_WATCH_MODE_ALL                       = 0x00000003,
18000  } TCP_WATCH_MODES;
18001  
18002  /*******************************************************
18003   * TD Enums
18004   *******************************************************/
18005  
18006  /*
18007   * TD_PERFCOUNT_SEL enum
18008   */
18009  
18010  typedef enum TD_PERFCOUNT_SEL {
18011  TD_PERF_SEL_none                         = 0x00000000,
18012  TD_PERF_SEL_td_busy                      = 0x00000001,
18013  TD_PERF_SEL_input_busy                   = 0x00000002,
18014  TD_PERF_SEL_sampler_lerp_busy            = 0x00000003,
18015  TD_PERF_SEL_sampler_out_busy             = 0x00000004,
18016  TD_PERF_SEL_nofilter_busy                = 0x00000005,
18017  TD_PERF_SEL_ray_tracing_bvh4_busy        = 0x00000006,
18018  TD_PERF_SEL_sampler_core_sclk_en         = 0x00000007,
18019  TD_PERF_SEL_sampler_preformatter_sclk_en = 0x00000008,
18020  TD_PERF_SEL_sampler_bilerp_sclk_en       = 0x00000009,
18021  TD_PERF_SEL_sampler_bypass_sclk_en       = 0x0000000a,
18022  TD_PERF_SEL_sampler_minmax_sclk_en       = 0x0000000b,
18023  TD_PERF_SEL_sampler_accum_sclk_en        = 0x0000000c,
18024  TD_PERF_SEL_sampler_format_flt_sclk_en   = 0x0000000d,
18025  TD_PERF_SEL_sampler_format_fxdpt_sclk_en = 0x0000000e,
18026  TD_PERF_SEL_sampler_out_sclk_en          = 0x0000000f,
18027  TD_PERF_SEL_nofilter_sclk_en             = 0x00000010,
18028  TD_PERF_SEL_nofilter_d32_sclk_en         = 0x00000011,
18029  TD_PERF_SEL_nofilter_d16_sclk_en         = 0x00000012,
18030  TD_PERF_SEL_ray_tracing_bvh4_sclk_en     = 0x00000016,
18031  TD_PERF_SEL_ray_tracing_bvh4_ip_sclk_en  = 0x00000017,
18032  TD_PERF_SEL_ray_tracing_bvh4_box_sclk_en = 0x00000018,
18033  TD_PERF_SEL_ray_tracing_bvh4_tri_sclk_en = 0x00000019,
18034  TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off = 0x0000001a,
18035  TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off = 0x0000001b,
18036  TD_PERF_SEL_all_pipes_sclk_on_at_same_time = 0x0000001c,
18037  TD_PERF_SEL_sampler_and_nofilter_sclk_on_bvh4_sclk_off = 0x0000001d,
18038  TD_PERF_SEL_sampler_and_bvh4_sclk_on_nofilter_sclk_off = 0x0000001e,
18039  TD_PERF_SEL_nofilter_and_bvh4_sclk_on_sampler_sclk_off = 0x0000001f,
18040  TD_PERF_SEL_core_state_ram_max_cnt       = 0x00000020,
18041  TD_PERF_SEL_core_state_rams_read         = 0x00000021,
18042  TD_PERF_SEL_weight_data_rams_read        = 0x00000022,
18043  TD_PERF_SEL_reference_data_rams_read     = 0x00000023,
18044  TD_PERF_SEL_tc_td_ram_fifo_full          = 0x00000024,
18045  TD_PERF_SEL_tc_td_ram_fifo_max_cnt       = 0x00000025,
18046  TD_PERF_SEL_tc_td_data_fifo_full         = 0x00000026,
18047  TD_PERF_SEL_input_state_fifo_full        = 0x00000027,
18048  TD_PERF_SEL_ta_data_stall                = 0x00000028,
18049  TD_PERF_SEL_tc_data_stall                = 0x00000029,
18050  TD_PERF_SEL_tc_ram_stall                 = 0x0000002a,
18051  TD_PERF_SEL_lds_stall                    = 0x0000002b,
18052  TD_PERF_SEL_sampler_pkr_full             = 0x0000002c,
18053  TD_PERF_SEL_sampler_pkr_full_due_to_arb  = 0x0000002d,
18054  TD_PERF_SEL_nofilter_pkr_full            = 0x0000002e,
18055  TD_PERF_SEL_nofilter_pkr_full_due_to_arb = 0x0000002f,
18056  TD_PERF_SEL_ray_tracing_bvh4_pkr_full    = 0x00000030,
18057  TD_PERF_SEL_ray_tracing_bvh4_pkr_full_due_to_arb = 0x00000031,
18058  TD_PERF_SEL_gather4_instr                = 0x00000032,
18059  TD_PERF_SEL_gather4h_instr               = 0x00000033,
18060  TD_PERF_SEL_sample_instr                 = 0x00000036,
18061  TD_PERF_SEL_sample_c_instr               = 0x00000037,
18062  TD_PERF_SEL_load_instr                   = 0x00000038,
18063  TD_PERF_SEL_ldfptr_instr                 = 0x00000039,
18064  TD_PERF_SEL_write_ack_instr              = 0x0000003a,
18065  TD_PERF_SEL_d16_en_instr                 = 0x0000003b,
18066  TD_PERF_SEL_bypassLerp_instr             = 0x0000003c,
18067  TD_PERF_SEL_min_max_filter_instr         = 0x0000003d,
18068  TD_PERF_SEL_one_comp_return_instr        = 0x0000003e,
18069  TD_PERF_SEL_two_comp_return_instr        = 0x0000003f,
18070  TD_PERF_SEL_three_comp_return_instr      = 0x00000040,
18071  TD_PERF_SEL_four_comp_return_instr       = 0x00000041,
18072  TD_PERF_SEL_user_defined_border          = 0x00000042,
18073  TD_PERF_SEL_white_border                 = 0x00000043,
18074  TD_PERF_SEL_opaque_black_border          = 0x00000044,
18075  TD_PERF_SEL_lod_warn_from_ta             = 0x00000045,
18076  TD_PERF_SEL_instruction_dest_is_lds      = 0x00000046,
18077  TD_PERF_SEL_td_cycling_of_nofilter_instr_2cycles = 0x00000047,
18078  TD_PERF_SEL_td_cycling_of_nofilter_instr_4cycles = 0x00000048,
18079  TD_PERF_SEL_tc_cycling_of_nofilter_instr_2cycles = 0x00000049,
18080  TD_PERF_SEL_tc_cycling_of_nofilter_instr_4cycles = 0x0000004a,
18081  TD_PERF_SEL_out_of_order_instr           = 0x0000004b,
18082  TD_PERF_SEL_total_num_instr              = 0x0000004c,
18083  TD_PERF_SEL_total_num_instr_with_perf_wdw = 0x0000004d,
18084  TD_PERF_SEL_total_num_sampler_instr      = 0x0000004e,
18085  TD_PERF_SEL_total_num_sampler_instr_with_perf_wdw = 0x0000004f,
18086  TD_PERF_SEL_total_num_nofilter_instr     = 0x00000050,
18087  TD_PERF_SEL_total_num_nofilter_instr_with_perf_wdw = 0x00000051,
18088  TD_PERF_SEL_total_num_ray_tracing_bvh4_instr = 0x00000052,
18089  TD_PERF_SEL_total_num_ray_tracing_bvh4_instr_with_perf_wdw = 0x00000053,
18090  TD_PERF_SEL_mixmode_instr                = 0x00000054,
18091  TD_PERF_SEL_mixmode_resource             = 0x00000055,
18092  TD_PERF_SEL_status_packet                = 0x00000056,
18093  TD_PERF_SEL_address_cmd_poison           = 0x00000057,
18094  TD_PERF_SEL_data_poison                  = 0x00000058,
18095  TD_PERF_SEL_done_scoreboard_max_stored_cnt = 0x00000059,
18096  TD_PERF_SEL_done_scoreboard_max_waiting_cnt = 0x0000005a,
18097  TD_PERF_SEL_done_scoreboard_not_empty    = 0x0000005b,
18098  TD_PERF_SEL_done_scoreboard_is_full      = 0x0000005c,
18099  TD_PERF_SEL_done_scoreboard_bp_due_to_ooo = 0x0000005d,
18100  TD_PERF_SEL_done_scoreboard_bp_due_to_lds = 0x0000005e,
18101  TD_PERF_SEL_nofilter_formatters_turned_on = 0x0000005f,
18102  TD_PERF_SEL_nofilter_insert_extra_comps  = 0x00000060,
18103  TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt = 0x00000061,
18104  TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt = 0x00000062,
18105  TD_PERF_SEL_msaa_load_instr              = 0x00000063,
18106  TD_PERF_SEL_blend_prt_with_prt_default_0 = 0x00000064,
18107  TD_PERF_SEL_blend_prt_with_prt_default_1 = 0x00000065,
18108  TD_PERF_SEL_resmap_instr                 = 0x00000066,
18109  TD_PERF_SEL_prt_ack_instr                = 0x00000067,
18110  TD_PERF_SEL_resmap_with_volume_filtering = 0x00000068,
18111  TD_PERF_SEL_resmap_with_aniso_filtering  = 0x00000069,
18112  TD_PERF_SEL_resmap_with_no_more_filtering = 0x0000006a,
18113  TD_PERF_SEL_resmap_with_cubemap_corner   = 0x0000006b,
18114  TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_0 = 0x0000006c,
18115  TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_1 = 0x0000006d,
18116  TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_2 = 0x0000006e,
18117  TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_3to4 = 0x0000006f,
18118  TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_5to8 = 0x00000070,
18119  TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_9to16 = 0x00000071,
18120  TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_17to31 = 0x00000072,
18121  TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_32 = 0x00000073,
18122  TD_PERF_SEL_ray_tracing_bvh4_fp16_box_node = 0x00000074,
18123  TD_PERF_SEL_ray_tracing_bvh4_fp32_box_node = 0x00000075,
18124  TD_PERF_SEL_ray_tracing_bvh4_tri_node    = 0x00000076,
18125  TD_PERF_SEL_ray_tracing_bvh4_dropped_box_node = 0x00000077,
18126  TD_PERF_SEL_ray_tracing_bvh4_dropped_tri_node = 0x00000078,
18127  TD_PERF_SEL_ray_tracing_bvh4_invalid_box_node = 0x00000079,
18128  TD_PERF_SEL_ray_tracing_bvh4_invalid_tri_node = 0x0000007a,
18129  TD_PERF_SEL_ray_tracing_bvh4_box_sort_en = 0x0000007b,
18130  TD_PERF_SEL_ray_tracing_bvh4_box_grow_val_nonzero = 0x0000007c,
18131  TD_PERF_SEL_ray_tracing_bvh4_num_box_with_inf_or_nan_vtx = 0x0000007d,
18132  TD_PERF_SEL_ray_tracing_bvh4_num_tri_with_inf_or_nan_vtx = 0x0000007e,
18133  TD_PERF_SEL_ray_tracing_bvh4_num_box_that_squashed_a_nan = 0x0000007f,
18134  TD_PERF_SEL_ray_tracing_bvh4_num_box_misses = 0x00000080,
18135  TD_PERF_SEL_ray_tracing_bvh4_num_tri_misses = 0x00000081,
18136  TD_PERF_SEL_ray_tracing_bvh4_num_tri_tie_breakers = 0x00000082,
18137  TD_PERF_SEL_burst_bin_preempting_nofilter_1 = 0x00000083,
18138  TD_PERF_SEL_burst_bin_preempting_nofilter_2to4 = 0x00000084,
18139  TD_PERF_SEL_burst_bin_preempting_nofilter_5to7 = 0x00000085,
18140  TD_PERF_SEL_burst_bin_preempting_nofilter_8to16 = 0x00000086,
18141  TD_PERF_SEL_burst_bin_preempting_nofilter_gt16 = 0x00000087,
18142  TD_PERF_SEL_burst_bin_sampler_1          = 0x00000088,
18143  TD_PERF_SEL_burst_bin_sampler_2to8       = 0x00000089,
18144  TD_PERF_SEL_burst_bin_sampler_9to16      = 0x0000008a,
18145  TD_PERF_SEL_burst_bin_sampler_gt16       = 0x0000008b,
18146  TD_PERF_SEL_burst_bin_gather_1           = 0x0000008c,
18147  TD_PERF_SEL_burst_bin_gather_2to8        = 0x0000008d,
18148  TD_PERF_SEL_burst_bin_gather_9to16       = 0x0000008e,
18149  TD_PERF_SEL_burst_bin_gather_gt16        = 0x0000008f,
18150  TD_PERF_SEL_burst_bin_nofilter_1         = 0x00000090,
18151  TD_PERF_SEL_burst_bin_nofilter_2to4      = 0x00000091,
18152  TD_PERF_SEL_burst_bin_nofilter_5to7      = 0x00000092,
18153  TD_PERF_SEL_burst_bin_nofilter_8to16     = 0x00000093,
18154  TD_PERF_SEL_burst_bin_nofilter_gt16      = 0x00000094,
18155  TD_PERF_SEL_burst_bin_bvh4_1             = 0x00000095,
18156  TD_PERF_SEL_burst_bin_bvh4_2to8          = 0x00000096,
18157  TD_PERF_SEL_burst_bin_bvh4_9to16         = 0x00000097,
18158  TD_PERF_SEL_burst_bin_bvh4_gt16          = 0x00000098,
18159  TD_PERF_SEL_burst_bin_bvh4_box_nodes_1   = 0x00000099,
18160  TD_PERF_SEL_burst_bin_bvh4_box_nodes_2to4 = 0x0000009a,
18161  TD_PERF_SEL_burst_bin_bvh4_box_nodes_5to7 = 0x0000009b,
18162  TD_PERF_SEL_burst_bin_bvh4_box_nodes_8to16 = 0x0000009c,
18163  TD_PERF_SEL_burst_bin_bvh4_box_nodes_gt16 = 0x0000009d,
18164  TD_PERF_SEL_burst_bin_bvh4_tri_nodes_1   = 0x0000009e,
18165  TD_PERF_SEL_burst_bin_bvh4_tri_nodes_2to8 = 0x0000009f,
18166  TD_PERF_SEL_burst_bin_bvh4_tri_nodes_9to16 = 0x000000a0,
18167  TD_PERF_SEL_burst_bin_bvh4_tri_nodes_gt16 = 0x000000a1,
18168  TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_1 = 0x000000a2,
18169  TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_2to8 = 0x000000a3,
18170  TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_9to16 = 0x000000a4,
18171  TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_gt16 = 0x000000a5,
18172  TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_1 = 0x000000a6,
18173  TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_2to8 = 0x000000a7,
18174  TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_9to16 = 0x000000a8,
18175  TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_gt16 = 0x000000a9,
18176  TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_0 = 0x000000aa,
18177  TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_1 = 0x000000ab,
18178  TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_2to31 = 0x000000ac,
18179  TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_32to127 = 0x000000ad,
18180  TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_128to511 = 0x000000ae,
18181  TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_gt511 = 0x000000af,
18182  TD_PERF_SEL_bubble_bin_lds_stall_1to3    = 0x000000b0,
18183  TD_PERF_SEL_bubble_bin_lds_stall_4to7    = 0x000000b1,
18184  TD_PERF_SEL_bubble_bin_lds_stall_8to15   = 0x000000b2,
18185  TD_PERF_SEL_bubble_bin_lds_stall_gt15    = 0x000000b3,
18186  TD_PERF_SEL_preempting_nofilter_max_cnt  = 0x000000b4,
18187  TD_PERF_SEL_sampler_lerp0_active         = 0x000000b5,
18188  TD_PERF_SEL_sampler_lerp1_active         = 0x000000b6,
18189  TD_PERF_SEL_sampler_lerp2_active         = 0x000000b7,
18190  TD_PERF_SEL_sampler_lerp3_active         = 0x000000b8,
18191  TD_PERF_SEL_nofilter_total_num_comps_to_lds = 0x000000b9,
18192  TD_PERF_SEL_nofilter_byte_cycling_4cycles = 0x000000ba,
18193  TD_PERF_SEL_nofilter_byte_cycling_8cycles = 0x000000bb,
18194  TD_PERF_SEL_nofilter_byte_cycling_16cycles = 0x000000bc,
18195  TD_PERF_SEL_nofilter_dword_cycling_2cycles = 0x000000bd,
18196  TD_PERF_SEL_nofilter_dword_cycling_4cycles = 0x000000be,
18197  TD_PERF_SEL_input_bp_due_to_done_scoreboard_full = 0x000000bf,
18198  TD_PERF_SEL_ray_tracing_bvh4_instr_invld_thread_cnt = 0x000000c0,
18199  } TD_PERFCOUNT_SEL;
18200  
18201  /*******************************************************
18202   * GL2C Enums
18203   *******************************************************/
18204  
18205  /*
18206   * GL2A_PERF_SEL enum
18207   */
18208  
18209  typedef enum GL2A_PERF_SEL {
18210  GL2A_PERF_SEL_NONE                       = 0x00000000,
18211  GL2A_PERF_SEL_CYCLE                      = 0x00000001,
18212  GL2A_PERF_SEL_BUSY                       = 0x00000002,
18213  GL2A_PERF_SEL_REQ_GL2C0                  = 0x00000003,
18214  GL2A_PERF_SEL_REQ_GL2C1                  = 0x00000004,
18215  GL2A_PERF_SEL_REQ_GL2C2                  = 0x00000005,
18216  GL2A_PERF_SEL_REQ_GL2C3                  = 0x00000006,
18217  GL2A_PERF_SEL_REQ_GL2C4                  = 0x00000007,
18218  GL2A_PERF_SEL_REQ_GL2C5                  = 0x00000008,
18219  GL2A_PERF_SEL_REQ_GL2C6                  = 0x00000009,
18220  GL2A_PERF_SEL_REQ_GL2C7                  = 0x0000000a,
18221  GL2A_PERF_SEL_REQ_HI_PRIO_GL2C0          = 0x0000000b,
18222  GL2A_PERF_SEL_REQ_HI_PRIO_GL2C1          = 0x0000000c,
18223  GL2A_PERF_SEL_REQ_HI_PRIO_GL2C2          = 0x0000000d,
18224  GL2A_PERF_SEL_REQ_HI_PRIO_GL2C3          = 0x0000000e,
18225  GL2A_PERF_SEL_REQ_HI_PRIO_GL2C4          = 0x0000000f,
18226  GL2A_PERF_SEL_REQ_HI_PRIO_GL2C5          = 0x00000010,
18227  GL2A_PERF_SEL_REQ_HI_PRIO_GL2C6          = 0x00000011,
18228  GL2A_PERF_SEL_REQ_HI_PRIO_GL2C7          = 0x00000012,
18229  GL2A_PERF_SEL_REQ_BURST_GL2C0            = 0x00000013,
18230  GL2A_PERF_SEL_REQ_BURST_GL2C1            = 0x00000014,
18231  GL2A_PERF_SEL_REQ_BURST_GL2C2            = 0x00000015,
18232  GL2A_PERF_SEL_REQ_BURST_GL2C3            = 0x00000016,
18233  GL2A_PERF_SEL_REQ_BURST_GL2C4            = 0x00000017,
18234  GL2A_PERF_SEL_REQ_BURST_GL2C5            = 0x00000018,
18235  GL2A_PERF_SEL_REQ_BURST_GL2C6            = 0x00000019,
18236  GL2A_PERF_SEL_REQ_BURST_GL2C7            = 0x0000001a,
18237  GL2A_PERF_SEL_REQ_STALL_GL2C0            = 0x0000001b,
18238  GL2A_PERF_SEL_REQ_STALL_GL2C1            = 0x0000001c,
18239  GL2A_PERF_SEL_REQ_STALL_GL2C2            = 0x0000001d,
18240  GL2A_PERF_SEL_REQ_STALL_GL2C3            = 0x0000001e,
18241  GL2A_PERF_SEL_REQ_STALL_GL2C4            = 0x0000001f,
18242  GL2A_PERF_SEL_REQ_STALL_GL2C5            = 0x00000020,
18243  GL2A_PERF_SEL_REQ_STALL_GL2C6            = 0x00000021,
18244  GL2A_PERF_SEL_REQ_STALL_GL2C7            = 0x00000022,
18245  GL2A_PERF_SEL_RTN_STALL_GL2C0            = 0x00000023,
18246  GL2A_PERF_SEL_RTN_STALL_GL2C1            = 0x00000024,
18247  GL2A_PERF_SEL_RTN_STALL_GL2C2            = 0x00000025,
18248  GL2A_PERF_SEL_RTN_STALL_GL2C3            = 0x00000026,
18249  GL2A_PERF_SEL_RTN_STALL_GL2C4            = 0x00000027,
18250  GL2A_PERF_SEL_RTN_STALL_GL2C5            = 0x00000028,
18251  GL2A_PERF_SEL_RTN_STALL_GL2C6            = 0x00000029,
18252  GL2A_PERF_SEL_RTN_STALL_GL2C7            = 0x0000002a,
18253  GL2A_PERF_SEL_RTN_CLIENT0                = 0x0000002b,
18254  GL2A_PERF_SEL_RTN_CLIENT1                = 0x0000002c,
18255  GL2A_PERF_SEL_RTN_CLIENT2                = 0x0000002d,
18256  GL2A_PERF_SEL_RTN_CLIENT3                = 0x0000002e,
18257  GL2A_PERF_SEL_RTN_CLIENT4                = 0x0000002f,
18258  GL2A_PERF_SEL_RTN_CLIENT5                = 0x00000030,
18259  GL2A_PERF_SEL_RTN_CLIENT6                = 0x00000031,
18260  GL2A_PERF_SEL_RTN_CLIENT7                = 0x00000032,
18261  GL2A_PERF_SEL_RTN_CLIENT8                = 0x00000033,
18262  GL2A_PERF_SEL_RTN_CLIENT9                = 0x00000034,
18263  GL2A_PERF_SEL_RTN_CLIENT10               = 0x00000035,
18264  GL2A_PERF_SEL_RTN_CLIENT11               = 0x00000036,
18265  GL2A_PERF_SEL_RTN_CLIENT12               = 0x00000037,
18266  GL2A_PERF_SEL_RTN_CLIENT13               = 0x00000038,
18267  GL2A_PERF_SEL_RTN_CLIENT14               = 0x00000039,
18268  GL2A_PERF_SEL_RTN_CLIENT15               = 0x0000003a,
18269  GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0  = 0x0000003b,
18270  GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1  = 0x0000003c,
18271  GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2  = 0x0000003d,
18272  GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3  = 0x0000003e,
18273  GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4  = 0x0000003f,
18274  GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5  = 0x00000040,
18275  GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6  = 0x00000041,
18276  GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7  = 0x00000042,
18277  GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT8  = 0x00000043,
18278  GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT9  = 0x00000044,
18279  GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT10 = 0x00000045,
18280  GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT11 = 0x00000046,
18281  GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT12 = 0x00000047,
18282  GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT13 = 0x00000048,
18283  GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT14 = 0x00000049,
18284  GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT15 = 0x0000004a,
18285  GL2A_PERF_SEL_REQ_BURST_CLIENT0          = 0x0000004b,
18286  GL2A_PERF_SEL_REQ_BURST_CLIENT1          = 0x0000004c,
18287  GL2A_PERF_SEL_REQ_BURST_CLIENT2          = 0x0000004d,
18288  GL2A_PERF_SEL_REQ_BURST_CLIENT3          = 0x0000004e,
18289  GL2A_PERF_SEL_REQ_BURST_CLIENT4          = 0x0000004f,
18290  GL2A_PERF_SEL_REQ_BURST_CLIENT5          = 0x00000050,
18291  GL2A_PERF_SEL_REQ_BURST_CLIENT6          = 0x00000051,
18292  GL2A_PERF_SEL_REQ_BURST_CLIENT7          = 0x00000052,
18293  GL2A_PERF_SEL_REQ_BURST_CLIENT8          = 0x00000053,
18294  GL2A_PERF_SEL_REQ_BURST_CLIENT9          = 0x00000054,
18295  GL2A_PERF_SEL_REQ_BURST_CLIENT10         = 0x00000055,
18296  GL2A_PERF_SEL_REQ_BURST_CLIENT11         = 0x00000056,
18297  GL2A_PERF_SEL_REQ_BURST_CLIENT12         = 0x00000057,
18298  GL2A_PERF_SEL_REQ_BURST_CLIENT13         = 0x00000058,
18299  GL2A_PERF_SEL_REQ_BURST_CLIENT14         = 0x00000059,
18300  GL2A_PERF_SEL_REQ_BURST_CLIENT15         = 0x0000005a,
18301  GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT0   = 0x0000005b,
18302  GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT1   = 0x0000005c,
18303  GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT2   = 0x0000005d,
18304  GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT3   = 0x0000005e,
18305  GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT4   = 0x0000005f,
18306  GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT5   = 0x00000060,
18307  GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT6   = 0x00000061,
18308  GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT7   = 0x00000062,
18309  GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT8   = 0x00000063,
18310  GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT9   = 0x00000064,
18311  GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT10  = 0x00000065,
18312  GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT11  = 0x00000067,
18313  GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT12  = 0x00000068,
18314  GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT13  = 0x00000069,
18315  GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT14  = 0x0000006a,
18316  GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT15  = 0x0000006b,
18317  } GL2A_PERF_SEL;
18318  
18319  /*
18320   * GL2C_PERF_SEL enum
18321   */
18322  
18323  typedef enum GL2C_PERF_SEL {
18324  GL2C_PERF_SEL_NONE                       = 0x00000000,
18325  GL2C_PERF_SEL_CYCLE                      = 0x00000001,
18326  GL2C_PERF_SEL_BUSY                       = 0x00000002,
18327  GL2C_PERF_SEL_REQ                        = 0x00000003,
18328  GL2C_PERF_SEL_VOL_REQ                    = 0x00000004,
18329  GL2C_PERF_SEL_HIGH_PRIORITY_REQ          = 0x00000005,
18330  GL2C_PERF_SEL_READ                       = 0x00000006,
18331  GL2C_PERF_SEL_WRITE                      = 0x00000007,
18332  GL2C_PERF_SEL_ATOMIC                     = 0x00000008,
18333  GL2C_PERF_SEL_NOP_ACK                    = 0x00000009,
18334  GL2C_PERF_SEL_NOP_RTN0                   = 0x0000000a,
18335  GL2C_PERF_SEL_PROBE                      = 0x0000000b,
18336  GL2C_PERF_SEL_PROBE_ALL                  = 0x0000000c,
18337  GL2C_PERF_SEL_INTERNAL_PROBE             = 0x0000000d,
18338  GL2C_PERF_SEL_COMPRESSED_READ_REQ        = 0x0000000e,
18339  GL2C_PERF_SEL_METADATA_READ_REQ          = 0x0000000f,
18340  GL2C_PERF_SEL_CLIENT0_REQ                = 0x00000010,
18341  GL2C_PERF_SEL_CLIENT1_REQ                = 0x00000011,
18342  GL2C_PERF_SEL_CLIENT2_REQ                = 0x00000012,
18343  GL2C_PERF_SEL_CLIENT3_REQ                = 0x00000013,
18344  GL2C_PERF_SEL_CLIENT4_REQ                = 0x00000014,
18345  GL2C_PERF_SEL_CLIENT5_REQ                = 0x00000015,
18346  GL2C_PERF_SEL_CLIENT6_REQ                = 0x00000016,
18347  GL2C_PERF_SEL_CLIENT7_REQ                = 0x00000017,
18348  GL2C_PERF_SEL_CLIENT8_REQ                = 0x00000018,
18349  GL2C_PERF_SEL_CLIENT9_REQ                = 0x00000019,
18350  GL2C_PERF_SEL_CLIENT10_REQ               = 0x0000001a,
18351  GL2C_PERF_SEL_CLIENT11_REQ               = 0x0000001b,
18352  GL2C_PERF_SEL_CLIENT12_REQ               = 0x0000001c,
18353  GL2C_PERF_SEL_CLIENT13_REQ               = 0x0000001d,
18354  GL2C_PERF_SEL_CLIENT14_REQ               = 0x0000001e,
18355  GL2C_PERF_SEL_CLIENT15_REQ               = 0x0000001f,
18356  GL2C_PERF_SEL_C_RW_S_REQ                 = 0x00000020,
18357  GL2C_PERF_SEL_C_RW_US_REQ                = 0x00000021,
18358  GL2C_PERF_SEL_C_RO_S_REQ                 = 0x00000022,
18359  GL2C_PERF_SEL_C_RO_US_REQ                = 0x00000023,
18360  GL2C_PERF_SEL_UC_REQ                     = 0x00000024,
18361  GL2C_PERF_SEL_LRU_REQ                    = 0x00000025,
18362  GL2C_PERF_SEL_STREAM_REQ                 = 0x00000026,
18363  GL2C_PERF_SEL_BYPASS_REQ                 = 0x00000027,
18364  GL2C_PERF_SEL_NOA_REQ                    = 0x00000028,
18365  GL2C_PERF_SEL_SHARED_REQ                 = 0x00000029,
18366  GL2C_PERF_SEL_HIT                        = 0x0000002a,
18367  GL2C_PERF_SEL_MISS                       = 0x0000002b,
18368  GL2C_PERF_SEL_FULL_HIT                   = 0x0000002c,
18369  GL2C_PERF_SEL_PARTIAL_32B_HIT            = 0x0000002d,
18370  GL2C_PERF_SEL_PARTIAL_64B_HIT            = 0x0000002e,
18371  GL2C_PERF_SEL_PARTIAL_96B_HIT            = 0x0000002f,
18372  GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT       = 0x00000030,
18373  GL2C_PERF_SEL_FULLY_WRITTEN_HIT          = 0x00000031,
18374  GL2C_PERF_SEL_UNCACHED_WRITE             = 0x00000032,
18375  GL2C_PERF_SEL_WRITEBACK                  = 0x00000033,
18376  GL2C_PERF_SEL_NORMAL_WRITEBACK           = 0x00000034,
18377  GL2C_PERF_SEL_EVICT                      = 0x00000035,
18378  GL2C_PERF_SEL_NORMAL_EVICT               = 0x00000036,
18379  GL2C_PERF_SEL_PROBE_EVICT                = 0x00000037,
18380  GL2C_PERF_SEL_REQ_TO_MISS_QUEUE          = 0x00000038,
18381  GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0   = 0x00000039,
18382  GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1   = 0x0000003a,
18383  GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2   = 0x0000003b,
18384  GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3   = 0x0000003c,
18385  GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4   = 0x0000003d,
18386  GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5   = 0x0000003e,
18387  GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6   = 0x0000003f,
18388  GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7   = 0x00000040,
18389  GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT8   = 0x00000041,
18390  GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT9   = 0x00000042,
18391  GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT10  = 0x00000043,
18392  GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT11  = 0x00000044,
18393  GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT12  = 0x00000045,
18394  GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT13  = 0x00000046,
18395  GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT14  = 0x00000047,
18396  GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT15  = 0x00000048,
18397  GL2C_PERF_SEL_READ_32_REQ                = 0x00000049,
18398  GL2C_PERF_SEL_READ_64_REQ                = 0x0000004a,
18399  GL2C_PERF_SEL_READ_128_REQ               = 0x0000004b,
18400  GL2C_PERF_SEL_WRITE_32_REQ               = 0x0000004c,
18401  GL2C_PERF_SEL_WRITE_64_REQ               = 0x0000004d,
18402  GL2C_PERF_SEL_COMPRESSED_READ_0_REQ      = 0x0000004e,
18403  GL2C_PERF_SEL_COMPRESSED_READ_32_REQ     = 0x0000004f,
18404  GL2C_PERF_SEL_COMPRESSED_READ_64_REQ     = 0x00000050,
18405  GL2C_PERF_SEL_COMPRESSED_READ_96_REQ     = 0x00000051,
18406  GL2C_PERF_SEL_COMPRESSED_READ_128_REQ    = 0x00000052,
18407  GL2C_PERF_SEL_MC_WRREQ                   = 0x00000053,
18408  GL2C_PERF_SEL_EA_WRREQ_SNOOP             = 0x00000054,
18409  GL2C_PERF_SEL_EA_WRREQ_64B               = 0x00000055,
18410  GL2C_PERF_SEL_EA_WRREQ_PROBE_COMMAND     = 0x00000056,
18411  GL2C_PERF_SEL_EA_WR_UNCACHED_32B         = 0x00000057,
18412  GL2C_PERF_SEL_MC_WRREQ_STALL             = 0x00000058,
18413  GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL   = 0x00000059,
18414  GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL  = 0x0000005a,
18415  GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL = 0x0000005b,
18416  GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL   = 0x0000005c,
18417  GL2C_PERF_SEL_MC_WRREQ_LEVEL             = 0x0000005d,
18418  GL2C_PERF_SEL_EA_ATOMIC                  = 0x0000005e,
18419  GL2C_PERF_SEL_EA_ATOMIC_LEVEL            = 0x0000005f,
18420  GL2C_PERF_SEL_MC_RDREQ                   = 0x00000060,
18421  GL2C_PERF_SEL_EA_RDREQ_SNOOP             = 0x00000061,
18422  GL2C_PERF_SEL_EA_RDREQ_SPLIT             = 0x00000062,
18423  GL2C_PERF_SEL_EA_RDREQ_32B               = 0x00000063,
18424  GL2C_PERF_SEL_EA_RDREQ_64B               = 0x00000064,
18425  GL2C_PERF_SEL_EA_RDREQ_96B               = 0x00000065,
18426  GL2C_PERF_SEL_EA_RDREQ_128B              = 0x00000066,
18427  GL2C_PERF_SEL_EA_RD_UNCACHED_32B         = 0x00000067,
18428  GL2C_PERF_SEL_EA_RD_MDC_32B              = 0x00000068,
18429  GL2C_PERF_SEL_EA_RD_COMPRESSED_32B       = 0x00000069,
18430  GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL   = 0x0000006a,
18431  GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL  = 0x0000006b,
18432  GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL = 0x0000006c,
18433  GL2C_PERF_SEL_MC_RDREQ_LEVEL             = 0x0000006d,
18434  GL2C_PERF_SEL_EA_RDREQ_DRAM              = 0x0000006e,
18435  GL2C_PERF_SEL_EA_WRREQ_DRAM              = 0x0000006f,
18436  GL2C_PERF_SEL_EA_RDREQ_DRAM_32B          = 0x00000070,
18437  GL2C_PERF_SEL_EA_WRREQ_DRAM_32B          = 0x00000071,
18438  GL2C_PERF_SEL_ONION_READ                 = 0x00000072,
18439  GL2C_PERF_SEL_ONION_WRITE                = 0x00000073,
18440  GL2C_PERF_SEL_IO_READ                    = 0x00000074,
18441  GL2C_PERF_SEL_IO_WRITE                   = 0x00000075,
18442  GL2C_PERF_SEL_GARLIC_READ                = 0x00000076,
18443  GL2C_PERF_SEL_GARLIC_WRITE               = 0x00000077,
18444  GL2C_PERF_SEL_EA_OUTSTANDING             = 0x00000078,
18445  GL2C_PERF_SEL_LATENCY_FIFO_FULL          = 0x00000079,
18446  GL2C_PERF_SEL_SRC_FIFO_FULL              = 0x0000007a,
18447  GL2C_PERF_SEL_TAG_STALL                  = 0x0000007b,
18448  GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL = 0x0000007c,
18449  GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 0x0000007d,
18450  GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL = 0x0000007e,
18451  GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL = 0x0000007f,
18452  GL2C_PERF_SEL_TAG_PROBE_STALL            = 0x00000080,
18453  GL2C_PERF_SEL_TAG_PROBE_FILTER_STALL     = 0x00000081,
18454  GL2C_PERF_SEL_TAG_PROBE_FIFO_FULL_STALL  = 0x00000082,
18455  GL2C_PERF_SEL_TAG_READ_DST_STALL         = 0x00000083,
18456  GL2C_PERF_SEL_READ_RETURN_TIMEOUT        = 0x00000084,
18457  GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT     = 0x00000085,
18458  GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE    = 0x00000086,
18459  GL2C_PERF_SEL_BUBBLE                     = 0x00000087,
18460  GL2C_PERF_SEL_IB_REQ                     = 0x00000088,
18461  GL2C_PERF_SEL_IB_STALL                   = 0x00000089,
18462  GL2C_PERF_SEL_IB_TAG_STALL               = 0x0000008a,
18463  GL2C_PERF_SEL_IB_CM_STALL                = 0x0000008b,
18464  GL2C_PERF_SEL_RETURN_ACK                 = 0x0000008c,
18465  GL2C_PERF_SEL_RETURN_DATA                = 0x0000008d,
18466  GL2C_PERF_SEL_EA_RDRET_NACK              = 0x0000008e,
18467  GL2C_PERF_SEL_EA_WRRET_NACK              = 0x0000008f,
18468  GL2C_PERF_SEL_GL2A_LEVEL                 = 0x00000090,
18469  GL2C_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION = 0x00000091,
18470  GL2C_PERF_SEL_PROBE_FILTER_DISABLED      = 0x00000092,
18471  GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START  = 0x00000093,
18472  GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START = 0x00000094,
18473  GL2C_PERF_SEL_GCR_INV                    = 0x00000095,
18474  GL2C_PERF_SEL_GCR_WB                     = 0x00000096,
18475  GL2C_PERF_SEL_GCR_DISCARD                = 0x00000097,
18476  GL2C_PERF_SEL_GCR_RANGE                  = 0x00000098,
18477  GL2C_PERF_SEL_GCR_ALL                    = 0x00000099,
18478  GL2C_PERF_SEL_GCR_VOL                    = 0x0000009a,
18479  GL2C_PERF_SEL_GCR_UNSHARED               = 0x0000009b,
18480  GL2C_PERF_SEL_GCR_MDC_INV                = 0x0000009c,
18481  GL2C_PERF_SEL_GCR_GL2_INV_ALL            = 0x0000009d,
18482  GL2C_PERF_SEL_GCR_GL2_WB_ALL             = 0x0000009e,
18483  GL2C_PERF_SEL_GCR_MDC_INV_ALL            = 0x0000009f,
18484  GL2C_PERF_SEL_GCR_GL2_INV_RANGE          = 0x000000a0,
18485  GL2C_PERF_SEL_GCR_GL2_WB_RANGE           = 0x000000a1,
18486  GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE       = 0x000000a2,
18487  GL2C_PERF_SEL_GCR_MDC_INV_RANGE          = 0x000000a3,
18488  GL2C_PERF_SEL_ALL_GCR_INV_EVICT          = 0x000000a4,
18489  GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT      = 0x000000a5,
18490  GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE    = 0x000000a6,
18491  GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE = 0x000000a7,
18492  GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK       = 0x000000a8,
18493  GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE        = 0x000000a9,
18494  GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT        = 0x000000aa,
18495  GL2C_PERF_SEL_GCR_INVL2_VOL_START        = 0x000000ab,
18496  GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE         = 0x000000ac,
18497  GL2C_PERF_SEL_GCR_WBL2_VOL_START         = 0x000000ad,
18498  GL2C_PERF_SEL_GCR_WBINVL2_CYCLE          = 0x000000ae,
18499  GL2C_PERF_SEL_GCR_WBINVL2_EVICT          = 0x000000af,
18500  GL2C_PERF_SEL_GCR_WBINVL2_START          = 0x000000b0,
18501  GL2C_PERF_SEL_MDC_INV_METADATA           = 0x000000b1,
18502  GL2C_PERF_SEL_MDC_REQ                    = 0x000000b2,
18503  GL2C_PERF_SEL_MDC_LEVEL                  = 0x000000b3,
18504  GL2C_PERF_SEL_MDC_TAG_HIT                = 0x000000b4,
18505  GL2C_PERF_SEL_MDC_SECTOR_HIT             = 0x000000b5,
18506  GL2C_PERF_SEL_MDC_SECTOR_MISS            = 0x000000b6,
18507  GL2C_PERF_SEL_MDC_TAG_STALL              = 0x000000b7,
18508  GL2C_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL = 0x000000b8,
18509  GL2C_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL = 0x000000b9,
18510  GL2C_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL = 0x000000ba,
18511  GL2C_PERF_SEL_CM_CHANNEL0_REQ            = 0x000000bb,
18512  GL2C_PERF_SEL_CM_CHANNEL1_REQ            = 0x000000bc,
18513  GL2C_PERF_SEL_CM_CHANNEL2_REQ            = 0x000000bd,
18514  GL2C_PERF_SEL_CM_CHANNEL3_REQ            = 0x000000be,
18515  GL2C_PERF_SEL_CM_CHANNEL4_REQ            = 0x000000bf,
18516  GL2C_PERF_SEL_CM_CHANNEL5_REQ            = 0x000000c0,
18517  GL2C_PERF_SEL_CM_CHANNEL6_REQ            = 0x000000c1,
18518  GL2C_PERF_SEL_CM_CHANNEL7_REQ            = 0x000000c2,
18519  GL2C_PERF_SEL_CM_CHANNEL8_REQ            = 0x000000c3,
18520  GL2C_PERF_SEL_CM_CHANNEL9_REQ            = 0x000000c4,
18521  GL2C_PERF_SEL_CM_CHANNEL10_REQ           = 0x000000c5,
18522  GL2C_PERF_SEL_CM_CHANNEL11_REQ           = 0x000000c6,
18523  GL2C_PERF_SEL_CM_CHANNEL12_REQ           = 0x000000c7,
18524  GL2C_PERF_SEL_CM_CHANNEL13_REQ           = 0x000000c8,
18525  GL2C_PERF_SEL_CM_CHANNEL14_REQ           = 0x000000c9,
18526  GL2C_PERF_SEL_CM_CHANNEL15_REQ           = 0x000000ca,
18527  GL2C_PERF_SEL_CM_CHANNEL16_REQ           = 0x000000cb,
18528  GL2C_PERF_SEL_CM_CHANNEL17_REQ           = 0x000000cc,
18529  GL2C_PERF_SEL_CM_CHANNEL18_REQ           = 0x000000cd,
18530  GL2C_PERF_SEL_CM_CHANNEL19_REQ           = 0x000000ce,
18531  GL2C_PERF_SEL_CM_CHANNEL20_REQ           = 0x000000cf,
18532  GL2C_PERF_SEL_CM_CHANNEL21_REQ           = 0x000000d0,
18533  GL2C_PERF_SEL_CM_CHANNEL22_REQ           = 0x000000d1,
18534  GL2C_PERF_SEL_CM_CHANNEL23_REQ           = 0x000000d2,
18535  GL2C_PERF_SEL_CM_CHANNEL24_REQ           = 0x000000d3,
18536  GL2C_PERF_SEL_CM_CHANNEL25_REQ           = 0x000000d4,
18537  GL2C_PERF_SEL_CM_CHANNEL26_REQ           = 0x000000d5,
18538  GL2C_PERF_SEL_CM_CHANNEL27_REQ           = 0x000000d6,
18539  GL2C_PERF_SEL_CM_CHANNEL28_REQ           = 0x000000d7,
18540  GL2C_PERF_SEL_CM_CHANNEL29_REQ           = 0x000000d8,
18541  GL2C_PERF_SEL_CM_CHANNEL30_REQ           = 0x000000d9,
18542  GL2C_PERF_SEL_CM_CHANNEL31_REQ           = 0x000000da,
18543  GL2C_PERF_SEL_CM_COMP_ATOMIC_COLOR_REQ   = 0x000000db,
18544  GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH16_REQ = 0x000000dc,
18545  GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH32_REQ = 0x000000dd,
18546  GL2C_PERF_SEL_CM_COMP_ATOMIC_STENCIL_REQ = 0x000000de,
18547  GL2C_PERF_SEL_CM_COMP_WRITE_COLOR_REQ    = 0x000000df,
18548  GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH16_REQ  = 0x000000e0,
18549  GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH32_REQ  = 0x000000e1,
18550  GL2C_PERF_SEL_CM_COMP_WRITE_STENCIL_REQ  = 0x000000e2,
18551  GL2C_PERF_SEL_CM_COMP_READ_REQ           = 0x000000e3,
18552  GL2C_PERF_SEL_CM_READ_BACK_REQ           = 0x000000e4,
18553  GL2C_PERF_SEL_CM_METADATA_WR_REQ         = 0x000000e5,
18554  GL2C_PERF_SEL_CM_WR_ACK_REQ              = 0x000000e6,
18555  GL2C_PERF_SEL_CM_NO_ACK_REQ              = 0x000000e7,
18556  GL2C_PERF_SEL_CM_NOOP_REQ                = 0x000000e8,
18557  GL2C_PERF_SEL_CM_COMP_COLOR_EN_REQ       = 0x000000e9,
18558  GL2C_PERF_SEL_CM_COMP_COLOR_DIS_REQ      = 0x000000ea,
18559  GL2C_PERF_SEL_CM_COMP_STENCIL_REQ        = 0x000000eb,
18560  GL2C_PERF_SEL_CM_COMP_DEPTH16_REQ        = 0x000000ec,
18561  GL2C_PERF_SEL_CM_COMP_DEPTH32_REQ        = 0x000000ed,
18562  GL2C_PERF_SEL_CM_COMP_RB_SKIP_REQ        = 0x000000ee,
18563  GL2C_PERF_SEL_CM_COLOR_32B_WR_REQ        = 0x000000ef,
18564  GL2C_PERF_SEL_CM_COLOR_64B_WR_REQ        = 0x000000f0,
18565  GL2C_PERF_SEL_CM_FULL_WRITE_REQ          = 0x000000f1,
18566  GL2C_PERF_SEL_CM_RVF_FULL                = 0x000000f2,
18567  GL2C_PERF_SEL_CM_SDR_FULL                = 0x000000f3,
18568  GL2C_PERF_SEL_CM_MERGE_BUF_FULL          = 0x000000f4,
18569  GL2C_PERF_SEL_CM_DCC_STALL               = 0x000000f5,
18570  GL2C_PERF_SEL_CM_DCC_IN_XFC              = 0x000000f6,
18571  GL2C_PERF_SEL_CM_DCC_OUT_XFC             = 0x000000f7,
18572  GL2C_PERF_SEL_CM_DCC_OUT_1x1             = 0x000000f8,
18573  GL2C_PERF_SEL_CM_DCC_OUT_1x2             = 0x000000f9,
18574  GL2C_PERF_SEL_CM_DCC_OUT_2x1             = 0x000000fa,
18575  GL2C_PERF_SEL_CM_DCC_OUT_2x2             = 0x000000fb,
18576  GL2C_PERF_SEL_CM_DCC_OUT_UNCOMP          = 0x000000fc,
18577  GL2C_PERF_SEL_CM_DCC_OUT_CONST           = 0x000000fd,
18578  GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT16  = 0x000000fe,
18579  GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT17  = 0x000000ff,
18580  GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT18  = 0x00000100,
18581  GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT19  = 0x00000101,
18582  } GL2C_PERF_SEL;
18583  
18584  /*******************************************************
18585   * GRBM Enums
18586   *******************************************************/
18587  
18588  /*
18589   * GRBM_PERF_SEL enum
18590   */
18591  
18592  typedef enum GRBM_PERF_SEL {
18593  GRBM_PERF_SEL_COUNT                      = 0x00000000,
18594  GRBM_PERF_SEL_USER_DEFINED               = 0x00000001,
18595  GRBM_PERF_SEL_GUI_ACTIVE                 = 0x00000002,
18596  GRBM_PERF_SEL_CP_BUSY                    = 0x00000003,
18597  GRBM_PERF_SEL_CP_COHER_BUSY              = 0x00000004,
18598  GRBM_PERF_SEL_CP_DMA_BUSY                = 0x00000005,
18599  GRBM_PERF_SEL_CB_BUSY                    = 0x00000006,
18600  GRBM_PERF_SEL_DB_BUSY                    = 0x00000007,
18601  GRBM_PERF_SEL_PA_BUSY                    = 0x00000008,
18602  GRBM_PERF_SEL_SC_BUSY                    = 0x00000009,
18603  GRBM_PERF_SEL_SPI_BUSY                   = 0x0000000b,
18604  GRBM_PERF_SEL_SX_BUSY                    = 0x0000000c,
18605  GRBM_PERF_SEL_TA_BUSY                    = 0x0000000d,
18606  GRBM_PERF_SEL_CB_CLEAN                   = 0x0000000e,
18607  GRBM_PERF_SEL_DB_CLEAN                   = 0x0000000f,
18608  GRBM_PERF_SEL_GDS_BUSY                   = 0x00000019,
18609  GRBM_PERF_SEL_BCI_BUSY                   = 0x0000001a,
18610  GRBM_PERF_SEL_RLC_BUSY                   = 0x0000001b,
18611  GRBM_PERF_SEL_TCP_BUSY                   = 0x0000001c,
18612  GRBM_PERF_SEL_CPG_BUSY                   = 0x0000001d,
18613  GRBM_PERF_SEL_CPC_BUSY                   = 0x0000001e,
18614  GRBM_PERF_SEL_CPF_BUSY                   = 0x0000001f,
18615  GRBM_PERF_SEL_GE_BUSY                    = 0x00000020,
18616  GRBM_PERF_SEL_GE_NO_DMA_BUSY             = 0x00000021,
18617  GRBM_PERF_SEL_UTCL2_BUSY                 = 0x00000022,
18618  GRBM_PERF_SEL_EA_BUSY                    = 0x00000023,
18619  GRBM_PERF_SEL_RMI_BUSY                   = 0x00000024,
18620  GRBM_PERF_SEL_CPAXI_BUSY                 = 0x00000025,
18621  GRBM_PERF_SEL_UTCL1_BUSY                 = 0x00000027,
18622  GRBM_PERF_SEL_GL2CC_BUSY                 = 0x00000028,
18623  GRBM_PERF_SEL_SDMA_BUSY                  = 0x00000029,
18624  GRBM_PERF_SEL_CH_BUSY                    = 0x0000002a,
18625  GRBM_PERF_SEL_PH_BUSY                    = 0x0000002b,
18626  GRBM_PERF_SEL_PMM_BUSY                   = 0x0000002c,
18627  GRBM_PERF_SEL_GUS_BUSY                   = 0x0000002d,
18628  GRBM_PERF_SEL_GL1CC_BUSY                 = 0x0000002e,
18629  GRBM_PERF_SEL_ANY_ACTIVE_F_BUSY          = 0x0000002f,
18630  GRBM_PERF_SEL_GL1H_BUSY                  = 0x00000030,
18631  GRBM_PERF_SEL_PC_BUSY                    = 0x00000031,
18632  } GRBM_PERF_SEL;
18633  
18634  /*
18635   * GRBM_SE0_PERF_SEL enum
18636   */
18637  
18638  typedef enum GRBM_SE0_PERF_SEL {
18639  GRBM_SE0_PERF_SEL_COUNT                  = 0x00000000,
18640  GRBM_SE0_PERF_SEL_USER_DEFINED           = 0x00000001,
18641  GRBM_SE0_PERF_SEL_CB_BUSY                = 0x00000002,
18642  GRBM_SE0_PERF_SEL_DB_BUSY                = 0x00000003,
18643  GRBM_SE0_PERF_SEL_SC_BUSY                = 0x00000004,
18644  GRBM_SE0_PERF_SEL_SPI_BUSY               = 0x00000006,
18645  GRBM_SE0_PERF_SEL_SX_BUSY                = 0x00000007,
18646  GRBM_SE0_PERF_SEL_TA_BUSY                = 0x00000008,
18647  GRBM_SE0_PERF_SEL_CB_CLEAN               = 0x00000009,
18648  GRBM_SE0_PERF_SEL_DB_CLEAN               = 0x0000000a,
18649  GRBM_SE0_PERF_SEL_PA_BUSY                = 0x0000000c,
18650  GRBM_SE0_PERF_SEL_BCI_BUSY               = 0x0000000e,
18651  GRBM_SE0_PERF_SEL_RMI_BUSY               = 0x0000000f,
18652  GRBM_SE0_PERF_SEL_UTCL1_BUSY             = 0x00000010,
18653  GRBM_SE0_PERF_SEL_TCP_BUSY               = 0x00000011,
18654  GRBM_SE0_PERF_SEL_GL1CC_BUSY             = 0x00000012,
18655  GRBM_SE0_PERF_SEL_GL1H_BUSY              = 0x00000013,
18656  GRBM_SE0_PERF_SEL_PC_BUSY                = 0x00000014,
18657  } GRBM_SE0_PERF_SEL;
18658  
18659  /*
18660   * GRBM_SE1_PERF_SEL enum
18661   */
18662  
18663  typedef enum GRBM_SE1_PERF_SEL {
18664  GRBM_SE1_PERF_SEL_COUNT                  = 0x00000000,
18665  GRBM_SE1_PERF_SEL_USER_DEFINED           = 0x00000001,
18666  GRBM_SE1_PERF_SEL_CB_BUSY                = 0x00000002,
18667  GRBM_SE1_PERF_SEL_DB_BUSY                = 0x00000003,
18668  GRBM_SE1_PERF_SEL_SC_BUSY                = 0x00000004,
18669  GRBM_SE1_PERF_SEL_SPI_BUSY               = 0x00000006,
18670  GRBM_SE1_PERF_SEL_SX_BUSY                = 0x00000007,
18671  GRBM_SE1_PERF_SEL_TA_BUSY                = 0x00000008,
18672  GRBM_SE1_PERF_SEL_CB_CLEAN               = 0x00000009,
18673  GRBM_SE1_PERF_SEL_DB_CLEAN               = 0x0000000a,
18674  GRBM_SE1_PERF_SEL_PA_BUSY                = 0x0000000c,
18675  GRBM_SE1_PERF_SEL_BCI_BUSY               = 0x0000000e,
18676  GRBM_SE1_PERF_SEL_RMI_BUSY               = 0x0000000f,
18677  GRBM_SE1_PERF_SEL_UTCL1_BUSY             = 0x00000010,
18678  GRBM_SE1_PERF_SEL_TCP_BUSY               = 0x00000011,
18679  GRBM_SE1_PERF_SEL_GL1CC_BUSY             = 0x00000012,
18680  GRBM_SE1_PERF_SEL_GL1H_BUSY              = 0x00000013,
18681  GRBM_SE1_PERF_SEL_PC_BUSY                = 0x00000014,
18682  } GRBM_SE1_PERF_SEL;
18683  
18684  /*
18685   * GRBM_SE2_PERF_SEL enum
18686   */
18687  
18688  typedef enum GRBM_SE2_PERF_SEL {
18689  GRBM_SE2_PERF_SEL_COUNT                  = 0x00000000,
18690  GRBM_SE2_PERF_SEL_USER_DEFINED           = 0x00000001,
18691  GRBM_SE2_PERF_SEL_CB_BUSY                = 0x00000002,
18692  GRBM_SE2_PERF_SEL_DB_BUSY                = 0x00000003,
18693  GRBM_SE2_PERF_SEL_SC_BUSY                = 0x00000004,
18694  GRBM_SE2_PERF_SEL_SPI_BUSY               = 0x00000006,
18695  GRBM_SE2_PERF_SEL_SX_BUSY                = 0x00000007,
18696  GRBM_SE2_PERF_SEL_TA_BUSY                = 0x00000008,
18697  GRBM_SE2_PERF_SEL_CB_CLEAN               = 0x00000009,
18698  GRBM_SE2_PERF_SEL_DB_CLEAN               = 0x0000000a,
18699  GRBM_SE2_PERF_SEL_PA_BUSY                = 0x0000000c,
18700  GRBM_SE2_PERF_SEL_BCI_BUSY               = 0x0000000e,
18701  GRBM_SE2_PERF_SEL_RMI_BUSY               = 0x0000000f,
18702  GRBM_SE2_PERF_SEL_UTCL1_BUSY             = 0x00000010,
18703  GRBM_SE2_PERF_SEL_TCP_BUSY               = 0x00000011,
18704  GRBM_SE2_PERF_SEL_GL1CC_BUSY             = 0x00000012,
18705  GRBM_SE2_PERF_SEL_GL1H_BUSY              = 0x00000013,
18706  GRBM_SE2_PERF_SEL_PC_BUSY                = 0x00000014,
18707  } GRBM_SE2_PERF_SEL;
18708  
18709  /*
18710   * GRBM_SE3_PERF_SEL enum
18711   */
18712  
18713  typedef enum GRBM_SE3_PERF_SEL {
18714  GRBM_SE3_PERF_SEL_COUNT                  = 0x00000000,
18715  GRBM_SE3_PERF_SEL_USER_DEFINED           = 0x00000001,
18716  GRBM_SE3_PERF_SEL_CB_BUSY                = 0x00000002,
18717  GRBM_SE3_PERF_SEL_DB_BUSY                = 0x00000003,
18718  GRBM_SE3_PERF_SEL_SC_BUSY                = 0x00000004,
18719  GRBM_SE3_PERF_SEL_SPI_BUSY               = 0x00000006,
18720  GRBM_SE3_PERF_SEL_SX_BUSY                = 0x00000007,
18721  GRBM_SE3_PERF_SEL_TA_BUSY                = 0x00000008,
18722  GRBM_SE3_PERF_SEL_CB_CLEAN               = 0x00000009,
18723  GRBM_SE3_PERF_SEL_DB_CLEAN               = 0x0000000a,
18724  GRBM_SE3_PERF_SEL_PA_BUSY                = 0x0000000c,
18725  GRBM_SE3_PERF_SEL_BCI_BUSY               = 0x0000000e,
18726  GRBM_SE3_PERF_SEL_RMI_BUSY               = 0x0000000f,
18727  GRBM_SE3_PERF_SEL_UTCL1_BUSY             = 0x00000010,
18728  GRBM_SE3_PERF_SEL_TCP_BUSY               = 0x00000011,
18729  GRBM_SE3_PERF_SEL_GL1CC_BUSY             = 0x00000012,
18730  GRBM_SE3_PERF_SEL_GL1H_BUSY              = 0x00000013,
18731  GRBM_SE3_PERF_SEL_PC_BUSY                = 0x00000014,
18732  } GRBM_SE3_PERF_SEL;
18733  
18734  /*
18735   * GRBM_SE4_PERF_SEL enum
18736   */
18737  
18738  typedef enum GRBM_SE4_PERF_SEL {
18739  GRBM_SE4_PERF_SEL_COUNT                  = 0x00000000,
18740  GRBM_SE4_PERF_SEL_USER_DEFINED           = 0x00000001,
18741  GRBM_SE4_PERF_SEL_CB_BUSY                = 0x00000002,
18742  GRBM_SE4_PERF_SEL_DB_BUSY                = 0x00000003,
18743  GRBM_SE4_PERF_SEL_SC_BUSY                = 0x00000004,
18744  GRBM_SE4_PERF_SEL_SPI_BUSY               = 0x00000006,
18745  GRBM_SE4_PERF_SEL_SX_BUSY                = 0x00000007,
18746  GRBM_SE4_PERF_SEL_TA_BUSY                = 0x00000008,
18747  GRBM_SE4_PERF_SEL_CB_CLEAN               = 0x00000009,
18748  GRBM_SE4_PERF_SEL_DB_CLEAN               = 0x0000000a,
18749  GRBM_SE4_PERF_SEL_PA_BUSY                = 0x0000000c,
18750  GRBM_SE4_PERF_SEL_BCI_BUSY               = 0x0000000e,
18751  GRBM_SE4_PERF_SEL_RMI_BUSY               = 0x0000000f,
18752  GRBM_SE4_PERF_SEL_UTCL1_BUSY             = 0x00000010,
18753  GRBM_SE4_PERF_SEL_TCP_BUSY               = 0x00000011,
18754  GRBM_SE4_PERF_SEL_GL1CC_BUSY             = 0x00000012,
18755  GRBM_SE4_PERF_SEL_GL1H_BUSY              = 0x00000013,
18756  GRBM_SE4_PERF_SEL_PC_BUSY                = 0x00000014,
18757  } GRBM_SE4_PERF_SEL;
18758  
18759  /*
18760   * GRBM_SE5_PERF_SEL enum
18761   */
18762  
18763  typedef enum GRBM_SE5_PERF_SEL {
18764  GRBM_SE5_PERF_SEL_COUNT                  = 0x00000000,
18765  GRBM_SE5_PERF_SEL_USER_DEFINED           = 0x00000001,
18766  GRBM_SE5_PERF_SEL_CB_BUSY                = 0x00000002,
18767  GRBM_SE5_PERF_SEL_DB_BUSY                = 0x00000003,
18768  GRBM_SE5_PERF_SEL_SC_BUSY                = 0x00000004,
18769  GRBM_SE5_PERF_SEL_SPI_BUSY               = 0x00000006,
18770  GRBM_SE5_PERF_SEL_SX_BUSY                = 0x00000007,
18771  GRBM_SE5_PERF_SEL_TA_BUSY                = 0x00000008,
18772  GRBM_SE5_PERF_SEL_CB_CLEAN               = 0x00000009,
18773  GRBM_SE5_PERF_SEL_DB_CLEAN               = 0x0000000a,
18774  GRBM_SE5_PERF_SEL_PA_BUSY                = 0x0000000c,
18775  GRBM_SE5_PERF_SEL_BCI_BUSY               = 0x0000000e,
18776  GRBM_SE5_PERF_SEL_RMI_BUSY               = 0x0000000f,
18777  GRBM_SE5_PERF_SEL_UTCL1_BUSY             = 0x00000010,
18778  GRBM_SE5_PERF_SEL_TCP_BUSY               = 0x00000011,
18779  GRBM_SE5_PERF_SEL_GL1CC_BUSY             = 0x00000012,
18780  GRBM_SE5_PERF_SEL_GL1H_BUSY              = 0x00000013,
18781  GRBM_SE5_PERF_SEL_PC_BUSY                = 0x00000014,
18782  } GRBM_SE5_PERF_SEL;
18783  
18784  /*
18785   * GRBM_SE6_PERF_SEL enum
18786   */
18787  
18788  typedef enum GRBM_SE6_PERF_SEL {
18789  GRBM_SE6_PERF_SEL_COUNT                  = 0x00000000,
18790  GRBM_SE6_PERF_SEL_USER_DEFINED           = 0x00000001,
18791  GRBM_SE6_PERF_SEL_CB_BUSY                = 0x00000002,
18792  GRBM_SE6_PERF_SEL_DB_BUSY                = 0x00000003,
18793  GRBM_SE6_PERF_SEL_SC_BUSY                = 0x00000004,
18794  GRBM_SE6_PERF_SEL_SPI_BUSY               = 0x00000006,
18795  GRBM_SE6_PERF_SEL_SX_BUSY                = 0x00000007,
18796  GRBM_SE6_PERF_SEL_TA_BUSY                = 0x00000008,
18797  GRBM_SE6_PERF_SEL_CB_CLEAN               = 0x00000009,
18798  GRBM_SE6_PERF_SEL_DB_CLEAN               = 0x0000000a,
18799  GRBM_SE6_PERF_SEL_PA_BUSY                = 0x0000000c,
18800  GRBM_SE6_PERF_SEL_BCI_BUSY               = 0x0000000e,
18801  GRBM_SE6_PERF_SEL_RMI_BUSY               = 0x0000000f,
18802  GRBM_SE6_PERF_SEL_UTCL1_BUSY             = 0x00000010,
18803  GRBM_SE6_PERF_SEL_TCP_BUSY               = 0x00000011,
18804  GRBM_SE6_PERF_SEL_GL1CC_BUSY             = 0x00000012,
18805  GRBM_SE6_PERF_SEL_GL1H_BUSY              = 0x00000013,
18806  GRBM_SE6_PERF_SEL_PC_BUSY                = 0x00000014,
18807  } GRBM_SE6_PERF_SEL;
18808  
18809  /*
18810   * GRBM_SE7_PERF_SEL enum
18811   */
18812  
18813  typedef enum GRBM_SE7_PERF_SEL {
18814  GRBM_SE7_PERF_SEL_COUNT                  = 0x00000000,
18815  GRBM_SE7_PERF_SEL_USER_DEFINED           = 0x00000001,
18816  GRBM_SE7_PERF_SEL_CB_BUSY                = 0x00000002,
18817  GRBM_SE7_PERF_SEL_DB_BUSY                = 0x00000003,
18818  GRBM_SE7_PERF_SEL_SC_BUSY                = 0x00000004,
18819  GRBM_SE7_PERF_SEL_SPI_BUSY               = 0x00000006,
18820  GRBM_SE7_PERF_SEL_SX_BUSY                = 0x00000007,
18821  GRBM_SE7_PERF_SEL_TA_BUSY                = 0x00000008,
18822  GRBM_SE7_PERF_SEL_CB_CLEAN               = 0x00000009,
18823  GRBM_SE7_PERF_SEL_DB_CLEAN               = 0x0000000a,
18824  GRBM_SE7_PERF_SEL_PA_BUSY                = 0x0000000c,
18825  GRBM_SE7_PERF_SEL_BCI_BUSY               = 0x0000000e,
18826  GRBM_SE7_PERF_SEL_RMI_BUSY               = 0x0000000f,
18827  GRBM_SE7_PERF_SEL_UTCL1_BUSY             = 0x00000010,
18828  GRBM_SE7_PERF_SEL_TCP_BUSY               = 0x00000011,
18829  GRBM_SE7_PERF_SEL_GL1CC_BUSY             = 0x00000012,
18830  GRBM_SE7_PERF_SEL_GL1H_BUSY              = 0x00000013,
18831  GRBM_SE7_PERF_SEL_PC_BUSY                = 0x00000014,
18832  } GRBM_SE7_PERF_SEL;
18833  
18834  /*
18835   * PIPE_COMPAT_LEVEL enum
18836   */
18837  
18838  typedef enum PIPE_COMPAT_LEVEL {
18839  GEN_ZERO                                 = 0x00000000,
18840  GEN_ONE                                  = 0x00000001,
18841  GEN_TWO                                  = 0x00000002,
18842  GEN_RESERVED                             = 0x00000003,
18843  } PIPE_COMPAT_LEVEL;
18844  
18845  /*******************************************************
18846   * CP Enums
18847   *******************************************************/
18848  
18849  /*
18850   * CPC_LATENCY_STATS_SEL enum
18851   */
18852  
18853  typedef enum CPC_LATENCY_STATS_SEL {
18854  CPC_LATENCY_STATS_SEL_XACK_MAX           = 0x00000000,
18855  CPC_LATENCY_STATS_SEL_XACK_MIN           = 0x00000001,
18856  CPC_LATENCY_STATS_SEL_XACK_LAST          = 0x00000002,
18857  CPC_LATENCY_STATS_SEL_XNACK_MAX          = 0x00000003,
18858  CPC_LATENCY_STATS_SEL_XNACK_MIN          = 0x00000004,
18859  CPC_LATENCY_STATS_SEL_XNACK_LAST         = 0x00000005,
18860  CPC_LATENCY_STATS_SEL_INVAL_MAX          = 0x00000006,
18861  CPC_LATENCY_STATS_SEL_INVAL_MIN          = 0x00000007,
18862  CPC_LATENCY_STATS_SEL_INVAL_LAST         = 0x00000008,
18863  } CPC_LATENCY_STATS_SEL;
18864  
18865  /*
18866   * CPC_PERFCOUNT_SEL enum
18867   */
18868  
18869  typedef enum CPC_PERFCOUNT_SEL {
18870  CPC_PERF_SEL_ALWAYS_COUNT                = 0x00000000,
18871  CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE     = 0x00000001,
18872  CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION   = 0x00000002,
18873  CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE     = 0x00000005,
18874  CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 0x00000006,
18875  CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 0x00000007,
18876  CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 0x00000008,
18877  CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_READ  = 0x00000009,
18878  CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_WRITE = 0x0000000a,
18879  CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ  = 0x0000000b,
18880  CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 0x0000000c,
18881  CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE  = 0x0000000d,
18882  CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 0x0000000e,
18883  CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 0x0000000f,
18884  CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 0x00000010,
18885  CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_READ  = 0x00000011,
18886  CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_WRITE = 0x00000012,
18887  CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ  = 0x00000013,
18888  CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 0x00000014,
18889  CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE  = 0x00000015,
18890  CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE  = 0x00000016,
18891  CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS  = 0x00000017,
18892  CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION  = 0x00000018,
18893  CPC_PERF_SEL_CPC_STAT_BUSY               = 0x00000019,
18894  CPC_PERF_SEL_CPC_STAT_IDLE               = 0x0000001a,
18895  CPC_PERF_SEL_CPC_STAT_STALL              = 0x0000001b,
18896  CPC_PERF_SEL_CPC_TCIU_BUSY               = 0x0000001c,
18897  CPC_PERF_SEL_CPC_TCIU_IDLE               = 0x0000001d,
18898  CPC_PERF_SEL_CPC_UTCL2IU_BUSY            = 0x0000001e,
18899  CPC_PERF_SEL_CPC_UTCL2IU_IDLE            = 0x0000001f,
18900  CPC_PERF_SEL_CPC_UTCL2IU_STALL           = 0x00000020,
18901  CPC_PERF_SEL_ME1_DC0_SPI_BUSY            = 0x00000021,
18902  CPC_PERF_SEL_ME2_DC1_SPI_BUSY            = 0x00000022,
18903  CPC_PERF_SEL_CPC_GCRIU_BUSY              = 0x00000023,
18904  CPC_PERF_SEL_CPC_GCRIU_IDLE              = 0x00000024,
18905  CPC_PERF_SEL_CPC_GCRIU_STALL             = 0x00000025,
18906  CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE    = 0x00000026,
18907  CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ = 0x00000027,
18908  CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ = 0x00000028,
18909  CPC_PERF_SEL_CPC_UTCL2IU_XACK            = 0x00000029,
18910  CPC_PERF_SEL_CPC_UTCL2IU_XNACK           = 0x0000002a,
18911  CPC_PERF_SEL_MEC_INSTR_CACHE_HIT         = 0x0000002b,
18912  CPC_PERF_SEL_MEC_INSTR_CACHE_MISS        = 0x0000002c,
18913  CPC_PERF_SEL_MES_THREAD0                 = 0x0000002d,
18914  CPC_PERF_SEL_MES_THREAD1                 = 0x0000002e,
18915  } CPC_PERFCOUNT_SEL;
18916  
18917  /*
18918   * CPF_LATENCY_STATS_SEL enum
18919   */
18920  
18921  typedef enum CPF_LATENCY_STATS_SEL {
18922  CPF_LATENCY_STATS_SEL_XACK_MAX           = 0x00000000,
18923  CPF_LATENCY_STATS_SEL_XACK_MIN           = 0x00000001,
18924  CPF_LATENCY_STATS_SEL_XACK_LAST          = 0x00000002,
18925  CPF_LATENCY_STATS_SEL_XNACK_MAX          = 0x00000003,
18926  CPF_LATENCY_STATS_SEL_XNACK_MIN          = 0x00000004,
18927  CPF_LATENCY_STATS_SEL_XNACK_LAST         = 0x00000005,
18928  CPF_LATENCY_STATS_SEL_READ_MAX           = 0x00000006,
18929  CPF_LATENCY_STATS_SEL_READ_MIN           = 0x00000007,
18930  CPF_LATENCY_STATS_SEL_READ_LAST          = 0x00000008,
18931  CPF_LATENCY_STATS_SEL_INVAL_MAX          = 0x00000009,
18932  CPF_LATENCY_STATS_SEL_INVAL_MIN          = 0x0000000a,
18933  CPF_LATENCY_STATS_SEL_INVAL_LAST         = 0x0000000b,
18934  } CPF_LATENCY_STATS_SEL;
18935  
18936  /*
18937   * CPF_PERFCOUNTWINDOW_SEL enum
18938   */
18939  
18940  typedef enum CPF_PERFCOUNTWINDOW_SEL {
18941  CPF_PERFWINDOW_SEL_CSF                   = 0x00000000,
18942  CPF_PERFWINDOW_SEL_HQD1                  = 0x00000001,
18943  CPF_PERFWINDOW_SEL_HQD2                  = 0x00000002,
18944  CPF_PERFWINDOW_SEL_RDMA                  = 0x00000003,
18945  CPF_PERFWINDOW_SEL_RWPP                  = 0x00000004,
18946  } CPF_PERFCOUNTWINDOW_SEL;
18947  
18948  /*
18949   * CPF_PERFCOUNT_SEL enum
18950   */
18951  
18952  typedef enum CPF_PERFCOUNT_SEL {
18953  CPF_PERF_SEL_ALWAYS_COUNT                = 0x00000000,
18954  CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 0x00000002,
18955  CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 0x00000003,
18956  CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING  = 0x00000004,
18957  CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1   = 0x00000005,
18958  CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2   = 0x00000006,
18959  CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_STATE = 0x00000007,
18960  CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR      = 0x0000000a,
18961  CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS    = 0x0000000b,
18962  CPF_PERF_SEL_GRBM_DWORDS_SENT            = 0x0000000c,
18963  CPF_PERF_SEL_DYNAMIC_CLOCK_VALID         = 0x0000000d,
18964  CPF_PERF_SEL_REGISTER_CLOCK_VALID        = 0x0000000e,
18965  CPF_PERF_SEL_GUS_WRITE_REQUEST_SENT      = 0x0000000f,
18966  CPF_PERF_SEL_GUS_READ_REQUEST_SENT       = 0x00000010,
18967  CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE  = 0x00000011,
18968  CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS  = 0x00000012,
18969  CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION = 0x00000013,
18970  CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION = 0x00000014,
18971  CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE     = 0x00000015,
18972  CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT     = 0x00000016,
18973  CPF_PERF_SEL_TCIU_READ_REQUEST_SENT      = 0x00000017,
18974  CPF_PERF_SEL_CPF_STAT_BUSY               = 0x00000018,
18975  CPF_PERF_SEL_CPF_STAT_IDLE               = 0x00000019,
18976  CPF_PERF_SEL_CPF_STAT_STALL              = 0x0000001a,
18977  CPF_PERF_SEL_CPF_TCIU_BUSY               = 0x0000001b,
18978  CPF_PERF_SEL_CPF_TCIU_IDLE               = 0x0000001c,
18979  CPF_PERF_SEL_CPF_TCIU_STALL              = 0x0000001d,
18980  CPF_PERF_SEL_CPF_UTCL2IU_BUSY            = 0x0000001e,
18981  CPF_PERF_SEL_CPF_UTCL2IU_IDLE            = 0x0000001f,
18982  CPF_PERF_SEL_CPF_UTCL2IU_STALL           = 0x00000020,
18983  CPF_PERF_SEL_CPF_GCRIU_BUSY              = 0x00000021,
18984  CPF_PERF_SEL_CPF_GCRIU_IDLE              = 0x00000022,
18985  CPF_PERF_SEL_CPF_GCRIU_STALL             = 0x00000023,
18986  CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE    = 0x00000024,
18987  CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB    = 0x00000025,
18988  CPF_PERF_SEL_CPF_UTCL2IU_XACK            = 0x00000026,
18989  CPF_PERF_SEL_CPF_UTCL2IU_XNACK           = 0x00000027,
18990  CPF_PERF_SEL_CP_SDMA_MNGR_DMA_REQ        = 0x00000028,
18991  CPF_PERF_SEL_CP_SDMA_MNGR_DMA_DONE       = 0x00000029,
18992  CPF_PERF_SEL_CP_SDMA_MNGR_LATENCY        = 0x0000002a,
18993  CPF_PERF_SEL_CP_SDMA_MNGR_SDMABUSY       = 0x0000002b,
18994  } CPF_PERFCOUNT_SEL;
18995  
18996  /*
18997   * CPF_SCRATCH_REG_ATOMIC_OP enum
18998   */
18999  
19000  typedef enum CPF_SCRATCH_REG_ATOMIC_OP {
19001  CPF_SCRATCH_REG_ATOMIC_ADD               = 0x00000000,
19002  CPF_SCRATCH_REG_ATOMIC_SUB               = 0x00000001,
19003  CPF_SCRATCH_REG_ATOMIC_OR                = 0x00000002,
19004  CPF_SCRATCH_REG_ATOMIC_AND               = 0x00000003,
19005  CPF_SCRATCH_REG_ATOMIC_NOT               = 0x00000004,
19006  CPF_SCRATCH_REG_ATOMIC_MIN               = 0x00000005,
19007  CPF_SCRATCH_REG_ATOMIC_MAX               = 0x00000006,
19008  CPF_SCRATCH_REG_ATOMIC_CMPSWAP           = 0x00000007,
19009  } CPF_SCRATCH_REG_ATOMIC_OP;
19010  
19011  /*
19012   * CPG_LATENCY_STATS_SEL enum
19013   */
19014  
19015  typedef enum CPG_LATENCY_STATS_SEL {
19016  CPG_LATENCY_STATS_SEL_XACK_MAX           = 0x00000000,
19017  CPG_LATENCY_STATS_SEL_XACK_MIN           = 0x00000001,
19018  CPG_LATENCY_STATS_SEL_XACK_LAST          = 0x00000002,
19019  CPG_LATENCY_STATS_SEL_XNACK_MAX          = 0x00000003,
19020  CPG_LATENCY_STATS_SEL_XNACK_MIN          = 0x00000004,
19021  CPG_LATENCY_STATS_SEL_XNACK_LAST         = 0x00000005,
19022  CPG_LATENCY_STATS_SEL_WRITE_MAX          = 0x00000006,
19023  CPG_LATENCY_STATS_SEL_WRITE_MIN          = 0x00000007,
19024  CPG_LATENCY_STATS_SEL_WRITE_LAST         = 0x00000008,
19025  CPG_LATENCY_STATS_SEL_READ_MAX           = 0x00000009,
19026  CPG_LATENCY_STATS_SEL_READ_MIN           = 0x0000000a,
19027  CPG_LATENCY_STATS_SEL_READ_LAST          = 0x0000000b,
19028  CPG_LATENCY_STATS_SEL_ATOMIC_MAX         = 0x0000000c,
19029  CPG_LATENCY_STATS_SEL_ATOMIC_MIN         = 0x0000000d,
19030  CPG_LATENCY_STATS_SEL_ATOMIC_LAST        = 0x0000000e,
19031  CPG_LATENCY_STATS_SEL_INVAL_MAX          = 0x0000000f,
19032  CPG_LATENCY_STATS_SEL_INVAL_MIN          = 0x00000010,
19033  CPG_LATENCY_STATS_SEL_INVAL_LAST         = 0x00000011,
19034  } CPG_LATENCY_STATS_SEL;
19035  
19036  /*
19037   * CPG_PERFCOUNTWINDOW_SEL enum
19038   */
19039  
19040  typedef enum CPG_PERFCOUNTWINDOW_SEL {
19041  CPG_PERFWINDOW_SEL_PFP                   = 0x00000000,
19042  CPG_PERFWINDOW_SEL_ME                    = 0x00000001,
19043  CPG_PERFWINDOW_SEL_CE                    = 0x00000002,
19044  CPG_PERFWINDOW_SEL_MES                   = 0x00000003,
19045  CPG_PERFWINDOW_SEL_MEC1                  = 0x00000004,
19046  CPG_PERFWINDOW_SEL_MEC2                  = 0x00000005,
19047  CPG_PERFWINDOW_SEL_DFY                   = 0x00000006,
19048  CPG_PERFWINDOW_SEL_DMA                   = 0x00000007,
19049  CPG_PERFWINDOW_SEL_SHADOW                = 0x00000008,
19050  CPG_PERFWINDOW_SEL_RB                    = 0x00000009,
19051  CPG_PERFWINDOW_SEL_CEDMA                 = 0x0000000a,
19052  CPG_PERFWINDOW_SEL_PRT_HDR_RPTR          = 0x0000000b,
19053  CPG_PERFWINDOW_SEL_PRT_SMP_RPTR          = 0x0000000c,
19054  CPG_PERFWINDOW_SEL_PQ1                   = 0x0000000d,
19055  CPG_PERFWINDOW_SEL_PQ2                   = 0x0000000e,
19056  CPG_PERFWINDOW_SEL_PQ3                   = 0x0000000f,
19057  CPG_PERFWINDOW_SEL_MEMWR                 = 0x00000010,
19058  CPG_PERFWINDOW_SEL_MEMRD                 = 0x00000011,
19059  CPG_PERFWINDOW_SEL_VGT0                  = 0x00000012,
19060  CPG_PERFWINDOW_SEL_VGT1                  = 0x00000013,
19061  CPG_PERFWINDOW_SEL_APPEND                = 0x00000014,
19062  CPG_PERFWINDOW_SEL_QURD                  = 0x00000015,
19063  CPG_PERFWINDOW_SEL_DDID                  = 0x00000016,
19064  CPG_PERFWINDOW_SEL_SR                    = 0x00000017,
19065  CPG_PERFWINDOW_SEL_QU_EOP                = 0x00000018,
19066  CPG_PERFWINDOW_SEL_QU_STRM               = 0x00000019,
19067  CPG_PERFWINDOW_SEL_QU_PIPE               = 0x0000001a,
19068  CPG_PERFWINDOW_SEL_RESERVED1             = 0x0000001b,
19069  CPG_PERFWINDOW_SEL_CPC_IC                = 0x0000001c,
19070  CPG_PERFWINDOW_SEL_RESERVED2             = 0x0000001d,
19071  CPG_PERFWINDOW_SEL_CPG_IC                = 0x0000001e,
19072  } CPG_PERFCOUNTWINDOW_SEL;
19073  
19074  /*
19075   * CPG_PERFCOUNT_SEL enum
19076   */
19077  
19078  typedef enum CPG_PERFCOUNT_SEL {
19079  CPG_PERF_SEL_ALWAYS_COUNT                = 0x00000000,
19080  CPG_PERF_SEL_RBIU_FIFO_FULL              = 0x00000001,
19081  CPG_PERF_SEL_CP_GRBM_DWORDS_SENT         = 0x00000004,
19082  CPG_PERF_SEL_ME_PARSER_BUSY              = 0x00000005,
19083  CPG_PERF_SEL_COUNT_TYPE0_PACKETS         = 0x00000006,
19084  CPG_PERF_SEL_COUNT_TYPE3_PACKETS         = 0x00000007,
19085  CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS      = 0x00000009,
19086  CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS  = 0x0000000a,
19087  CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS  = 0x0000000b,
19088  CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ     = 0x0000000c,
19089  CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ    = 0x0000000d,
19090  CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX  = 0x0000000e,
19091  CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 0x0000000f,
19092  CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 0x00000010,
19093  CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 0x00000011,
19094  CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY    = 0x00000012,
19095  CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY    = 0x00000013,
19096  CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY   = 0x00000014,
19097  CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 0x00000015,
19098  CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 0x00000016,
19099  CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 0x00000017,
19100  CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 0x00000018,
19101  CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU  = 0x00000019,
19102  CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 0x0000001a,
19103  CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 0x0000001b,
19104  CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER       = 0x0000001c,
19105  CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER     = 0x0000001d,
19106  CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 0x0000001f,
19107  CPG_PERF_SEL_DYNAMIC_CLK_VALID           = 0x00000020,
19108  CPG_PERF_SEL_REGISTER_CLK_VALID          = 0x00000021,
19109  CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT      = 0x00000022,
19110  CPG_PERF_SEL_GUS_READ_REQUEST_SENT       = 0x00000023,
19111  CPG_PERF_SEL_CE_STALL_RAM_DUMP           = 0x00000024,
19112  CPG_PERF_SEL_CE_STALL_RAM_WRITE          = 0x00000025,
19113  CPG_PERF_SEL_CE_STALL_ON_INC_FIFO        = 0x00000026,
19114  CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO     = 0x00000027,
19115  CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ   = 0x00000029,
19116  CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG  = 0x0000002a,
19117  CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER      = 0x0000002b,
19118  CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE     = 0x0000002c,
19119  CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS     = 0x0000002d,
19120  CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE  = 0x0000002e,
19121  CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS  = 0x0000002f,
19122  CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION  = 0x00000030,
19123  CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT     = 0x00000031,
19124  CPG_PERF_SEL_TCIU_READ_REQUEST_SENT      = 0x00000032,
19125  CPG_PERF_SEL_CPG_STAT_BUSY               = 0x00000033,
19126  CPG_PERF_SEL_CPG_STAT_IDLE               = 0x00000034,
19127  CPG_PERF_SEL_CPG_STAT_STALL              = 0x00000035,
19128  CPG_PERF_SEL_CPG_TCIU_BUSY               = 0x00000036,
19129  CPG_PERF_SEL_CPG_TCIU_IDLE               = 0x00000037,
19130  CPG_PERF_SEL_CPG_TCIU_STALL              = 0x00000038,
19131  CPG_PERF_SEL_CPG_UTCL2IU_BUSY            = 0x00000039,
19132  CPG_PERF_SEL_CPG_UTCL2IU_IDLE            = 0x0000003a,
19133  CPG_PERF_SEL_CPG_UTCL2IU_STALL           = 0x0000003b,
19134  CPG_PERF_SEL_CPG_GCRIU_BUSY              = 0x0000003c,
19135  CPG_PERF_SEL_CPG_GCRIU_IDLE              = 0x0000003d,
19136  CPG_PERF_SEL_CPG_GCRIU_STALL             = 0x0000003e,
19137  CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE    = 0x0000003f,
19138  CPG_PERF_SEL_ALL_GFX_PIPES_BUSY          = 0x00000040,
19139  CPG_PERF_SEL_CPG_UTCL2IU_XACK            = 0x00000041,
19140  CPG_PERF_SEL_CPG_UTCL2IU_XNACK           = 0x00000042,
19141  CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY = 0x00000043,
19142  CPG_PERF_SEL_PFP_INSTR_CACHE_HIT         = 0x00000044,
19143  CPG_PERF_SEL_PFP_INSTR_CACHE_MISS        = 0x00000045,
19144  CPG_PERF_SEL_CE_INSTR_CACHE_HIT          = 0x00000046,
19145  CPG_PERF_SEL_CE_INSTR_CACHE_MISS         = 0x00000047,
19146  CPG_PERF_SEL_ME_INSTR_CACHE_HIT          = 0x00000048,
19147  CPG_PERF_SEL_ME_INSTR_CACHE_MISS         = 0x00000049,
19148  CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1   = 0x0000004a,
19149  CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1  = 0x0000004b,
19150  CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2   = 0x0000004c,
19151  CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2  = 0x0000004d,
19152  CPG_PERF_SEL_DMA_BUSY                    = 0x0000004e,
19153  CPG_PERF_SEL_DMA_STARVED                 = 0x0000004f,
19154  CPG_PERF_SEL_DMA_STALLED                 = 0x00000050,
19155  CPG_PERF_SEL_DMA_FETCHER_STALLED_ON_ROQ_FULL = 0x00000051,
19156  CPG_PERF_SEL_PFP_PWS_STALLED0            = 0x00000052,
19157  CPG_PERF_SEL_ME_PWS_STALLED0             = 0x00000053,
19158  CPG_PERF_SEL_PFP_PWS_STALLED1            = 0x00000054,
19159  CPG_PERF_SEL_ME_PWS_STALLED1             = 0x00000055,
19160  } CPG_PERFCOUNT_SEL;
19161  
19162  /*
19163   * CP_ALPHA_TAG_RAM_SEL enum
19164   */
19165  
19166  typedef enum CP_ALPHA_TAG_RAM_SEL {
19167  CPG_TAG_RAM                              = 0x00000000,
19168  CPC_TAG_RAM                              = 0x00000001,
19169  CPF_TAG_RAM                              = 0x00000002,
19170  RSV_TAG_RAM                              = 0x00000003,
19171  } CP_ALPHA_TAG_RAM_SEL;
19172  
19173  /*
19174   * CP_DDID_CNTL_MODE enum
19175   */
19176  
19177  typedef enum CP_DDID_CNTL_MODE {
19178  STALL                                    = 0x00000000,
19179  OVERRUN                                  = 0x00000001,
19180  } CP_DDID_CNTL_MODE;
19181  
19182  /*
19183   * CP_DDID_CNTL_SIZE enum
19184   */
19185  
19186  typedef enum CP_DDID_CNTL_SIZE {
19187  SIZE_8K                                  = 0x00000000,
19188  SIZE_16K                                 = 0x00000001,
19189  } CP_DDID_CNTL_SIZE;
19190  
19191  /*
19192   * CP_DDID_CNTL_VMID_SEL enum
19193   */
19194  
19195  typedef enum CP_DDID_CNTL_VMID_SEL {
19196  DDID_VMID_PIPE                           = 0x00000000,
19197  DDID_VMID_CNTL                           = 0x00000001,
19198  } CP_DDID_CNTL_VMID_SEL;
19199  
19200  /*
19201   * CP_ME_ID enum
19202   */
19203  
19204  typedef enum CP_ME_ID {
19205  ME_ID0                                   = 0x00000000,
19206  ME_ID1                                   = 0x00000001,
19207  ME_ID2                                   = 0x00000002,
19208  ME_ID3                                   = 0x00000003,
19209  } CP_ME_ID;
19210  
19211  /*
19212   * CP_PERFMON_ENABLE_MODE enum
19213   */
19214  
19215  typedef enum CP_PERFMON_ENABLE_MODE {
19216  CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT      = 0x00000000,
19217  CP_PERFMON_ENABLE_MODE_RESERVED_1        = 0x00000001,
19218  CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 0x00000002,
19219  CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 0x00000003,
19220  } CP_PERFMON_ENABLE_MODE;
19221  
19222  /*
19223   * CP_PERFMON_STATE enum
19224   */
19225  
19226  typedef enum CP_PERFMON_STATE {
19227  CP_PERFMON_STATE_DISABLE_AND_RESET       = 0x00000000,
19228  CP_PERFMON_STATE_START_COUNTING          = 0x00000001,
19229  CP_PERFMON_STATE_STOP_COUNTING           = 0x00000002,
19230  CP_PERFMON_STATE_RESERVED_3              = 0x00000003,
19231  CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004,
19232  CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM  = 0x00000005,
19233  } CP_PERFMON_STATE;
19234  
19235  /*
19236   * CP_PIPE_ID enum
19237   */
19238  
19239  typedef enum CP_PIPE_ID {
19240  PIPE_ID0                                 = 0x00000000,
19241  PIPE_ID1                                 = 0x00000001,
19242  PIPE_ID2                                 = 0x00000002,
19243  PIPE_ID3                                 = 0x00000003,
19244  } CP_PIPE_ID;
19245  
19246  /*
19247   * CP_RING_ID enum
19248   */
19249  
19250  typedef enum CP_RING_ID {
19251  RINGID0                                  = 0x00000000,
19252  RINGID1                                  = 0x00000001,
19253  RINGID2                                  = 0x00000002,
19254  RINGID3                                  = 0x00000003,
19255  } CP_RING_ID;
19256  
19257  /*
19258   * SPM_PERFMON_STATE enum
19259   */
19260  
19261  typedef enum SPM_PERFMON_STATE {
19262  STRM_PERFMON_STATE_DISABLE_AND_RESET     = 0x00000000,
19263  STRM_PERFMON_STATE_START_COUNTING        = 0x00000001,
19264  STRM_PERFMON_STATE_STOP_COUNTING         = 0x00000002,
19265  STRM_PERFMON_STATE_RESERVED_3            = 0x00000003,
19266  STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004,
19267  STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x00000005,
19268  } SPM_PERFMON_STATE;
19269  
19270  /*
19271   * SEM_RESPONSE value
19272   */
19273  
19274  #define SEM_ECC_ERROR                  0x00000000
19275  #define SEM_TRANS_ERROR                0x00000001
19276  #define SEM_RESP_FAILED                0x00000002
19277  #define SEM_RESP_PASSED                0x00000003
19278  
19279  /*
19280   * IQ_RETRY_TYPE value
19281   */
19282  
19283  #define IQ_QUEUE_SLEEP                 0x00000000
19284  #define IQ_OFFLOAD_RETRY               0x00000001
19285  #define IQ_SCH_WAVE_MSG                0x00000002
19286  #define IQ_SEM_REARM                   0x00000003
19287  #define IQ_DEQUEUE_RETRY               0x00000004
19288  
19289  /*
19290   * IQ_INTR_TYPE value
19291   */
19292  
19293  #define IQ_INTR_TYPE_PQ                0x00000000
19294  #define IQ_INTR_TYPE_IB                0x00000001
19295  #define IQ_INTR_TYPE_MQD               0x00000002
19296  
19297  /*
19298   * VMID_SIZE value
19299   */
19300  
19301  #define VMID_SZ                        0x00000004
19302  
19303  /*
19304   * SRCID_SECURE value
19305   */
19306  
19307  #define SRCID_RLC                      0x00000000
19308  #define SRCID_RLCV                     0x00000006
19309  #define SRCID_SECURE_CP                0x00000007
19310  #define SRCID_NONSECURE_CP             0x00000001
19311  #define SRCID_SECURE_CP_RCIU           0x00000007
19312  #define SRCID_NONSECURE_CP_RCIU        0x00000001
19313  
19314  /*
19315   * CONFIG_SPACE value
19316   */
19317  
19318  #define CONFIG_SPACE_START             0x00002000
19319  #define CONFIG_SPACE_END               0x00009fff
19320  
19321  /*
19322   * CONFIG_SPACE1 value
19323   */
19324  
19325  #define CONFIG_SPACE1_START            0x00002000
19326  #define CONFIG_SPACE1_END              0x00002bff
19327  
19328  /*
19329   * CONFIG_SPACE2 value
19330   */
19331  
19332  #define CONFIG_SPACE2_START            0x00003000
19333  #define CONFIG_SPACE2_END              0x00009fff
19334  
19335  /*
19336   * UCONFIG_SPACE value
19337   */
19338  
19339  #define UCONFIG_SPACE_START            0x0000c000
19340  #define UCONFIG_SPACE_END              0x0000ffff
19341  
19342  /*
19343   * PERSISTENT_SPACE value
19344   */
19345  
19346  #define PERSISTENT_SPACE_START         0x00002c00
19347  #define PERSISTENT_SPACE_END           0x00002fff
19348  
19349  /*
19350   * CONTEXT_SPACE value
19351   */
19352  
19353  #define CONTEXT_SPACE_START            0x0000a000
19354  #define CONTEXT_SPACE_END              0x0000a3ff
19355  
19356  /*******************************************************
19357   * SX Enums
19358   *******************************************************/
19359  
19360  /*
19361   * SX_BLEND_OPT enum
19362   */
19363  
19364  typedef enum SX_BLEND_OPT {
19365  BLEND_OPT_PRESERVE_NONE_IGNORE_ALL       = 0x00000000,
19366  BLEND_OPT_PRESERVE_ALL_IGNORE_NONE       = 0x00000001,
19367  BLEND_OPT_PRESERVE_C1_IGNORE_C0          = 0x00000002,
19368  BLEND_OPT_PRESERVE_C0_IGNORE_C1          = 0x00000003,
19369  BLEND_OPT_PRESERVE_A1_IGNORE_A0          = 0x00000004,
19370  BLEND_OPT_PRESERVE_A0_IGNORE_A1          = 0x00000005,
19371  BLEND_OPT_PRESERVE_NONE_IGNORE_A0        = 0x00000006,
19372  BLEND_OPT_PRESERVE_NONE_IGNORE_NONE      = 0x00000007,
19373  } SX_BLEND_OPT;
19374  
19375  /*
19376   * SX_DOWNCONVERT_FORMAT enum
19377   */
19378  
19379  typedef enum SX_DOWNCONVERT_FORMAT {
19380  SX_RT_EXPORT_NO_CONVERSION               = 0x00000000,
19381  SX_RT_EXPORT_32_R                        = 0x00000001,
19382  SX_RT_EXPORT_32_A                        = 0x00000002,
19383  SX_RT_EXPORT_10_11_11                    = 0x00000003,
19384  SX_RT_EXPORT_2_10_10_10                  = 0x00000004,
19385  SX_RT_EXPORT_8_8_8_8                     = 0x00000005,
19386  SX_RT_EXPORT_5_6_5                       = 0x00000006,
19387  SX_RT_EXPORT_1_5_5_5                     = 0x00000007,
19388  SX_RT_EXPORT_4_4_4_4                     = 0x00000008,
19389  SX_RT_EXPORT_16_16_GR                    = 0x00000009,
19390  SX_RT_EXPORT_16_16_AR                    = 0x0000000a,
19391  SX_RT_EXPORT_9_9_9_E5                    = 0x0000000b,
19392  SX_RT_EXPORT_2_10_10_10_7E3              = 0x0000000c,
19393  SX_RT_EXPORT_2_10_10_10_6E4              = 0x0000000d,
19394  } SX_DOWNCONVERT_FORMAT;
19395  
19396  /*
19397   * SX_OPT_COMB_FCN enum
19398   */
19399  
19400  typedef enum SX_OPT_COMB_FCN {
19401  OPT_COMB_NONE                            = 0x00000000,
19402  OPT_COMB_ADD                             = 0x00000001,
19403  OPT_COMB_SUBTRACT                        = 0x00000002,
19404  OPT_COMB_MIN                             = 0x00000003,
19405  OPT_COMB_MAX                             = 0x00000004,
19406  OPT_COMB_REVSUBTRACT                     = 0x00000005,
19407  OPT_COMB_BLEND_DISABLED                  = 0x00000006,
19408  OPT_COMB_SAFE_ADD                        = 0x00000007,
19409  } SX_OPT_COMB_FCN;
19410  
19411  /*
19412   * SX_PERFCOUNTER_VALS enum
19413   */
19414  
19415  typedef enum SX_PERFCOUNTER_VALS {
19416  SX_PERF_SEL_PA_IDLE_CYCLES               = 0x00000000,
19417  SX_PERF_SEL_PA_REQ                       = 0x00000001,
19418  SX_PERF_SEL_PA_POS                       = 0x00000002,
19419  SX_PERF_SEL_CLOCK                        = 0x00000003,
19420  SX_PERF_SEL_GATE_EN1                     = 0x00000004,
19421  SX_PERF_SEL_GATE_EN2                     = 0x00000005,
19422  SX_PERF_SEL_GATE_EN3                     = 0x00000006,
19423  SX_PERF_SEL_GATE_EN4                     = 0x00000007,
19424  SX_PERF_SEL_SH_POS_STARVE                = 0x00000008,
19425  SX_PERF_SEL_SH_COLOR_STARVE              = 0x00000009,
19426  SX_PERF_SEL_SH_POS_STALL                 = 0x0000000a,
19427  SX_PERF_SEL_SH_COLOR_STALL               = 0x0000000b,
19428  SX_PERF_SEL_DB0_PIXELS                   = 0x0000000c,
19429  SX_PERF_SEL_DB0_HALF_QUADS               = 0x0000000d,
19430  SX_PERF_SEL_DB0_PIXEL_STALL              = 0x0000000e,
19431  SX_PERF_SEL_DB0_PIXEL_IDLE               = 0x0000000f,
19432  SX_PERF_SEL_DB0_PRED_PIXELS              = 0x00000010,
19433  SX_PERF_SEL_DB1_PIXELS                   = 0x00000011,
19434  SX_PERF_SEL_DB1_HALF_QUADS               = 0x00000012,
19435  SX_PERF_SEL_DB1_PIXEL_STALL              = 0x00000013,
19436  SX_PERF_SEL_DB1_PIXEL_IDLE               = 0x00000014,
19437  SX_PERF_SEL_DB1_PRED_PIXELS              = 0x00000015,
19438  SX_PERF_SEL_DB2_PIXELS                   = 0x00000016,
19439  SX_PERF_SEL_DB2_HALF_QUADS               = 0x00000017,
19440  SX_PERF_SEL_DB2_PIXEL_STALL              = 0x00000018,
19441  SX_PERF_SEL_DB2_PIXEL_IDLE               = 0x00000019,
19442  SX_PERF_SEL_DB2_PRED_PIXELS              = 0x0000001a,
19443  SX_PERF_SEL_DB3_PIXELS                   = 0x0000001b,
19444  SX_PERF_SEL_DB3_HALF_QUADS               = 0x0000001c,
19445  SX_PERF_SEL_DB3_PIXEL_STALL              = 0x0000001d,
19446  SX_PERF_SEL_DB3_PIXEL_IDLE               = 0x0000001e,
19447  SX_PERF_SEL_DB3_PRED_PIXELS              = 0x0000001f,
19448  SX_PERF_SEL_COL_BUSY                     = 0x00000020,
19449  SX_PERF_SEL_POS_BUSY                     = 0x00000021,
19450  SX_PERF_SEL_DB0_MRT_BLEND_BYPASS         = 0x00000022,
19451  SX_PERF_SEL_DB0_MRT_DONT_RD_DEST         = 0x00000023,
19452  SX_PERF_SEL_DB0_MRT_DISCARD_SRC          = 0x00000024,
19453  SX_PERF_SEL_DB0_MRT_SINGLE_QUADS         = 0x00000025,
19454  SX_PERF_SEL_DB0_MRT_DOUBLE_QUADS         = 0x00000026,
19455  SX_PERF_SEL_DB1_MRT_BLEND_BYPASS         = 0x00000027,
19456  SX_PERF_SEL_DB1_MRT_DONT_RD_DEST         = 0x00000028,
19457  SX_PERF_SEL_DB1_MRT_DISCARD_SRC          = 0x00000029,
19458  SX_PERF_SEL_DB1_MRT_SINGLE_QUADS         = 0x0000002a,
19459  SX_PERF_SEL_DB1_MRT_DOUBLE_QUADS         = 0x0000002b,
19460  SX_PERF_SEL_DB2_MRT_BLEND_BYPASS         = 0x0000002c,
19461  SX_PERF_SEL_DB2_MRT_DONT_RD_DEST         = 0x0000002d,
19462  SX_PERF_SEL_DB2_MRT_DISCARD_SRC          = 0x0000002e,
19463  SX_PERF_SEL_DB2_MRT_SINGLE_QUADS         = 0x0000002f,
19464  SX_PERF_SEL_DB2_MRT_DOUBLE_QUADS         = 0x00000030,
19465  SX_PERF_SEL_DB3_MRT_BLEND_BYPASS         = 0x00000031,
19466  SX_PERF_SEL_DB3_MRT_DONT_RD_DEST         = 0x00000032,
19467  SX_PERF_SEL_DB3_MRT_DISCARD_SRC          = 0x00000033,
19468  SX_PERF_SEL_DB3_MRT_SINGLE_QUADS         = 0x00000034,
19469  SX_PERF_SEL_DB3_MRT_DOUBLE_QUADS         = 0x00000035,
19470  SX_PERF_SEL_PA_REQ_LATENCY               = 0x00000036,
19471  SX_PERF_SEL_POS_SCBD_STALL               = 0x00000037,
19472  SX_PERF_SEL_CLOCK_DROP_STALL             = 0x00000038,
19473  SX_PERF_SEL_GATE_EN5                     = 0x00000039,
19474  SX_PERF_SEL_GATE_EN6                     = 0x0000003a,
19475  SX_PERF_SEL_DB0_SIZE                     = 0x0000003b,
19476  SX_PERF_SEL_DB1_SIZE                     = 0x0000003c,
19477  SX_PERF_SEL_DB2_SIZE                     = 0x0000003d,
19478  SX_PERF_SEL_DB3_SIZE                     = 0x0000003e,
19479  SX_PERF_SEL_IDX_STALL_CYCLES             = 0x0000003f,
19480  SX_PERF_SEL_IDX_IDLE_CYCLES              = 0x00000040,
19481  SX_PERF_SEL_IDX_REQ                      = 0x00000041,
19482  SX_PERF_SEL_IDX_RET                      = 0x00000042,
19483  SX_PERF_SEL_IDX_REQ_LATENCY              = 0x00000043,
19484  SX_PERF_SEL_IDX_SCBD_STALL               = 0x00000044,
19485  SX_PERF_SEL_GATE_EN7                     = 0x00000045,
19486  SX_PERF_SEL_GATE_EN8                     = 0x00000046,
19487  SX_PERF_SEL_SH_IDX_STARVE                = 0x00000047,
19488  SX_PERF_SEL_IDX_BUSY                     = 0x00000048,
19489  SX_PERF_SEL_PA_POS_BANK_CONF             = 0x00000049,
19490  SX_PERF_SEL_DB0_END_OF_WAVE              = 0x0000004a,
19491  SX_PERF_SEL_DB0_4X2_DISCARD              = 0x0000004b,
19492  SX_PERF_SEL_DB1_END_OF_WAVE              = 0x0000004c,
19493  SX_PERF_SEL_DB1_4X2_DISCARD              = 0x0000004d,
19494  SX_PERF_SEL_DB2_END_OF_WAVE              = 0x0000004e,
19495  SX_PERF_SEL_DB2_4X2_DISCARD              = 0x0000004f,
19496  SX_PERF_SEL_DB3_END_OF_WAVE              = 0x00000050,
19497  SX_PERF_SEL_DB3_4X2_DISCARD              = 0x00000051,
19498  } SX_PERFCOUNTER_VALS;
19499  
19500  /*******************************************************
19501   * DB Enums
19502   *******************************************************/
19503  
19504  /*
19505   * CompareFrag enum
19506   */
19507  
19508  typedef enum CompareFrag {
19509  FRAG_NEVER                               = 0x00000000,
19510  FRAG_LESS                                = 0x00000001,
19511  FRAG_EQUAL                               = 0x00000002,
19512  FRAG_LEQUAL                              = 0x00000003,
19513  FRAG_GREATER                             = 0x00000004,
19514  FRAG_NOTEQUAL                            = 0x00000005,
19515  FRAG_GEQUAL                              = 0x00000006,
19516  FRAG_ALWAYS                              = 0x00000007,
19517  } CompareFrag;
19518  
19519  /*
19520   * ConservativeZExport enum
19521   */
19522  
19523  typedef enum ConservativeZExport {
19524  EXPORT_ANY_Z                             = 0x00000000,
19525  EXPORT_LESS_THAN_Z                       = 0x00000001,
19526  EXPORT_GREATER_THAN_Z                    = 0x00000002,
19527  EXPORT_RESERVED                          = 0x00000003,
19528  } ConservativeZExport;
19529  
19530  /*
19531   * DFSMFlushEvents enum
19532   */
19533  
19534  typedef enum DFSMFlushEvents {
19535  DB_FLUSH_AND_INV_DB_DATA_TS              = 0x00000000,
19536  DB_FLUSH_AND_INV_DB_META                 = 0x00000001,
19537  DB_CACHE_FLUSH                           = 0x00000002,
19538  DB_CACHE_FLUSH_TS                        = 0x00000003,
19539  DB_CACHE_FLUSH_AND_INV_EVENT             = 0x00000004,
19540  DB_CACHE_FLUSH_AND_INV_TS_EVENT          = 0x00000005,
19541  DB_VPORT_CHANGED_EVENT                   = 0x00000006,
19542  DB_CONTEXT_DONE_EVENT                    = 0x00000007,
19543  DB_BREAK_BATCH_EVENT                     = 0x00000008,
19544  DB_INVOKE_CHANGE_EVENT                   = 0x00000009,
19545  DB_CONTEXT_SUSPEND_EVENT                 = 0x0000000a,
19546  } DFSMFlushEvents;
19547  
19548  /*
19549   * DbMemArbWatermarks enum
19550   */
19551  
19552  typedef enum DbMemArbWatermarks {
19553  TRANSFERRED_64_BYTES                     = 0x00000000,
19554  TRANSFERRED_128_BYTES                    = 0x00000001,
19555  TRANSFERRED_256_BYTES                    = 0x00000002,
19556  TRANSFERRED_512_BYTES                    = 0x00000003,
19557  TRANSFERRED_1024_BYTES                   = 0x00000004,
19558  TRANSFERRED_2048_BYTES                   = 0x00000005,
19559  TRANSFERRED_4096_BYTES                   = 0x00000006,
19560  TRANSFERRED_8192_BYTES                   = 0x00000007,
19561  } DbMemArbWatermarks;
19562  
19563  /*
19564   * DbPRTFaultBehavior enum
19565   */
19566  
19567  typedef enum DbPRTFaultBehavior {
19568  FAULT_ZERO                               = 0x00000000,
19569  FAULT_ONE                                = 0x00000001,
19570  FAULT_FAIL                               = 0x00000002,
19571  FAULT_PASS                               = 0x00000003,
19572  } DbPRTFaultBehavior;
19573  
19574  /*
19575   * DbPSLControl enum
19576   */
19577  
19578  typedef enum DbPSLControl {
19579  PSLC_AUTO                                = 0x00000000,
19580  PSLC_ON_HANG_ONLY                        = 0x00000001,
19581  PSLC_ASAP                                = 0x00000002,
19582  PSLC_COUNTDOWN                           = 0x00000003,
19583  } DbPSLControl;
19584  
19585  /*
19586   * ForceControl enum
19587   */
19588  
19589  typedef enum ForceControl {
19590  FORCE_OFF                                = 0x00000000,
19591  FORCE_ENABLE                             = 0x00000001,
19592  FORCE_DISABLE                            = 0x00000002,
19593  FORCE_RESERVED                           = 0x00000003,
19594  } ForceControl;
19595  
19596  /*
19597   * OreoMode enum
19598   */
19599  
19600  typedef enum OreoMode {
19601  OMODE_BLEND                              = 0x00000000,
19602  OMODE_O_THEN_B                           = 0x00000001,
19603  OMODE_P_THEN_O_THEN_B                    = 0x00000002,
19604  OMODE_RESERVED_3                         = 0x00000003,
19605  } OreoMode;
19606  
19607  /*
19608   * PerfCounter_Vals enum
19609   */
19610  
19611  typedef enum PerfCounter_Vals {
19612  DB_PERF_SEL_SC_DB_tile_sends             = 0x00000000,
19613  DB_PERF_SEL_SC_DB_tile_busy              = 0x00000001,
19614  DB_PERF_SEL_SC_DB_tile_stalls            = 0x00000002,
19615  DB_PERF_SEL_SC_DB_tile_events            = 0x00000003,
19616  DB_PERF_SEL_SC_DB_tile_tiles             = 0x00000004,
19617  DB_PERF_SEL_SC_DB_tile_covered           = 0x00000005,
19618  DB_PERF_SEL_hiz_tc_read_starved          = 0x00000006,
19619  DB_PERF_SEL_hiz_tc_write_stall           = 0x00000007,
19620  DB_PERF_SEL_hiz_tile_culled              = 0x00000008,
19621  DB_PERF_SEL_his_tile_culled              = 0x00000009,
19622  DB_PERF_SEL_DB_SC_tile_sends             = 0x0000000a,
19623  DB_PERF_SEL_DB_SC_tile_busy              = 0x0000000b,
19624  DB_PERF_SEL_DB_SC_tile_stalls            = 0x0000000c,
19625  DB_PERF_SEL_DB_SC_tile_df_stalls         = 0x0000000d,
19626  DB_PERF_SEL_DB_SC_tile_tiles             = 0x0000000e,
19627  DB_PERF_SEL_DB_SC_tile_culled            = 0x0000000f,
19628  DB_PERF_SEL_DB_SC_tile_hier_kill         = 0x00000010,
19629  DB_PERF_SEL_DB_SC_tile_fast_ops          = 0x00000011,
19630  DB_PERF_SEL_DB_SC_tile_no_ops            = 0x00000012,
19631  DB_PERF_SEL_DB_SC_tile_tile_rate         = 0x00000013,
19632  DB_PERF_SEL_DB_SC_tile_ssaa_kill         = 0x00000014,
19633  DB_PERF_SEL_DB_SC_tile_fast_z_ops        = 0x00000015,
19634  DB_PERF_SEL_DB_SC_tile_fast_stencil_ops  = 0x00000016,
19635  DB_PERF_SEL_SC_DB_quad_sends             = 0x00000017,
19636  DB_PERF_SEL_SC_DB_quad_busy              = 0x00000018,
19637  DB_PERF_SEL_SC_DB_quad_squads            = 0x00000019,
19638  DB_PERF_SEL_SC_DB_quad_tiles             = 0x0000001a,
19639  DB_PERF_SEL_SC_DB_quad_pixels            = 0x0000001b,
19640  DB_PERF_SEL_SC_DB_quad_killed_tiles      = 0x0000001c,
19641  DB_PERF_SEL_DB_SC_quad_sends             = 0x0000001d,
19642  DB_PERF_SEL_DB_SC_quad_busy              = 0x0000001e,
19643  DB_PERF_SEL_DB_SC_quad_stalls            = 0x0000001f,
19644  DB_PERF_SEL_DB_SC_quad_tiles             = 0x00000020,
19645  DB_PERF_SEL_DB_SC_quad_lit_quad          = 0x00000021,
19646  DB_PERF_SEL_DB_CB_tile_sends             = 0x00000022,
19647  DB_PERF_SEL_DB_CB_tile_busy              = 0x00000023,
19648  DB_PERF_SEL_DB_CB_tile_stalls            = 0x00000024,
19649  DB_PERF_SEL_SX_DB_quad_sends             = 0x00000025,
19650  DB_PERF_SEL_SX_DB_quad_busy              = 0x00000026,
19651  DB_PERF_SEL_SX_DB_quad_stalls            = 0x00000027,
19652  DB_PERF_SEL_SX_DB_quad_quads             = 0x00000028,
19653  DB_PERF_SEL_SX_DB_quad_pixels            = 0x00000029,
19654  DB_PERF_SEL_SX_DB_quad_exports           = 0x0000002a,
19655  DB_PERF_SEL_SH_quads_outstanding_sum     = 0x0000002b,
19656  DB_PERF_SEL_DB_CB_lquad_sends            = 0x0000002c,
19657  DB_PERF_SEL_DB_CB_lquad_busy             = 0x0000002d,
19658  DB_PERF_SEL_DB_CB_lquad_stalls           = 0x0000002e,
19659  DB_PERF_SEL_DB_CB_lquad_quads            = 0x0000002f,
19660  DB_PERF_SEL_tile_rd_sends                = 0x00000030,
19661  DB_PERF_SEL_mi_tile_rd_outstanding_sum   = 0x00000031,
19662  DB_PERF_SEL_quad_rd_sends                = 0x00000032,
19663  DB_PERF_SEL_quad_rd_busy                 = 0x00000033,
19664  DB_PERF_SEL_quad_rd_mi_stall             = 0x00000034,
19665  DB_PERF_SEL_quad_rd_rw_collision         = 0x00000035,
19666  DB_PERF_SEL_quad_rd_tag_stall            = 0x00000036,
19667  DB_PERF_SEL_quad_rd_32byte_reqs          = 0x00000037,
19668  DB_PERF_SEL_quad_rd_panic                = 0x00000038,
19669  DB_PERF_SEL_mi_quad_rd_outstanding_sum   = 0x00000039,
19670  DB_PERF_SEL_quad_rdret_sends             = 0x0000003a,
19671  DB_PERF_SEL_quad_rdret_busy              = 0x0000003b,
19672  DB_PERF_SEL_tile_wr_sends                = 0x0000003c,
19673  DB_PERF_SEL_tile_wr_acks                 = 0x0000003d,
19674  DB_PERF_SEL_mi_tile_wr_outstanding_sum   = 0x0000003e,
19675  DB_PERF_SEL_quad_wr_sends                = 0x0000003f,
19676  DB_PERF_SEL_quad_wr_busy                 = 0x00000040,
19677  DB_PERF_SEL_quad_wr_mi_stall             = 0x00000041,
19678  DB_PERF_SEL_quad_wr_coherency_stall      = 0x00000042,
19679  DB_PERF_SEL_quad_wr_acks                 = 0x00000043,
19680  DB_PERF_SEL_mi_quad_wr_outstanding_sum   = 0x00000044,
19681  DB_PERF_SEL_Tile_Cache_misses            = 0x00000045,
19682  DB_PERF_SEL_Tile_Cache_hits              = 0x00000046,
19683  DB_PERF_SEL_Tile_Cache_flushes           = 0x00000047,
19684  DB_PERF_SEL_Tile_Cache_surface_stall     = 0x00000048,
19685  DB_PERF_SEL_Tile_Cache_starves           = 0x00000049,
19686  DB_PERF_SEL_Tile_Cache_mem_return_starve = 0x0000004a,
19687  DB_PERF_SEL_tcp_dispatcher_reads         = 0x0000004b,
19688  DB_PERF_SEL_tcp_prefetcher_reads         = 0x0000004c,
19689  DB_PERF_SEL_tcp_preloader_reads          = 0x0000004d,
19690  DB_PERF_SEL_tcp_dispatcher_flushes       = 0x0000004e,
19691  DB_PERF_SEL_tcp_prefetcher_flushes       = 0x0000004f,
19692  DB_PERF_SEL_tcp_preloader_flushes        = 0x00000050,
19693  DB_PERF_SEL_Depth_Tile_Cache_sends       = 0x00000051,
19694  DB_PERF_SEL_Depth_Tile_Cache_busy        = 0x00000052,
19695  DB_PERF_SEL_Depth_Tile_Cache_starves     = 0x00000053,
19696  DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 0x00000054,
19697  DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 0x00000055,
19698  DB_PERF_SEL_Depth_Tile_Cache_misses      = 0x00000056,
19699  DB_PERF_SEL_Depth_Tile_Cache_hits        = 0x00000057,
19700  DB_PERF_SEL_Depth_Tile_Cache_flushes     = 0x00000058,
19701  DB_PERF_SEL_Depth_Tile_Cache_noop_tile   = 0x00000059,
19702  DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 0x0000005a,
19703  DB_PERF_SEL_Depth_Tile_Cache_event       = 0x0000005b,
19704  DB_PERF_SEL_Depth_Tile_Cache_tile_frees  = 0x0000005c,
19705  DB_PERF_SEL_Depth_Tile_Cache_data_frees  = 0x0000005d,
19706  DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 0x0000005e,
19707  DB_PERF_SEL_Stencil_Cache_misses         = 0x0000005f,
19708  DB_PERF_SEL_Stencil_Cache_hits           = 0x00000060,
19709  DB_PERF_SEL_Stencil_Cache_flushes        = 0x00000061,
19710  DB_PERF_SEL_Stencil_Cache_starves        = 0x00000062,
19711  DB_PERF_SEL_Stencil_Cache_frees          = 0x00000063,
19712  DB_PERF_SEL_Z_Cache_separate_Z_misses    = 0x00000064,
19713  DB_PERF_SEL_Z_Cache_separate_Z_hits      = 0x00000065,
19714  DB_PERF_SEL_Z_Cache_separate_Z_flushes   = 0x00000066,
19715  DB_PERF_SEL_Z_Cache_separate_Z_starves   = 0x00000067,
19716  DB_PERF_SEL_Z_Cache_pmask_misses         = 0x00000068,
19717  DB_PERF_SEL_Z_Cache_pmask_hits           = 0x00000069,
19718  DB_PERF_SEL_Z_Cache_pmask_flushes        = 0x0000006a,
19719  DB_PERF_SEL_Z_Cache_pmask_starves        = 0x0000006b,
19720  DB_PERF_SEL_Z_Cache_frees                = 0x0000006c,
19721  DB_PERF_SEL_Plane_Cache_misses           = 0x0000006d,
19722  DB_PERF_SEL_Plane_Cache_hits             = 0x0000006e,
19723  DB_PERF_SEL_Plane_Cache_flushes          = 0x0000006f,
19724  DB_PERF_SEL_Plane_Cache_starves          = 0x00000070,
19725  DB_PERF_SEL_Plane_Cache_frees            = 0x00000071,
19726  DB_PERF_SEL_flush_expanded_stencil       = 0x00000072,
19727  DB_PERF_SEL_flush_compressed_stencil     = 0x00000073,
19728  DB_PERF_SEL_flush_single_stencil         = 0x00000074,
19729  DB_PERF_SEL_planes_flushed               = 0x00000075,
19730  DB_PERF_SEL_flush_1plane                 = 0x00000076,
19731  DB_PERF_SEL_flush_2plane                 = 0x00000077,
19732  DB_PERF_SEL_flush_3plane                 = 0x00000078,
19733  DB_PERF_SEL_flush_4plane                 = 0x00000079,
19734  DB_PERF_SEL_flush_5plane                 = 0x0000007a,
19735  DB_PERF_SEL_flush_6plane                 = 0x0000007b,
19736  DB_PERF_SEL_flush_7plane                 = 0x0000007c,
19737  DB_PERF_SEL_flush_8plane                 = 0x0000007d,
19738  DB_PERF_SEL_flush_9plane                 = 0x0000007e,
19739  DB_PERF_SEL_flush_10plane                = 0x0000007f,
19740  DB_PERF_SEL_flush_11plane                = 0x00000080,
19741  DB_PERF_SEL_flush_12plane                = 0x00000081,
19742  DB_PERF_SEL_flush_13plane                = 0x00000082,
19743  DB_PERF_SEL_flush_14plane                = 0x00000083,
19744  DB_PERF_SEL_flush_15plane                = 0x00000084,
19745  DB_PERF_SEL_flush_16plane                = 0x00000085,
19746  DB_PERF_SEL_flush_expanded_z             = 0x00000086,
19747  DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 0x00000087,
19748  DB_PERF_SEL_reZ_waiting_for_postZ_done   = 0x00000088,
19749  DB_PERF_SEL_dk_tile_sends                = 0x00000089,
19750  DB_PERF_SEL_dk_tile_busy                 = 0x0000008a,
19751  DB_PERF_SEL_dk_tile_quad_starves         = 0x0000008b,
19752  DB_PERF_SEL_dk_tile_stalls               = 0x0000008c,
19753  DB_PERF_SEL_dk_squad_sends               = 0x0000008d,
19754  DB_PERF_SEL_dk_squad_busy                = 0x0000008e,
19755  DB_PERF_SEL_dk_squad_stalls              = 0x0000008f,
19756  DB_PERF_SEL_Op_Pipe_Busy                 = 0x00000090,
19757  DB_PERF_SEL_Op_Pipe_MC_Read_stall        = 0x00000091,
19758  DB_PERF_SEL_qc_busy                      = 0x00000092,
19759  DB_PERF_SEL_qc_xfc                       = 0x00000093,
19760  DB_PERF_SEL_qc_conflicts                 = 0x00000094,
19761  DB_PERF_SEL_qc_full_stall                = 0x00000095,
19762  DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 0x00000096,
19763  DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 0x00000097,
19764  DB_PERF_SEL_tsc_insert_summarize_stall   = 0x00000098,
19765  DB_PERF_SEL_tl_busy                      = 0x00000099,
19766  DB_PERF_SEL_tl_dtc_read_starved          = 0x0000009a,
19767  DB_PERF_SEL_tl_z_fetch_stall             = 0x0000009b,
19768  DB_PERF_SEL_tl_stencil_stall             = 0x0000009c,
19769  DB_PERF_SEL_tl_z_decompress_stall        = 0x0000009d,
19770  DB_PERF_SEL_tl_stencil_locked_stall      = 0x0000009e,
19771  DB_PERF_SEL_tl_events                    = 0x0000009f,
19772  DB_PERF_SEL_tl_summarize_squads          = 0x000000a0,
19773  DB_PERF_SEL_tl_flush_expand_squads       = 0x000000a1,
19774  DB_PERF_SEL_tl_expand_squads             = 0x000000a2,
19775  DB_PERF_SEL_tl_preZ_squads               = 0x000000a3,
19776  DB_PERF_SEL_tl_postZ_squads              = 0x000000a4,
19777  DB_PERF_SEL_tl_preZ_noop_squads          = 0x000000a5,
19778  DB_PERF_SEL_tl_postZ_noop_squads         = 0x000000a6,
19779  DB_PERF_SEL_tl_tile_ops                  = 0x000000a7,
19780  DB_PERF_SEL_tl_in_xfc                    = 0x000000a8,
19781  DB_PERF_SEL_tl_in_single_stencil_expand_stall = 0x000000a9,
19782  DB_PERF_SEL_tl_in_fast_z_stall           = 0x000000aa,
19783  DB_PERF_SEL_tl_out_xfc                   = 0x000000ab,
19784  DB_PERF_SEL_tl_out_squads                = 0x000000ac,
19785  DB_PERF_SEL_zf_plane_multicycle          = 0x000000ad,
19786  DB_PERF_SEL_PostZ_Samples_passing_Z      = 0x000000ae,
19787  DB_PERF_SEL_PostZ_Samples_failing_Z      = 0x000000af,
19788  DB_PERF_SEL_PostZ_Samples_failing_S      = 0x000000b0,
19789  DB_PERF_SEL_PreZ_Samples_passing_Z       = 0x000000b1,
19790  DB_PERF_SEL_PreZ_Samples_failing_Z       = 0x000000b2,
19791  DB_PERF_SEL_PreZ_Samples_failing_S       = 0x000000b3,
19792  DB_PERF_SEL_ts_tc_update_stall           = 0x000000b4,
19793  DB_PERF_SEL_sc_kick_start                = 0x000000b5,
19794  DB_PERF_SEL_sc_kick_end                  = 0x000000b6,
19795  DB_PERF_SEL_clock_reg_active             = 0x000000b7,
19796  DB_PERF_SEL_clock_main_active            = 0x000000b8,
19797  DB_PERF_SEL_clock_mem_export_active      = 0x000000b9,
19798  DB_PERF_SEL_esr_ps_out_busy              = 0x000000ba,
19799  DB_PERF_SEL_esr_ps_lqf_busy              = 0x000000bb,
19800  DB_PERF_SEL_esr_ps_lqf_stall             = 0x000000bc,
19801  DB_PERF_SEL_etr_out_send                 = 0x000000bd,
19802  DB_PERF_SEL_etr_out_busy                 = 0x000000be,
19803  DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 0x000000bf,
19804  DB_PERF_SEL_etr_out_cb_tile_stall        = 0x000000c0,
19805  DB_PERF_SEL_etr_out_esr_stall            = 0x000000c1,
19806  DB_PERF_SEL_esr_ps_vic_busy              = 0x000000c2,
19807  DB_PERF_SEL_esr_ps_vic_stall             = 0x000000c3,
19808  DB_PERF_SEL_esr_eot_fwd_busy             = 0x000000c4,
19809  DB_PERF_SEL_esr_eot_fwd_holding_squad    = 0x000000c5,
19810  DB_PERF_SEL_esr_eot_fwd_forward          = 0x000000c6,
19811  DB_PERF_SEL_esr_sqq_zi_busy              = 0x000000c7,
19812  DB_PERF_SEL_esr_sqq_zi_stall             = 0x000000c8,
19813  DB_PERF_SEL_postzl_sq_pt_busy            = 0x000000c9,
19814  DB_PERF_SEL_postzl_sq_pt_stall           = 0x000000ca,
19815  DB_PERF_SEL_postzl_se_busy               = 0x000000cb,
19816  DB_PERF_SEL_postzl_se_stall              = 0x000000cc,
19817  DB_PERF_SEL_postzl_partial_launch        = 0x000000cd,
19818  DB_PERF_SEL_postzl_full_launch           = 0x000000ce,
19819  DB_PERF_SEL_postzl_partial_waiting       = 0x000000cf,
19820  DB_PERF_SEL_postzl_tile_mem_stall        = 0x000000d0,
19821  DB_PERF_SEL_postzl_tile_init_stall       = 0x000000d1,
19822  DB_PERF_SEL_prezl_tile_mem_stall         = 0x000000d2,
19823  DB_PERF_SEL_prezl_tile_init_stall        = 0x000000d3,
19824  DB_PERF_SEL_dtt_sm_clash_stall           = 0x000000d4,
19825  DB_PERF_SEL_dtt_sm_slot_stall            = 0x000000d5,
19826  DB_PERF_SEL_dtt_sm_miss_stall            = 0x000000d6,
19827  DB_PERF_SEL_mi_rdreq_busy                = 0x000000d7,
19828  DB_PERF_SEL_mi_rdreq_stall               = 0x000000d8,
19829  DB_PERF_SEL_mi_wrreq_busy                = 0x000000d9,
19830  DB_PERF_SEL_mi_wrreq_stall               = 0x000000da,
19831  DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 0x000000db,
19832  DB_PERF_SEL_dkg_tile_rate_tile           = 0x000000dc,
19833  DB_PERF_SEL_prezl_src_in_sends           = 0x000000dd,
19834  DB_PERF_SEL_prezl_src_in_stall           = 0x000000de,
19835  DB_PERF_SEL_prezl_src_in_squads          = 0x000000df,
19836  DB_PERF_SEL_prezl_src_in_squads_unrolled = 0x000000e0,
19837  DB_PERF_SEL_prezl_src_in_tile_rate       = 0x000000e1,
19838  DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 0x000000e2,
19839  DB_PERF_SEL_prezl_src_out_stall          = 0x000000e3,
19840  DB_PERF_SEL_postzl_src_in_sends          = 0x000000e4,
19841  DB_PERF_SEL_postzl_src_in_stall          = 0x000000e5,
19842  DB_PERF_SEL_postzl_src_in_squads         = 0x000000e6,
19843  DB_PERF_SEL_postzl_src_in_squads_unrolled = 0x000000e7,
19844  DB_PERF_SEL_postzl_src_in_tile_rate      = 0x000000e8,
19845  DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 0x000000e9,
19846  DB_PERF_SEL_postzl_src_out_stall         = 0x000000ea,
19847  DB_PERF_SEL_esr_ps_src_in_sends          = 0x000000eb,
19848  DB_PERF_SEL_esr_ps_src_in_stall          = 0x000000ec,
19849  DB_PERF_SEL_esr_ps_src_in_squads         = 0x000000ed,
19850  DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 0x000000ee,
19851  DB_PERF_SEL_esr_ps_src_in_tile_rate      = 0x000000ef,
19852  DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 0x000000f0,
19853  DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate = 0x000000f1,
19854  DB_PERF_SEL_esr_ps_src_out_stall         = 0x000000f2,
19855  DB_PERF_SEL_depth_bounds_tile_culled     = 0x000000f3,
19856  DB_PERF_SEL_PreZ_Samples_failing_DB      = 0x000000f4,
19857  DB_PERF_SEL_PostZ_Samples_failing_DB     = 0x000000f5,
19858  DB_PERF_SEL_flush_compressed             = 0x000000f6,
19859  DB_PERF_SEL_flush_plane_le4              = 0x000000f7,
19860  DB_PERF_SEL_tiles_z_fully_summarized     = 0x000000f8,
19861  DB_PERF_SEL_tiles_stencil_fully_summarized = 0x000000f9,
19862  DB_PERF_SEL_tiles_z_clear_on_expclear    = 0x000000fa,
19863  DB_PERF_SEL_tiles_s_clear_on_expclear    = 0x000000fb,
19864  DB_PERF_SEL_tiles_decomp_on_expclear     = 0x000000fc,
19865  DB_PERF_SEL_tiles_compressed_to_decompressed = 0x000000fd,
19866  DB_PERF_SEL_Op_Pipe_Prez_Busy            = 0x000000fe,
19867  DB_PERF_SEL_Op_Pipe_Postz_Busy           = 0x000000ff,
19868  DB_PERF_SEL_di_dt_stall                  = 0x00000100,
19869  Spare_257                                = 0x00000101,
19870  DB_PERF_SEL_DB_SC_s_tile_rate            = 0x00000102,
19871  DB_PERF_SEL_DB_SC_c_tile_rate            = 0x00000103,
19872  DB_PERF_SEL_DB_SC_z_tile_rate            = 0x00000104,
19873  DB_PERF_SEL_DB_CB_lquad_export_quads     = 0x00000105,
19874  DB_PERF_SEL_DB_CB_lquad_double_format    = 0x00000106,
19875  DB_PERF_SEL_DB_CB_lquad_fast_format      = 0x00000107,
19876  DB_PERF_SEL_DB_CB_lquad_slow_format      = 0x00000108,
19877  DB_PERF_SEL_CB_DB_rdreq_sends            = 0x00000109,
19878  DB_PERF_SEL_CB_DB_rdreq_prt_sends        = 0x0000010a,
19879  DB_PERF_SEL_CB_DB_wrreq_sends            = 0x0000010b,
19880  DB_PERF_SEL_CB_DB_wrreq_prt_sends        = 0x0000010c,
19881  DB_PERF_SEL_DB_CB_rdret_ack              = 0x0000010d,
19882  DB_PERF_SEL_DB_CB_rdret_nack             = 0x0000010e,
19883  DB_PERF_SEL_DB_CB_wrret_ack              = 0x0000010f,
19884  DB_PERF_SEL_DB_CB_wrret_nack             = 0x00000110,
19885  DB_PERF_SEL_MI_tile_req_wrack_counter_stall = 0x00000111,
19886  DB_PERF_SEL_MI_quad_req_wrack_counter_stall = 0x00000112,
19887  DB_PERF_SEL_MI_zpc_req_wrack_counter_stall = 0x00000113,
19888  DB_PERF_SEL_MI_psd_req_wrack_counter_stall = 0x00000114,
19889  DB_PERF_SEL_unmapped_z_tile_culled       = 0x00000115,
19890  DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_DB_DATA_TS = 0x00000116,
19891  DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_CB_PIXEL_DATA = 0x00000117,
19892  DB_PERF_SEL_DB_CB_tile_is_event_BOTTOM_OF_PIPE_TS = 0x00000118,
19893  DB_PERF_SEL_DB_CB_tile_waiting_for_perfcounter_stop_event = 0x00000119,
19894  DB_PERF_SEL_DB_CB_lquad_fmt_32bpp_8pix   = 0x0000011a,
19895  DB_PERF_SEL_DB_CB_lquad_fmt_16_16_unsigned_8pix = 0x0000011b,
19896  DB_PERF_SEL_DB_CB_lquad_fmt_16_16_signed_8pix = 0x0000011c,
19897  DB_PERF_SEL_DB_CB_lquad_fmt_16_16_float_8pix = 0x0000011d,
19898  DB_PERF_SEL_DB_CB_lquad_num_pixels_need_blending = 0x0000011e,
19899  DB_PERF_SEL_DB_CB_context_dones          = 0x0000011f,
19900  DB_PERF_SEL_DB_CB_eop_dones              = 0x00000120,
19901  DB_PERF_SEL_SX_DB_quad_all_pixels_killed = 0x00000121,
19902  DB_PERF_SEL_SX_DB_quad_all_pixels_enabled = 0x00000122,
19903  DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read = 0x00000123,
19904  DB_PERF_SEL_SC_DB_tile_backface          = 0x00000124,
19905  DB_PERF_SEL_SC_DB_quad_quads             = 0x00000125,
19906  DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel = 0x00000126,
19907  DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels = 0x00000127,
19908  DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels = 0x00000128,
19909  DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels = 0x00000129,
19910  DB_PERF_SEL_DB_SC_quad_double_quad       = 0x0000012a,
19911  DB_PERF_SEL_SX_DB_quad_export_quads      = 0x0000012b,
19912  DB_PERF_SEL_SX_DB_quad_double_format     = 0x0000012c,
19913  DB_PERF_SEL_SX_DB_quad_fast_format       = 0x0000012d,
19914  DB_PERF_SEL_SX_DB_quad_slow_format       = 0x0000012e,
19915  DB_PERF_SEL_quad_rd_sends_unc            = 0x0000012f,
19916  DB_PERF_SEL_quad_rd_mi_stall_unc         = 0x00000130,
19917  DB_PERF_SEL_SC_DB_tile_tiles_pipe0       = 0x00000131,
19918  DB_PERF_SEL_SC_DB_tile_tiles_pipe1       = 0x00000132,
19919  DB_PERF_SEL_SC_DB_quad_quads_pipe0       = 0x00000133,
19920  DB_PERF_SEL_SC_DB_quad_quads_pipe1       = 0x00000134,
19921  DB_PERF_SEL_PERF_fg_lob_fwdr_timeout_hits = 0x00000135,
19922  DB_PERF_SEL_noz_waiting_for_postz_done   = 0x00000136,
19923  DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x1 = 0x00000137,
19924  DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x1 = 0x00000138,
19925  DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x2 = 0x00000139,
19926  DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x2 = 0x0000013a,
19927  DB_PERF_SEL_RMI_rd_tile_32byte_req       = 0x0000013b,
19928  DB_PERF_SEL_RMI_rd_z_32byte_req          = 0x0000013c,
19929  DB_PERF_SEL_RMI_rd_s_32byte_req          = 0x0000013d,
19930  DB_PERF_SEL_RMI_wr_tile_32byte_req       = 0x0000013e,
19931  DB_PERF_SEL_RMI_wr_z_32byte_req          = 0x0000013f,
19932  DB_PERF_SEL_RMI_wr_s_32byte_req          = 0x00000140,
19933  DB_PERF_SEL_RMI_wr_psdzpc_32byte_req     = 0x00000141,
19934  DB_PERF_SEL_RMI_rd_tile_32byte_ret       = 0x00000142,
19935  DB_PERF_SEL_RMI_rd_z_32byte_ret          = 0x00000143,
19936  DB_PERF_SEL_RMI_rd_s_32byte_ret          = 0x00000144,
19937  DB_PERF_SEL_RMI_wr_tile_32byte_ack       = 0x00000145,
19938  DB_PERF_SEL_RMI_wr_z_32byte_ack          = 0x00000146,
19939  DB_PERF_SEL_RMI_wr_s_32byte_ack          = 0x00000147,
19940  DB_PERF_SEL_RMI_wr_psdzpc_32byte_ack     = 0x00000148,
19941  DB_PERF_SEL_esr_vic_sqq_busy             = 0x00000149,
19942  DB_PERF_SEL_esr_vic_sqq_stall            = 0x0000014a,
19943  DB_PERF_SEL_esr_psi_vic_tile_rate        = 0x0000014b,
19944  DB_PERF_SEL_esr_vic_footprint_match_2x2  = 0x0000014c,
19945  DB_PERF_SEL_esr_vic_footprint_match_2x1  = 0x0000014d,
19946  DB_PERF_SEL_esr_vic_footprint_match_1x2  = 0x0000014e,
19947  DB_PERF_SEL_DB_SC_quad_num_null_2x2_coarse_pixels = 0x0000014f,
19948  DB_PERF_SEL_DB_SC_quad_num_null_2x1_coarse_pixels = 0x00000150,
19949  DB_PERF_SEL_DB_SC_quad_num_null_1x2_coarse_pixels = 0x00000151,
19950  DB_PERF_SEL_hi_z_s_checker_force_coarse_vrs_1x1 = 0x00000152,
19951  DB_PERF_SEL_hi_z_s_checker_force_ssaa_vrs_1x1 = 0x00000153,
19952  DB_PERF_SEL_esr_ps_woc_1squadIn_2squadOut = 0x00000154,
19953  DB_PERF_SEL_esr_ps_woc_2squadIn_1squadOut = 0x00000155,
19954  DB_PERF_SEL_prez_ps_invoked_pixel_cnt    = 0x00000156,
19955  DB_PERF_SEL_postz_ps_invoked_pixel_cnt   = 0x00000157,
19956  DB_PERF_SEL_ts_events_pws_enable         = 0x00000158,
19957  DB_PERF_SEL_ps_events_pws_enable         = 0x00000159,
19958  DB_PERF_SEL_cs_events_pws_enable         = 0x0000015a,
19959  DB_PERF_SEL_DB_SC_quad_noz_tiles         = 0x0000015b,
19960  DB_PERF_SEL_DB_SC_quad_lit_noz_quad      = 0x0000015c,
19961  } PerfCounter_Vals;
19962  
19963  /*
19964   * PixelPipeCounterId enum
19965   */
19966  
19967  typedef enum PixelPipeCounterId {
19968  PIXEL_PIPE_OCCLUSION_COUNT_0             = 0x00000000,
19969  PIXEL_PIPE_OCCLUSION_COUNT_1             = 0x00000001,
19970  PIXEL_PIPE_OCCLUSION_COUNT_2             = 0x00000002,
19971  PIXEL_PIPE_OCCLUSION_COUNT_3             = 0x00000003,
19972  PIXEL_PIPE_SCREEN_MIN_EXTENTS_0          = 0x00000004,
19973  PIXEL_PIPE_SCREEN_MAX_EXTENTS_0          = 0x00000005,
19974  PIXEL_PIPE_SCREEN_MIN_EXTENTS_1          = 0x00000006,
19975  PIXEL_PIPE_SCREEN_MAX_EXTENTS_1          = 0x00000007,
19976  } PixelPipeCounterId;
19977  
19978  /*
19979   * PixelPipeStride enum
19980   */
19981  
19982  typedef enum PixelPipeStride {
19983  PIXEL_PIPE_STRIDE_32_BITS                = 0x00000000,
19984  PIXEL_PIPE_STRIDE_64_BITS                = 0x00000001,
19985  PIXEL_PIPE_STRIDE_128_BITS               = 0x00000002,
19986  PIXEL_PIPE_STRIDE_256_BITS               = 0x00000003,
19987  } PixelPipeStride;
19988  
19989  /*
19990   * RingCounterControl enum
19991   */
19992  
19993  typedef enum RingCounterControl {
19994  COUNTER_RING_SPLIT                       = 0x00000000,
19995  COUNTER_RING_0                           = 0x00000001,
19996  COUNTER_RING_1                           = 0x00000002,
19997  } RingCounterControl;
19998  
19999  /*
20000   * StencilOp enum
20001   */
20002  
20003  typedef enum StencilOp {
20004  STENCIL_KEEP                             = 0x00000000,
20005  STENCIL_ZERO                             = 0x00000001,
20006  STENCIL_ONES                             = 0x00000002,
20007  STENCIL_REPLACE_TEST                     = 0x00000003,
20008  STENCIL_REPLACE_OP                       = 0x00000004,
20009  STENCIL_ADD_CLAMP                        = 0x00000005,
20010  STENCIL_SUB_CLAMP                        = 0x00000006,
20011  STENCIL_INVERT                           = 0x00000007,
20012  STENCIL_ADD_WRAP                         = 0x00000008,
20013  STENCIL_SUB_WRAP                         = 0x00000009,
20014  STENCIL_AND                              = 0x0000000a,
20015  STENCIL_OR                               = 0x0000000b,
20016  STENCIL_XOR                              = 0x0000000c,
20017  STENCIL_NAND                             = 0x0000000d,
20018  STENCIL_NOR                              = 0x0000000e,
20019  STENCIL_XNOR                             = 0x0000000f,
20020  } StencilOp;
20021  
20022  /*
20023   * ZLimitSumm enum
20024   */
20025  
20026  typedef enum ZLimitSumm {
20027  FORCE_SUMM_OFF                           = 0x00000000,
20028  FORCE_SUMM_MINZ                          = 0x00000001,
20029  FORCE_SUMM_MAXZ                          = 0x00000002,
20030  FORCE_SUMM_BOTH                          = 0x00000003,
20031  } ZLimitSumm;
20032  
20033  /*
20034   * ZModeForce enum
20035   */
20036  
20037  typedef enum ZModeForce {
20038  NO_FORCE                                 = 0x00000000,
20039  FORCE_EARLY_Z                            = 0x00000001,
20040  FORCE_LATE_Z                             = 0x00000002,
20041  FORCE_RE_Z                               = 0x00000003,
20042  } ZModeForce;
20043  
20044  /*
20045   * ZOrder enum
20046   */
20047  
20048  typedef enum ZOrder {
20049  LATE_Z                                   = 0x00000000,
20050  EARLY_Z_THEN_LATE_Z                      = 0x00000001,
20051  RE_Z                                     = 0x00000002,
20052  EARLY_Z_THEN_RE_Z                        = 0x00000003,
20053  } ZOrder;
20054  
20055  /*
20056   * ZSamplePosition enum
20057   */
20058  
20059  typedef enum ZSamplePosition {
20060  Z_SAMPLE_CENTER                          = 0x00000000,
20061  Z_SAMPLE_CENTROID                        = 0x00000001,
20062  } ZSamplePosition;
20063  
20064  /*
20065   * ZpassControl enum
20066   */
20067  
20068  typedef enum ZpassControl {
20069  ZPASS_DISABLE                            = 0x00000000,
20070  ZPASS_SAMPLES                            = 0x00000001,
20071  ZPASS_PIXELS                             = 0x00000002,
20072  } ZpassControl;
20073  
20074  /*******************************************************
20075   * PA Enums
20076   *******************************************************/
20077  
20078  /*
20079   * SU_PERFCNT_SEL enum
20080   */
20081  
20082  typedef enum SU_PERFCNT_SEL {
20083  PERF_PAPC_PASX_REQ                       = 0x00000000,
20084  PERF_PAPC_PASX_DISABLE_PIPE              = 0x00000001,
20085  PERF_PAPC_PASX_FIRST_VECTOR              = 0x00000002,
20086  PERF_PAPC_PASX_SECOND_VECTOR             = 0x00000003,
20087  PERF_PAPC_PASX_FIRST_DEAD                = 0x00000004,
20088  PERF_PAPC_PASX_SECOND_DEAD               = 0x00000005,
20089  PERF_PAPC_PASX_VTX_KILL_DISCARD          = 0x00000006,
20090  PERF_PAPC_PASX_VTX_NAN_DISCARD           = 0x00000007,
20091  PERF_PAPC_PA_INPUT_PRIM                  = 0x00000008,
20092  PERF_PAPC_PA_INPUT_NULL_PRIM             = 0x00000009,
20093  PERF_PAPC_PA_INPUT_EVENT_FLAG            = 0x0000000a,
20094  PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT       = 0x0000000b,
20095  PERF_PAPC_PA_INPUT_END_OF_PACKET         = 0x0000000c,
20096  PERF_PAPC_PA_INPUT_EXTENDED_EVENT        = 0x0000000d,
20097  PERF_PAPC_CLPR_CULL_PRIM                 = 0x0000000e,
20098  PERF_PAPC_CLPR_VVUCP_CULL_PRIM           = 0x0000000f,
20099  PERF_PAPC_CLPR_VV_CULL_PRIM              = 0x00000010,
20100  PERF_PAPC_CLPR_UCP_CULL_PRIM             = 0x00000011,
20101  PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM        = 0x00000012,
20102  PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM         = 0x00000013,
20103  PERF_PAPC_CLPR_CULL_TO_NULL_PRIM         = 0x00000014,
20104  PERF_PAPC_CLPR_VVUCP_CLIP_PRIM           = 0x00000015,
20105  PERF_PAPC_CLPR_VV_CLIP_PRIM              = 0x00000016,
20106  PERF_PAPC_CLPR_UCP_CLIP_PRIM             = 0x00000017,
20107  PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE      = 0x00000018,
20108  PERF_PAPC_CLPR_CLIP_PLANE_CNT_1          = 0x00000019,
20109  PERF_PAPC_CLPR_CLIP_PLANE_CNT_2          = 0x0000001a,
20110  PERF_PAPC_CLPR_CLIP_PLANE_CNT_3          = 0x0000001b,
20111  PERF_PAPC_CLPR_CLIP_PLANE_CNT_4          = 0x0000001c,
20112  PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8        = 0x0000001d,
20113  PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12       = 0x0000001e,
20114  PERF_PAPC_CLPR_CLIP_PLANE_NEAR           = 0x0000001f,
20115  PERF_PAPC_CLPR_CLIP_PLANE_FAR            = 0x00000020,
20116  PERF_PAPC_CLPR_CLIP_PLANE_LEFT           = 0x00000021,
20117  PERF_PAPC_CLPR_CLIP_PLANE_RIGHT          = 0x00000022,
20118  PERF_PAPC_CLPR_CLIP_PLANE_TOP            = 0x00000023,
20119  PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM         = 0x00000024,
20120  PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM        = 0x00000025,
20121  PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM     = 0x00000026,
20122  PERF_PAPC_CLSM_NULL_PRIM                 = 0x00000027,
20123  PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM      = 0x00000028,
20124  PERF_PAPC_CLSM_CULL_TO_NULL_PRIM         = 0x00000029,
20125  PERF_PAPC_CLSM_OUT_PRIM_CNT_1            = 0x0000002a,
20126  PERF_PAPC_CLSM_OUT_PRIM_CNT_2            = 0x0000002b,
20127  PERF_PAPC_CLSM_OUT_PRIM_CNT_3            = 0x0000002c,
20128  PERF_PAPC_CLSM_OUT_PRIM_CNT_4            = 0x0000002d,
20129  PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8          = 0x0000002e,
20130  PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13         = 0x0000002f,
20131  PERF_PAPC_CLIPGA_VTE_KILL_PRIM           = 0x00000030,
20132  PERF_PAPC_SU_INPUT_PRIM                  = 0x00000031,
20133  PERF_PAPC_SU_INPUT_CLIP_PRIM             = 0x00000032,
20134  PERF_PAPC_SU_INPUT_NULL_PRIM             = 0x00000033,
20135  PERF_PAPC_SU_INPUT_PRIM_DUAL             = 0x00000034,
20136  PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL        = 0x00000035,
20137  PERF_PAPC_SU_ZERO_AREA_CULL_PRIM         = 0x00000036,
20138  PERF_PAPC_SU_BACK_FACE_CULL_PRIM         = 0x00000037,
20139  PERF_PAPC_SU_FRONT_FACE_CULL_PRIM        = 0x00000038,
20140  PERF_PAPC_SU_POLYMODE_FACE_CULL          = 0x00000039,
20141  PERF_PAPC_SU_POLYMODE_BACK_CULL          = 0x0000003a,
20142  PERF_PAPC_SU_POLYMODE_FRONT_CULL         = 0x0000003b,
20143  PERF_PAPC_SU_POLYMODE_INVALID_FILL       = 0x0000003c,
20144  PERF_PAPC_SU_OUTPUT_PRIM                 = 0x0000003d,
20145  PERF_PAPC_SU_OUTPUT_CLIP_PRIM            = 0x0000003e,
20146  PERF_PAPC_SU_OUTPUT_NULL_PRIM            = 0x0000003f,
20147  PERF_PAPC_SU_OUTPUT_EVENT_FLAG           = 0x00000040,
20148  PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT      = 0x00000041,
20149  PERF_PAPC_SU_OUTPUT_END_OF_PACKET        = 0x00000042,
20150  PERF_PAPC_SU_OUTPUT_POLYMODE_FACE        = 0x00000043,
20151  PERF_PAPC_SU_OUTPUT_POLYMODE_BACK        = 0x00000044,
20152  PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT       = 0x00000045,
20153  PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE      = 0x00000046,
20154  PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK      = 0x00000047,
20155  PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT     = 0x00000048,
20156  PERF_PAPC_SU_OUTPUT_PRIM_DUAL            = 0x00000049,
20157  PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL       = 0x0000004a,
20158  PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL        = 0x0000004b,
20159  PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL   = 0x0000004c,
20160  PERF_PAPC_PASX_REQ_IDLE                  = 0x0000004d,
20161  PERF_PAPC_PASX_REQ_BUSY                  = 0x0000004e,
20162  PERF_PAPC_PASX_REQ_STALLED               = 0x0000004f,
20163  PERF_PAPC_PASX_REC_IDLE                  = 0x00000050,
20164  PERF_PAPC_PASX_REC_BUSY                  = 0x00000051,
20165  PERF_PAPC_PASX_REC_STARVED_SX            = 0x00000052,
20166  PERF_PAPC_PASX_REC_STALLED               = 0x00000053,
20167  PERF_PAPC_PASX_REC_STALLED_POS_MEM       = 0x00000054,
20168  PERF_PAPC_PASX_REC_STALLED_CCGSM_IN      = 0x00000055,
20169  PERF_PAPC_CCGSM_IDLE                     = 0x00000056,
20170  PERF_PAPC_CCGSM_BUSY                     = 0x00000057,
20171  PERF_PAPC_CCGSM_STALLED                  = 0x00000058,
20172  PERF_PAPC_CLPRIM_IDLE                    = 0x00000059,
20173  PERF_PAPC_CLPRIM_BUSY                    = 0x0000005a,
20174  PERF_PAPC_CLPRIM_STALLED                 = 0x0000005b,
20175  PERF_PAPC_CLPRIM_STARVED_CCGSM           = 0x0000005c,
20176  PERF_PAPC_CLIPSM_IDLE                    = 0x0000005d,
20177  PERF_PAPC_CLIPSM_BUSY                    = 0x0000005e,
20178  PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH     = 0x0000005f,
20179  PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ       = 0x00000060,
20180  PERF_PAPC_CLIPSM_WAIT_CLIPGA             = 0x00000061,
20181  PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP     = 0x00000062,
20182  PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM         = 0x00000063,
20183  PERF_PAPC_CLIPGA_IDLE                    = 0x00000064,
20184  PERF_PAPC_CLIPGA_BUSY                    = 0x00000065,
20185  PERF_PAPC_CLIPGA_STARVED_VTE_CLIP        = 0x00000066,
20186  PERF_PAPC_CLIPGA_STALLED                 = 0x00000067,
20187  PERF_PAPC_CLIP_IDLE                      = 0x00000068,
20188  PERF_PAPC_CLIP_BUSY                      = 0x00000069,
20189  PERF_PAPC_SU_IDLE                        = 0x0000006a,
20190  PERF_PAPC_SU_BUSY                        = 0x0000006b,
20191  PERF_PAPC_SU_STARVED_CLIP                = 0x0000006c,
20192  PERF_PAPC_SU_STALLED_SC                  = 0x0000006d,
20193  PERF_PAPC_CL_DYN_SCLK_VLD                = 0x0000006e,
20194  PERF_PAPC_SU_DYN_SCLK_VLD                = 0x0000006f,
20195  PERF_PAPC_PA_REG_SCLK_VLD                = 0x00000070,
20196  PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL  = 0x00000071,
20197  PERF_PAPC_PASX_SE0_REQ                   = 0x00000072,
20198  PERF_PAPC_PASX_SE1_REQ                   = 0x00000073,
20199  PERF_PAPC_PASX_SE0_FIRST_VECTOR          = 0x00000074,
20200  PERF_PAPC_PASX_SE0_SECOND_VECTOR         = 0x00000075,
20201  PERF_PAPC_PASX_SE1_FIRST_VECTOR          = 0x00000076,
20202  PERF_PAPC_PASX_SE1_SECOND_VECTOR         = 0x00000077,
20203  PERF_PAPC_SU_SE0_PRIM_FILTER_CULL        = 0x00000078,
20204  PERF_PAPC_SU_SE1_PRIM_FILTER_CULL        = 0x00000079,
20205  PERF_PAPC_SU_SE01_PRIM_FILTER_CULL       = 0x0000007a,
20206  PERF_PAPC_SU_SE0_OUTPUT_PRIM             = 0x0000007b,
20207  PERF_PAPC_SU_SE1_OUTPUT_PRIM             = 0x0000007c,
20208  PERF_PAPC_SU_SE01_OUTPUT_PRIM            = 0x0000007d,
20209  PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM        = 0x0000007e,
20210  PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM        = 0x0000007f,
20211  PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM       = 0x00000080,
20212  PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT  = 0x00000081,
20213  PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT  = 0x00000082,
20214  PERF_PAPC_SU_SE0_STALLED_SC              = 0x00000083,
20215  PERF_PAPC_SU_SE1_STALLED_SC              = 0x00000084,
20216  PERF_PAPC_SU_SE01_STALLED_SC             = 0x00000085,
20217  PERF_PAPC_CLSM_CLIPPING_PRIM             = 0x00000086,
20218  PERF_PAPC_SU_CULLED_PRIM                 = 0x00000087,
20219  PERF_PAPC_SU_OUTPUT_EOPG                 = 0x00000088,
20220  PERF_PAPC_SU_SE2_PRIM_FILTER_CULL        = 0x00000089,
20221  PERF_PAPC_SU_SE3_PRIM_FILTER_CULL        = 0x0000008a,
20222  PERF_PAPC_SU_SE2_OUTPUT_PRIM             = 0x0000008b,
20223  PERF_PAPC_SU_SE3_OUTPUT_PRIM             = 0x0000008c,
20224  PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM        = 0x0000008d,
20225  PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM        = 0x0000008e,
20226  PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET    = 0x0000008f,
20227  PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET    = 0x00000090,
20228  PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET    = 0x00000091,
20229  PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET    = 0x00000092,
20230  PERF_PAPC_SU_SE0_OUTPUT_EOPG             = 0x00000093,
20231  PERF_PAPC_SU_SE1_OUTPUT_EOPG             = 0x00000094,
20232  PERF_PAPC_SU_SE2_OUTPUT_EOPG             = 0x00000095,
20233  PERF_PAPC_SU_SE3_OUTPUT_EOPG             = 0x00000096,
20234  PERF_PAPC_SU_SE2_STALLED_SC              = 0x00000097,
20235  PERF_PAPC_SU_SE3_STALLED_SC              = 0x00000098,
20236  PERF_SU_SMALL_PRIM_FILTER_CULL_CNT       = 0x00000099,
20237  PERF_SMALL_PRIM_CULL_PRIM_1X1            = 0x0000009a,
20238  PERF_SMALL_PRIM_CULL_PRIM_2X1            = 0x0000009b,
20239  PERF_SMALL_PRIM_CULL_PRIM_1X2            = 0x0000009c,
20240  PERF_SMALL_PRIM_CULL_PRIM_2X2            = 0x0000009d,
20241  PERF_SMALL_PRIM_CULL_PRIM_3X1            = 0x0000009e,
20242  PERF_SMALL_PRIM_CULL_PRIM_1X3            = 0x0000009f,
20243  PERF_SMALL_PRIM_CULL_PRIM_3X2            = 0x000000a0,
20244  PERF_SMALL_PRIM_CULL_PRIM_2X3            = 0x000000a1,
20245  PERF_SMALL_PRIM_CULL_PRIM_NX1            = 0x000000a2,
20246  PERF_SMALL_PRIM_CULL_PRIM_1XN            = 0x000000a3,
20247  PERF_SMALL_PRIM_CULL_PRIM_NX2            = 0x000000a4,
20248  PERF_SMALL_PRIM_CULL_PRIM_2XN            = 0x000000a5,
20249  PERF_SMALL_PRIM_CULL_PRIM_FULL_RES_EVENT = 0x000000a6,
20250  PERF_SMALL_PRIM_CULL_PRIM_HALF_RES_EVENT = 0x000000a7,
20251  PERF_SMALL_PRIM_CULL_PRIM_QUARTER_RES_EVENT = 0x000000a8,
20252  PERF_SC0_QUALIFIED_SEND_BUSY_EVENT       = 0x000000aa,
20253  PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT   = 0x000000ab,
20254  PERF_SC1_QUALIFIED_SEND_BUSY_EVENT       = 0x000000ac,
20255  PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT   = 0x000000ad,
20256  PERF_SC2_QUALIFIED_SEND_BUSY_EVENT       = 0x000000ae,
20257  PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT   = 0x000000af,
20258  PERF_SC3_QUALIFIED_SEND_BUSY_EVENT       = 0x000000b0,
20259  PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT   = 0x000000b1,
20260  PERF_PA_VERTEX_FIFO_FULL                 = 0x000000b3,
20261  PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL       = 0x000000b4,
20262  PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL      = 0x000000b6,
20263  PERF_PA_FETCH_TO_SXIF_FIFO_FULL          = 0x000000b7,
20264  PERF_PA_PIPE0_SWITCHED_GEN               = 0x000000b9,
20265  PERF_PA_PIPE1_SWITCHED_GEN               = 0x000000ba,
20266  PERF_ENGG_CSB_MACHINE_IS_STARVED         = 0x000000bc,
20267  PERF_ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY = 0x000000bd,
20268  PERF_ENGG_CSB_MACHINE_STALLED_BY_SPI     = 0x000000be,
20269  PERF_ENGG_CSB_GE_INPUT_FIFO_FULL         = 0x000000bf,
20270  PERF_ENGG_CSB_SPI_INPUT_FIFO_FULL        = 0x000000c0,
20271  PERF_ENGG_CSB_PAYLOAD_INPUT_FIFO_FULL    = 0x000000c1,
20272  PERF_ENGG_CSB_GE_INPUT_FIFO_POP_BIT      = 0x000000c2,
20273  PERF_ENGG_CSB_PRIM_COUNT_EQ0             = 0x000000c3,
20274  PERF_ENGG_CSB_NULL_SUBGROUP              = 0x000000c4,
20275  PERF_ENGG_CSB_GE_SENDING_SUBGROUP        = 0x000000c5,
20276  PERF_ENGG_CSB_GE_MEMORY_FULL             = 0x000000c6,
20277  PERF_ENGG_CSB_GE_MEMORY_EMPTY            = 0x000000c7,
20278  PERF_ENGG_CSB_SPI_MEMORY_FULL            = 0x000000c8,
20279  PERF_ENGG_CSB_SPI_MEMORY_EMPTY           = 0x000000c9,
20280  PERF_ENGG_CSB_DELAY_BIN00                = 0x000000ca,
20281  PERF_ENGG_CSB_DELAY_BIN01                = 0x000000cb,
20282  PERF_ENGG_CSB_DELAY_BIN02                = 0x000000cc,
20283  PERF_ENGG_CSB_DELAY_BIN03                = 0x000000cd,
20284  PERF_ENGG_CSB_DELAY_BIN04                = 0x000000ce,
20285  PERF_ENGG_CSB_DELAY_BIN05                = 0x000000cf,
20286  PERF_ENGG_CSB_DELAY_BIN06                = 0x000000d0,
20287  PERF_ENGG_CSB_DELAY_BIN07                = 0x000000d1,
20288  PERF_ENGG_CSB_DELAY_BIN08                = 0x000000d2,
20289  PERF_ENGG_CSB_DELAY_BIN09                = 0x000000d3,
20290  PERF_ENGG_CSB_DELAY_BIN10                = 0x000000d4,
20291  PERF_ENGG_CSB_DELAY_BIN11                = 0x000000d5,
20292  PERF_ENGG_CSB_DELAY_BIN12                = 0x000000d6,
20293  PERF_ENGG_CSB_DELAY_BIN13                = 0x000000d7,
20294  PERF_ENGG_CSB_DELAY_BIN14                = 0x000000d8,
20295  PERF_ENGG_CSB_DELAY_BIN15                = 0x000000d9,
20296  PERF_ENGG_CSB_SPI_DELAY_BIN00            = 0x000000da,
20297  PERF_ENGG_CSB_SPI_DELAY_BIN01            = 0x000000db,
20298  PERF_ENGG_CSB_SPI_DELAY_BIN02            = 0x000000dc,
20299  PERF_ENGG_CSB_SPI_DELAY_BIN03            = 0x000000dd,
20300  PERF_ENGG_CSB_SPI_DELAY_BIN04            = 0x000000de,
20301  PERF_ENGG_CSB_SPI_DELAY_BIN05            = 0x000000df,
20302  PERF_ENGG_CSB_SPI_DELAY_BIN06            = 0x000000e0,
20303  PERF_ENGG_CSB_SPI_DELAY_BIN07            = 0x000000e1,
20304  PERF_ENGG_CSB_SPI_DELAY_BIN08            = 0x000000e2,
20305  PERF_ENGG_CSB_SPI_DELAY_BIN09            = 0x000000e3,
20306  PERF_ENGG_CSB_SPI_DELAY_BIN10            = 0x000000e4,
20307  PERF_ENGG_INDEX_REQ_NULL_REQUEST         = 0x000000e5,
20308  PERF_ENGG_INDEX_REQ_0_NEW_VERTS_THIS_PRIM = 0x000000e6,
20309  PERF_ENGG_INDEX_REQ_1_NEW_VERTS_THIS_PRIM = 0x000000e7,
20310  PERF_ENGG_INDEX_REQ_2_NEW_VERTS_THIS_PRIM = 0x000000e8,
20311  PERF_ENGG_INDEX_REQ_3_NEW_VERTS_THIS_PRIM = 0x000000e9,
20312  PERF_ENGG_INDEX_REQ_STARVED              = 0x000000ea,
20313  PERF_ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 0x000000eb,
20314  PERF_ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 0x000000ec,
20315  PERF_ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS = 0x000000ed,
20316  PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_FULL    = 0x000000ee,
20317  PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY   = 0x000000ef,
20318  PERF_ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL = 0x000000f0,
20319  PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_CSB  = 0x000000f1,
20320  PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS = 0x000000f2,
20321  PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO = 0x000000f3,
20322  PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO = 0x000000f4,
20323  PERF_ENGG_INDEX_RET_SXRX_READING_EVENT   = 0x000000f5,
20324  PERF_ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP = 0x000000f6,
20325  PERF_ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0 = 0x000000f7,
20326  PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL = 0x000000f8,
20327  PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL = 0x000000f9,
20328  PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_NOPL = 0x000000fa,
20329  PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_NOPL = 0x000000fb,
20330  PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_NOPL = 0x000000fc,
20331  PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL = 0x000000fd,
20332  PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL = 0x000000fe,
20333  PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_PL = 0x000000ff,
20334  PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_PL = 0x00000100,
20335  PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_PL = 0x00000101,
20336  PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_NULL_PRIMS = 0x00000102,
20337  PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_NULL_PRIMS = 0x00000103,
20338  PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_NULL_PRIMS = 0x00000104,
20339  PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_NULL_PRIMS = 0x00000105,
20340  PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_NULL_PRIMS = 0x00000106,
20341  PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO = 0x00000107,
20342  PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO = 0x00000108,
20343  PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_CSB = 0x00000109,
20344  PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM = 0x0000010a,
20345  PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE = 0x0000010b,
20346  PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE = 0x0000010c,
20347  PERF_ENGG_POS_REQ_STARVED                = 0x0000010d,
20348  PERF_ENGG_INDEX_RET_SXRX_NULL_DROPPER_STALLED_BY_FULL_PRIM_FIFO = 0x0000010e,
20349  PERF_ENGG_BUSY                           = 0x0000010f,
20350  PERF_CLIPSM_CULL_PRIMS_CNT               = 0x00000110,
20351  PERF_PH_SEND_1_SC                        = 0x00000111,
20352  PERF_PH_SEND_2_SC                        = 0x00000112,
20353  PERF_PH_SEND_3_SC                        = 0x00000113,
20354  PERF_PH_SEND_4_SC                        = 0x00000114,
20355  PERF_OUTPUT_PRIM_1_SC                    = 0x00000115,
20356  PERF_OUTPUT_PRIM_2_SC                    = 0x00000116,
20357  PERF_OUTPUT_PRIM_3_SC                    = 0x00000117,
20358  PERF_OUTPUT_PRIM_4_SC                    = 0x00000118,
20359  } SU_PERFCNT_SEL;
20360  
20361  /*******************************************************
20362   * PH Enums
20363   *******************************************************/
20364  
20365  /*
20366   * PH_PERFCNT_SEL enum
20367   */
20368  
20369  typedef enum PH_PERFCNT_SEL {
20370  PH_PERF_SEL_SC0_SRPS_WINDOW_VALID        = 0x00000000,
20371  PH_PERF_SEL_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000001,
20372  PH_PERF_SEL_SC0_ARB_XFC_ONLY_PRIM_CYCLES = 0x00000002,
20373  PH_PERF_SEL_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x00000003,
20374  PH_PERF_SEL_SC0_ARB_STALLED_FROM_BELOW   = 0x00000004,
20375  PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE   = 0x00000005,
20376  PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x00000006,
20377  PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x00000007,
20378  PH_PERF_SEL_SC0_ARB_BUSY                 = 0x00000008,
20379  PH_PERF_SEL_SC0_ARB_PA_BUSY_SOP          = 0x00000009,
20380  PH_PERF_SEL_SC0_ARB_EOP_POP_SYNC_POP     = 0x0000000a,
20381  PH_PERF_SEL_SC0_ARB_EVENT_SYNC_POP       = 0x0000000b,
20382  PH_PERF_SEL_SC0_PS_ENG_MULTICYCLE_BUBBLE = 0x0000000c,
20383  PH_PERF_SEL_SC0_EOP_SYNC_WINDOW          = 0x0000000d,
20384  PH_PERF_SEL_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x0000000e,
20385  PH_PERF_SEL_SC0_BUSY_CNT_NOT_ZERO        = 0x0000000f,
20386  PH_PERF_SEL_SC0_SEND                     = 0x00000010,
20387  PH_PERF_SEL_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000011,
20388  PH_PERF_SEL_SC0_CREDIT_AT_MAX            = 0x00000012,
20389  PH_PERF_SEL_SC0_CREDIT_AT_MAX_NO_PENDING_SEND = 0x00000013,
20390  PH_PERF_SEL_SC0_GFX_PIPE0_TO_1_TRANSITION = 0x00000014,
20391  PH_PERF_SEL_SC0_GFX_PIPE1_TO_0_TRANSITION = 0x00000015,
20392  PH_PERF_SEL_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION = 0x00000016,
20393  PH_PERF_SEL_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x00000017,
20394  PH_PERF_SEL_SC0_PA0_DATA_FIFO_RD         = 0x00000018,
20395  PH_PERF_SEL_SC0_PA0_DATA_FIFO_WE         = 0x00000019,
20396  PH_PERF_SEL_SC0_PA0_FIFO_EMPTY           = 0x0000001a,
20397  PH_PERF_SEL_SC0_PA0_FIFO_FULL            = 0x0000001b,
20398  PH_PERF_SEL_SC0_PA0_NULL_WE              = 0x0000001c,
20399  PH_PERF_SEL_SC0_PA0_EVENT_WE             = 0x0000001d,
20400  PH_PERF_SEL_SC0_PA0_FPOV_WE              = 0x0000001e,
20401  PH_PERF_SEL_SC0_PA0_LPOV_WE              = 0x0000001f,
20402  PH_PERF_SEL_SC0_PA0_EOP_WE               = 0x00000020,
20403  PH_PERF_SEL_SC0_PA0_DATA_FIFO_EOP_RD     = 0x00000021,
20404  PH_PERF_SEL_SC0_PA0_EOPG_WE              = 0x00000022,
20405  PH_PERF_SEL_SC0_PA0_DEALLOC_4_0_RD       = 0x00000023,
20406  PH_PERF_SEL_SC0_PA1_DATA_FIFO_RD         = 0x00000024,
20407  PH_PERF_SEL_SC0_PA1_DATA_FIFO_WE         = 0x00000025,
20408  PH_PERF_SEL_SC0_PA1_FIFO_EMPTY           = 0x00000026,
20409  PH_PERF_SEL_SC0_PA1_FIFO_FULL            = 0x00000027,
20410  PH_PERF_SEL_SC0_PA1_NULL_WE              = 0x00000028,
20411  PH_PERF_SEL_SC0_PA1_EVENT_WE             = 0x00000029,
20412  PH_PERF_SEL_SC0_PA1_FPOV_WE              = 0x0000002a,
20413  PH_PERF_SEL_SC0_PA1_LPOV_WE              = 0x0000002b,
20414  PH_PERF_SEL_SC0_PA1_EOP_WE               = 0x0000002c,
20415  PH_PERF_SEL_SC0_PA1_DATA_FIFO_EOP_RD     = 0x0000002d,
20416  PH_PERF_SEL_SC0_PA1_EOPG_WE              = 0x0000002e,
20417  PH_PERF_SEL_SC0_PA1_DEALLOC_4_0_RD       = 0x0000002f,
20418  PH_PERF_SEL_SC0_PA2_DATA_FIFO_RD         = 0x00000030,
20419  PH_PERF_SEL_SC0_PA2_DATA_FIFO_WE         = 0x00000031,
20420  PH_PERF_SEL_SC0_PA2_FIFO_EMPTY           = 0x00000032,
20421  PH_PERF_SEL_SC0_PA2_FIFO_FULL            = 0x00000033,
20422  PH_PERF_SEL_SC0_PA2_NULL_WE              = 0x00000034,
20423  PH_PERF_SEL_SC0_PA2_EVENT_WE             = 0x00000035,
20424  PH_PERF_SEL_SC0_PA2_FPOV_WE              = 0x00000036,
20425  PH_PERF_SEL_SC0_PA2_LPOV_WE              = 0x00000037,
20426  PH_PERF_SEL_SC0_PA2_EOP_WE               = 0x00000038,
20427  PH_PERF_SEL_SC0_PA2_DATA_FIFO_EOP_RD     = 0x00000039,
20428  PH_PERF_SEL_SC0_PA2_EOPG_WE              = 0x0000003a,
20429  PH_PERF_SEL_SC0_PA2_DEALLOC_4_0_RD       = 0x0000003b,
20430  PH_PERF_SEL_SC0_PA3_DATA_FIFO_RD         = 0x0000003c,
20431  PH_PERF_SEL_SC0_PA3_DATA_FIFO_WE         = 0x0000003d,
20432  PH_PERF_SEL_SC0_PA3_FIFO_EMPTY           = 0x0000003e,
20433  PH_PERF_SEL_SC0_PA3_FIFO_FULL            = 0x0000003f,
20434  PH_PERF_SEL_SC0_PA3_NULL_WE              = 0x00000040,
20435  PH_PERF_SEL_SC0_PA3_EVENT_WE             = 0x00000041,
20436  PH_PERF_SEL_SC0_PA3_FPOV_WE              = 0x00000042,
20437  PH_PERF_SEL_SC0_PA3_LPOV_WE              = 0x00000043,
20438  PH_PERF_SEL_SC0_PA3_EOP_WE               = 0x00000044,
20439  PH_PERF_SEL_SC0_PA3_DATA_FIFO_EOP_RD     = 0x00000045,
20440  PH_PERF_SEL_SC0_PA3_EOPG_WE              = 0x00000046,
20441  PH_PERF_SEL_SC0_PA3_DEALLOC_4_0_RD       = 0x00000047,
20442  PH_PERF_SEL_SC0_PA4_DATA_FIFO_RD         = 0x00000048,
20443  PH_PERF_SEL_SC0_PA4_DATA_FIFO_WE         = 0x00000049,
20444  PH_PERF_SEL_SC0_PA4_FIFO_EMPTY           = 0x0000004a,
20445  PH_PERF_SEL_SC0_PA4_FIFO_FULL            = 0x0000004b,
20446  PH_PERF_SEL_SC0_PA4_NULL_WE              = 0x0000004c,
20447  PH_PERF_SEL_SC0_PA4_EVENT_WE             = 0x0000004d,
20448  PH_PERF_SEL_SC0_PA4_FPOV_WE              = 0x0000004e,
20449  PH_PERF_SEL_SC0_PA4_LPOV_WE              = 0x0000004f,
20450  PH_PERF_SEL_SC0_PA4_EOP_WE               = 0x00000050,
20451  PH_PERF_SEL_SC0_PA4_DATA_FIFO_EOP_RD     = 0x00000051,
20452  PH_PERF_SEL_SC0_PA4_EOPG_WE              = 0x00000052,
20453  PH_PERF_SEL_SC0_PA4_DEALLOC_4_0_RD       = 0x00000053,
20454  PH_PERF_SEL_SC0_PA5_DATA_FIFO_RD         = 0x00000054,
20455  PH_PERF_SEL_SC0_PA5_DATA_FIFO_WE         = 0x00000055,
20456  PH_PERF_SEL_SC0_PA5_FIFO_EMPTY           = 0x00000056,
20457  PH_PERF_SEL_SC0_PA5_FIFO_FULL            = 0x00000057,
20458  PH_PERF_SEL_SC0_PA5_NULL_WE              = 0x00000058,
20459  PH_PERF_SEL_SC0_PA5_EVENT_WE             = 0x00000059,
20460  PH_PERF_SEL_SC0_PA5_FPOV_WE              = 0x0000005a,
20461  PH_PERF_SEL_SC0_PA5_LPOV_WE              = 0x0000005b,
20462  PH_PERF_SEL_SC0_PA5_EOP_WE               = 0x0000005c,
20463  PH_PERF_SEL_SC0_PA5_DATA_FIFO_EOP_RD     = 0x0000005d,
20464  PH_PERF_SEL_SC0_PA5_EOPG_WE              = 0x0000005e,
20465  PH_PERF_SEL_SC0_PA5_DEALLOC_4_0_RD       = 0x0000005f,
20466  PH_PERF_SEL_SC0_PA6_DATA_FIFO_RD         = 0x00000060,
20467  PH_PERF_SEL_SC0_PA6_DATA_FIFO_WE         = 0x00000061,
20468  PH_PERF_SEL_SC0_PA6_FIFO_EMPTY           = 0x00000062,
20469  PH_PERF_SEL_SC0_PA6_FIFO_FULL            = 0x00000063,
20470  PH_PERF_SEL_SC0_PA6_NULL_WE              = 0x00000064,
20471  PH_PERF_SEL_SC0_PA6_EVENT_WE             = 0x00000065,
20472  PH_PERF_SEL_SC0_PA6_FPOV_WE              = 0x00000066,
20473  PH_PERF_SEL_SC0_PA6_LPOV_WE              = 0x00000067,
20474  PH_PERF_SEL_SC0_PA6_EOP_WE               = 0x00000068,
20475  PH_PERF_SEL_SC0_PA6_DATA_FIFO_EOP_RD     = 0x00000069,
20476  PH_PERF_SEL_SC0_PA6_EOPG_WE              = 0x0000006a,
20477  PH_PERF_SEL_SC0_PA6_DEALLOC_4_0_RD       = 0x0000006b,
20478  PH_PERF_SEL_SC0_PA7_DATA_FIFO_RD         = 0x0000006c,
20479  PH_PERF_SEL_SC0_PA7_DATA_FIFO_WE         = 0x0000006d,
20480  PH_PERF_SEL_SC0_PA7_FIFO_EMPTY           = 0x0000006e,
20481  PH_PERF_SEL_SC0_PA7_FIFO_FULL            = 0x0000006f,
20482  PH_PERF_SEL_SC0_PA7_NULL_WE              = 0x00000070,
20483  PH_PERF_SEL_SC0_PA7_EVENT_WE             = 0x00000071,
20484  PH_PERF_SEL_SC0_PA7_FPOV_WE              = 0x00000072,
20485  PH_PERF_SEL_SC0_PA7_LPOV_WE              = 0x00000073,
20486  PH_PERF_SEL_SC0_PA7_EOP_WE               = 0x00000074,
20487  PH_PERF_SEL_SC0_PA7_DATA_FIFO_EOP_RD     = 0x00000075,
20488  PH_PERF_SEL_SC0_PA7_EOPG_WE              = 0x00000076,
20489  PH_PERF_SEL_SC0_PA7_DEALLOC_4_0_RD       = 0x00000077,
20490  PH_PERF_SEL_SC1_SRPS_WINDOW_VALID        = 0x00000078,
20491  PH_PERF_SEL_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000079,
20492  PH_PERF_SEL_SC1_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000007a,
20493  PH_PERF_SEL_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000007b,
20494  PH_PERF_SEL_SC1_ARB_STALLED_FROM_BELOW   = 0x0000007c,
20495  PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE   = 0x0000007d,
20496  PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x0000007e,
20497  PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x0000007f,
20498  PH_PERF_SEL_SC1_ARB_BUSY                 = 0x00000080,
20499  PH_PERF_SEL_SC1_ARB_PA_BUSY_SOP          = 0x00000081,
20500  PH_PERF_SEL_SC1_ARB_EOP_POP_SYNC_POP     = 0x00000082,
20501  PH_PERF_SEL_SC1_ARB_EVENT_SYNC_POP       = 0x00000083,
20502  PH_PERF_SEL_SC1_PS_ENG_MULTICYCLE_BUBBLE = 0x00000084,
20503  PH_PERF_SEL_SC1_EOP_SYNC_WINDOW          = 0x00000085,
20504  PH_PERF_SEL_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000086,
20505  PH_PERF_SEL_SC1_BUSY_CNT_NOT_ZERO        = 0x00000087,
20506  PH_PERF_SEL_SC1_SEND                     = 0x00000088,
20507  PH_PERF_SEL_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000089,
20508  PH_PERF_SEL_SC1_CREDIT_AT_MAX            = 0x0000008a,
20509  PH_PERF_SEL_SC1_CREDIT_AT_MAX_NO_PENDING_SEND = 0x0000008b,
20510  PH_PERF_SEL_SC1_GFX_PIPE0_TO_1_TRANSITION = 0x0000008c,
20511  PH_PERF_SEL_SC1_GFX_PIPE1_TO_0_TRANSITION = 0x0000008d,
20512  PH_PERF_SEL_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x0000008e,
20513  PH_PERF_SEL_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x0000008f,
20514  PH_PERF_SEL_SC1_PA0_DATA_FIFO_RD         = 0x00000090,
20515  PH_PERF_SEL_SC1_PA0_DATA_FIFO_WE         = 0x00000091,
20516  PH_PERF_SEL_SC1_PA0_FIFO_EMPTY           = 0x00000092,
20517  PH_PERF_SEL_SC1_PA0_FIFO_FULL            = 0x00000093,
20518  PH_PERF_SEL_SC1_PA0_NULL_WE              = 0x00000094,
20519  PH_PERF_SEL_SC1_PA0_EVENT_WE             = 0x00000095,
20520  PH_PERF_SEL_SC1_PA0_FPOV_WE              = 0x00000096,
20521  PH_PERF_SEL_SC1_PA0_LPOV_WE              = 0x00000097,
20522  PH_PERF_SEL_SC1_PA0_EOP_WE               = 0x00000098,
20523  PH_PERF_SEL_SC1_PA0_DATA_FIFO_EOP_RD     = 0x00000099,
20524  PH_PERF_SEL_SC1_PA0_EOPG_WE              = 0x0000009a,
20525  PH_PERF_SEL_SC1_PA0_DEALLOC_4_0_RD       = 0x0000009b,
20526  PH_PERF_SEL_SC1_PA1_DATA_FIFO_RD         = 0x0000009c,
20527  PH_PERF_SEL_SC1_PA1_DATA_FIFO_WE         = 0x0000009d,
20528  PH_PERF_SEL_SC1_PA1_FIFO_EMPTY           = 0x0000009e,
20529  PH_PERF_SEL_SC1_PA1_FIFO_FULL            = 0x0000009f,
20530  PH_PERF_SEL_SC1_PA1_NULL_WE              = 0x000000a0,
20531  PH_PERF_SEL_SC1_PA1_EVENT_WE             = 0x000000a1,
20532  PH_PERF_SEL_SC1_PA1_FPOV_WE              = 0x000000a2,
20533  PH_PERF_SEL_SC1_PA1_LPOV_WE              = 0x000000a3,
20534  PH_PERF_SEL_SC1_PA1_EOP_WE               = 0x000000a4,
20535  PH_PERF_SEL_SC1_PA1_DATA_FIFO_EOP_RD     = 0x000000a5,
20536  PH_PERF_SEL_SC1_PA1_EOPG_WE              = 0x000000a6,
20537  PH_PERF_SEL_SC1_PA1_DEALLOC_4_0_RD       = 0x000000a7,
20538  PH_PERF_SEL_SC1_PA2_DATA_FIFO_RD         = 0x000000a8,
20539  PH_PERF_SEL_SC1_PA2_DATA_FIFO_WE         = 0x000000a9,
20540  PH_PERF_SEL_SC1_PA2_FIFO_EMPTY           = 0x000000aa,
20541  PH_PERF_SEL_SC1_PA2_FIFO_FULL            = 0x000000ab,
20542  PH_PERF_SEL_SC1_PA2_NULL_WE              = 0x000000ac,
20543  PH_PERF_SEL_SC1_PA2_EVENT_WE             = 0x000000ad,
20544  PH_PERF_SEL_SC1_PA2_FPOV_WE              = 0x000000ae,
20545  PH_PERF_SEL_SC1_PA2_LPOV_WE              = 0x000000af,
20546  PH_PERF_SEL_SC1_PA2_EOP_WE               = 0x000000b0,
20547  PH_PERF_SEL_SC1_PA2_DATA_FIFO_EOP_RD     = 0x000000b1,
20548  PH_PERF_SEL_SC1_PA2_EOPG_WE              = 0x000000b2,
20549  PH_PERF_SEL_SC1_PA2_DEALLOC_4_0_RD       = 0x000000b3,
20550  PH_PERF_SEL_SC1_PA3_DATA_FIFO_RD         = 0x000000b4,
20551  PH_PERF_SEL_SC1_PA3_DATA_FIFO_WE         = 0x000000b5,
20552  PH_PERF_SEL_SC1_PA3_FIFO_EMPTY           = 0x000000b6,
20553  PH_PERF_SEL_SC1_PA3_FIFO_FULL            = 0x000000b7,
20554  PH_PERF_SEL_SC1_PA3_NULL_WE              = 0x000000b8,
20555  PH_PERF_SEL_SC1_PA3_EVENT_WE             = 0x000000b9,
20556  PH_PERF_SEL_SC1_PA3_FPOV_WE              = 0x000000ba,
20557  PH_PERF_SEL_SC1_PA3_LPOV_WE              = 0x000000bb,
20558  PH_PERF_SEL_SC1_PA3_EOP_WE               = 0x000000bc,
20559  PH_PERF_SEL_SC1_PA3_DATA_FIFO_EOP_RD     = 0x000000bd,
20560  PH_PERF_SEL_SC1_PA3_EOPG_WE              = 0x000000be,
20561  PH_PERF_SEL_SC1_PA3_DEALLOC_4_0_RD       = 0x000000bf,
20562  PH_PERF_SEL_SC1_PA4_DATA_FIFO_RD         = 0x000000c0,
20563  PH_PERF_SEL_SC1_PA4_DATA_FIFO_WE         = 0x000000c1,
20564  PH_PERF_SEL_SC1_PA4_FIFO_EMPTY           = 0x000000c2,
20565  PH_PERF_SEL_SC1_PA4_FIFO_FULL            = 0x000000c3,
20566  PH_PERF_SEL_SC1_PA4_NULL_WE              = 0x000000c4,
20567  PH_PERF_SEL_SC1_PA4_EVENT_WE             = 0x000000c5,
20568  PH_PERF_SEL_SC1_PA4_FPOV_WE              = 0x000000c6,
20569  PH_PERF_SEL_SC1_PA4_LPOV_WE              = 0x000000c7,
20570  PH_PERF_SEL_SC1_PA4_EOP_WE               = 0x000000c8,
20571  PH_PERF_SEL_SC1_PA4_DATA_FIFO_EOP_RD     = 0x000000c9,
20572  PH_PERF_SEL_SC1_PA4_EOPG_WE              = 0x000000ca,
20573  PH_PERF_SEL_SC1_PA4_DEALLOC_4_0_RD       = 0x000000cb,
20574  PH_PERF_SEL_SC1_PA5_DATA_FIFO_RD         = 0x000000cc,
20575  PH_PERF_SEL_SC1_PA5_DATA_FIFO_WE         = 0x000000cd,
20576  PH_PERF_SEL_SC1_PA5_FIFO_EMPTY           = 0x000000ce,
20577  PH_PERF_SEL_SC1_PA5_FIFO_FULL            = 0x000000cf,
20578  PH_PERF_SEL_SC1_PA5_NULL_WE              = 0x000000d0,
20579  PH_PERF_SEL_SC1_PA5_EVENT_WE             = 0x000000d1,
20580  PH_PERF_SEL_SC1_PA5_FPOV_WE              = 0x000000d2,
20581  PH_PERF_SEL_SC1_PA5_LPOV_WE              = 0x000000d3,
20582  PH_PERF_SEL_SC1_PA5_EOP_WE               = 0x000000d4,
20583  PH_PERF_SEL_SC1_PA5_DATA_FIFO_EOP_RD     = 0x000000d5,
20584  PH_PERF_SEL_SC1_PA5_EOPG_WE              = 0x000000d6,
20585  PH_PERF_SEL_SC1_PA5_DEALLOC_4_0_RD       = 0x000000d7,
20586  PH_PERF_SEL_SC1_PA6_DATA_FIFO_RD         = 0x000000d8,
20587  PH_PERF_SEL_SC1_PA6_DATA_FIFO_WE         = 0x000000d9,
20588  PH_PERF_SEL_SC1_PA6_FIFO_EMPTY           = 0x000000da,
20589  PH_PERF_SEL_SC1_PA6_FIFO_FULL            = 0x000000db,
20590  PH_PERF_SEL_SC1_PA6_NULL_WE              = 0x000000dc,
20591  PH_PERF_SEL_SC1_PA6_EVENT_WE             = 0x000000dd,
20592  PH_PERF_SEL_SC1_PA6_FPOV_WE              = 0x000000de,
20593  PH_PERF_SEL_SC1_PA6_LPOV_WE              = 0x000000df,
20594  PH_PERF_SEL_SC1_PA6_EOP_WE               = 0x000000e0,
20595  PH_PERF_SEL_SC1_PA6_DATA_FIFO_EOP_RD     = 0x000000e1,
20596  PH_PERF_SEL_SC1_PA6_EOPG_WE              = 0x000000e2,
20597  PH_PERF_SEL_SC1_PA6_DEALLOC_4_0_RD       = 0x000000e3,
20598  PH_PERF_SEL_SC1_PA7_DATA_FIFO_RD         = 0x000000e4,
20599  PH_PERF_SEL_SC1_PA7_DATA_FIFO_WE         = 0x000000e5,
20600  PH_PERF_SEL_SC1_PA7_FIFO_EMPTY           = 0x000000e6,
20601  PH_PERF_SEL_SC1_PA7_FIFO_FULL            = 0x000000e7,
20602  PH_PERF_SEL_SC1_PA7_NULL_WE              = 0x000000e8,
20603  PH_PERF_SEL_SC1_PA7_EVENT_WE             = 0x000000e9,
20604  PH_PERF_SEL_SC1_PA7_FPOV_WE              = 0x000000ea,
20605  PH_PERF_SEL_SC1_PA7_LPOV_WE              = 0x000000eb,
20606  PH_PERF_SEL_SC1_PA7_EOP_WE               = 0x000000ec,
20607  PH_PERF_SEL_SC1_PA7_DATA_FIFO_EOP_RD     = 0x000000ed,
20608  PH_PERF_SEL_SC1_PA7_EOPG_WE              = 0x000000ee,
20609  PH_PERF_SEL_SC1_PA7_DEALLOC_4_0_RD       = 0x000000ef,
20610  PH_PERF_SEL_SC2_SRPS_WINDOW_VALID        = 0x000000f0,
20611  PH_PERF_SEL_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x000000f1,
20612  PH_PERF_SEL_SC2_ARB_XFC_ONLY_PRIM_CYCLES = 0x000000f2,
20613  PH_PERF_SEL_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x000000f3,
20614  PH_PERF_SEL_SC2_ARB_STALLED_FROM_BELOW   = 0x000000f4,
20615  PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE   = 0x000000f5,
20616  PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000000f6,
20617  PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000000f7,
20618  PH_PERF_SEL_SC2_ARB_BUSY                 = 0x000000f8,
20619  PH_PERF_SEL_SC2_ARB_PA_BUSY_SOP          = 0x000000f9,
20620  PH_PERF_SEL_SC2_ARB_EOP_POP_SYNC_POP     = 0x000000fa,
20621  PH_PERF_SEL_SC2_ARB_EVENT_SYNC_POP       = 0x000000fb,
20622  PH_PERF_SEL_SC2_PS_ENG_MULTICYCLE_BUBBLE = 0x000000fc,
20623  PH_PERF_SEL_SC2_EOP_SYNC_WINDOW          = 0x000000fd,
20624  PH_PERF_SEL_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x000000fe,
20625  PH_PERF_SEL_SC2_BUSY_CNT_NOT_ZERO        = 0x000000ff,
20626  PH_PERF_SEL_SC2_SEND                     = 0x00000100,
20627  PH_PERF_SEL_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000101,
20628  PH_PERF_SEL_SC2_CREDIT_AT_MAX            = 0x00000102,
20629  PH_PERF_SEL_SC2_CREDIT_AT_MAX_NO_PENDING_SEND = 0x00000103,
20630  PH_PERF_SEL_SC2_GFX_PIPE0_TO_1_TRANSITION = 0x00000104,
20631  PH_PERF_SEL_SC2_GFX_PIPE1_TO_0_TRANSITION = 0x00000105,
20632  PH_PERF_SEL_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x00000106,
20633  PH_PERF_SEL_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x00000107,
20634  PH_PERF_SEL_SC2_PA0_DATA_FIFO_RD         = 0x00000108,
20635  PH_PERF_SEL_SC2_PA0_DATA_FIFO_WE         = 0x00000109,
20636  PH_PERF_SEL_SC2_PA0_FIFO_EMPTY           = 0x0000010a,
20637  PH_PERF_SEL_SC2_PA0_FIFO_FULL            = 0x0000010b,
20638  PH_PERF_SEL_SC2_PA0_NULL_WE              = 0x0000010c,
20639  PH_PERF_SEL_SC2_PA0_EVENT_WE             = 0x0000010d,
20640  PH_PERF_SEL_SC2_PA0_FPOV_WE              = 0x0000010e,
20641  PH_PERF_SEL_SC2_PA0_LPOV_WE              = 0x0000010f,
20642  PH_PERF_SEL_SC2_PA0_EOP_WE               = 0x00000110,
20643  PH_PERF_SEL_SC2_PA0_DATA_FIFO_EOP_RD     = 0x00000111,
20644  PH_PERF_SEL_SC2_PA0_EOPG_WE              = 0x00000112,
20645  PH_PERF_SEL_SC2_PA0_DEALLOC_4_0_RD       = 0x00000113,
20646  PH_PERF_SEL_SC2_PA1_DATA_FIFO_RD         = 0x00000114,
20647  PH_PERF_SEL_SC2_PA1_DATA_FIFO_WE         = 0x00000115,
20648  PH_PERF_SEL_SC2_PA1_FIFO_EMPTY           = 0x00000116,
20649  PH_PERF_SEL_SC2_PA1_FIFO_FULL            = 0x00000117,
20650  PH_PERF_SEL_SC2_PA1_NULL_WE              = 0x00000118,
20651  PH_PERF_SEL_SC2_PA1_EVENT_WE             = 0x00000119,
20652  PH_PERF_SEL_SC2_PA1_FPOV_WE              = 0x0000011a,
20653  PH_PERF_SEL_SC2_PA1_LPOV_WE              = 0x0000011b,
20654  PH_PERF_SEL_SC2_PA1_EOP_WE               = 0x0000011c,
20655  PH_PERF_SEL_SC2_PA1_DATA_FIFO_EOP_RD     = 0x0000011d,
20656  PH_PERF_SEL_SC2_PA1_EOPG_WE              = 0x0000011e,
20657  PH_PERF_SEL_SC2_PA1_DEALLOC_4_0_RD       = 0x0000011f,
20658  PH_PERF_SEL_SC2_PA2_DATA_FIFO_RD         = 0x00000120,
20659  PH_PERF_SEL_SC2_PA2_DATA_FIFO_WE         = 0x00000121,
20660  PH_PERF_SEL_SC2_PA2_FIFO_EMPTY           = 0x00000122,
20661  PH_PERF_SEL_SC2_PA2_FIFO_FULL            = 0x00000123,
20662  PH_PERF_SEL_SC2_PA2_NULL_WE              = 0x00000124,
20663  PH_PERF_SEL_SC2_PA2_EVENT_WE             = 0x00000125,
20664  PH_PERF_SEL_SC2_PA2_FPOV_WE              = 0x00000126,
20665  PH_PERF_SEL_SC2_PA2_LPOV_WE              = 0x00000127,
20666  PH_PERF_SEL_SC2_PA2_EOP_WE               = 0x00000128,
20667  PH_PERF_SEL_SC2_PA2_DATA_FIFO_EOP_RD     = 0x00000129,
20668  PH_PERF_SEL_SC2_PA2_EOPG_WE              = 0x0000012a,
20669  PH_PERF_SEL_SC2_PA2_DEALLOC_4_0_RD       = 0x0000012b,
20670  PH_PERF_SEL_SC2_PA3_DATA_FIFO_RD         = 0x0000012c,
20671  PH_PERF_SEL_SC2_PA3_DATA_FIFO_WE         = 0x0000012d,
20672  PH_PERF_SEL_SC2_PA3_FIFO_EMPTY           = 0x0000012e,
20673  PH_PERF_SEL_SC2_PA3_FIFO_FULL            = 0x0000012f,
20674  PH_PERF_SEL_SC2_PA3_NULL_WE              = 0x00000130,
20675  PH_PERF_SEL_SC2_PA3_EVENT_WE             = 0x00000131,
20676  PH_PERF_SEL_SC2_PA3_FPOV_WE              = 0x00000132,
20677  PH_PERF_SEL_SC2_PA3_LPOV_WE              = 0x00000133,
20678  PH_PERF_SEL_SC2_PA3_EOP_WE               = 0x00000134,
20679  PH_PERF_SEL_SC2_PA3_DATA_FIFO_EOP_RD     = 0x00000135,
20680  PH_PERF_SEL_SC2_PA3_EOPG_WE              = 0x00000136,
20681  PH_PERF_SEL_SC2_PA3_DEALLOC_4_0_RD       = 0x00000137,
20682  PH_PERF_SEL_SC2_PA4_DATA_FIFO_RD         = 0x00000138,
20683  PH_PERF_SEL_SC2_PA4_DATA_FIFO_WE         = 0x00000139,
20684  PH_PERF_SEL_SC2_PA4_FIFO_EMPTY           = 0x0000013a,
20685  PH_PERF_SEL_SC2_PA4_FIFO_FULL            = 0x0000013b,
20686  PH_PERF_SEL_SC2_PA4_NULL_WE              = 0x0000013c,
20687  PH_PERF_SEL_SC2_PA4_EVENT_WE             = 0x0000013d,
20688  PH_PERF_SEL_SC2_PA4_FPOV_WE              = 0x0000013e,
20689  PH_PERF_SEL_SC2_PA4_LPOV_WE              = 0x0000013f,
20690  PH_PERF_SEL_SC2_PA4_EOP_WE               = 0x00000140,
20691  PH_PERF_SEL_SC2_PA4_DATA_FIFO_EOP_RD     = 0x00000141,
20692  PH_PERF_SEL_SC2_PA4_EOPG_WE              = 0x00000142,
20693  PH_PERF_SEL_SC2_PA4_DEALLOC_4_0_RD       = 0x00000143,
20694  PH_PERF_SEL_SC2_PA5_DATA_FIFO_RD         = 0x00000144,
20695  PH_PERF_SEL_SC2_PA5_DATA_FIFO_WE         = 0x00000145,
20696  PH_PERF_SEL_SC2_PA5_FIFO_EMPTY           = 0x00000146,
20697  PH_PERF_SEL_SC2_PA5_FIFO_FULL            = 0x00000147,
20698  PH_PERF_SEL_SC2_PA5_NULL_WE              = 0x00000148,
20699  PH_PERF_SEL_SC2_PA5_EVENT_WE             = 0x00000149,
20700  PH_PERF_SEL_SC2_PA5_FPOV_WE              = 0x0000014a,
20701  PH_PERF_SEL_SC2_PA5_LPOV_WE              = 0x0000014b,
20702  PH_PERF_SEL_SC2_PA5_EOP_WE               = 0x0000014c,
20703  PH_PERF_SEL_SC2_PA5_DATA_FIFO_EOP_RD     = 0x0000014d,
20704  PH_PERF_SEL_SC2_PA5_EOPG_WE              = 0x0000014e,
20705  PH_PERF_SEL_SC2_PA5_DEALLOC_4_0_RD       = 0x0000014f,
20706  PH_PERF_SEL_SC2_PA6_DATA_FIFO_RD         = 0x00000150,
20707  PH_PERF_SEL_SC2_PA6_DATA_FIFO_WE         = 0x00000151,
20708  PH_PERF_SEL_SC2_PA6_FIFO_EMPTY           = 0x00000152,
20709  PH_PERF_SEL_SC2_PA6_FIFO_FULL            = 0x00000153,
20710  PH_PERF_SEL_SC2_PA6_NULL_WE              = 0x00000154,
20711  PH_PERF_SEL_SC2_PA6_EVENT_WE             = 0x00000155,
20712  PH_PERF_SEL_SC2_PA6_FPOV_WE              = 0x00000156,
20713  PH_PERF_SEL_SC2_PA6_LPOV_WE              = 0x00000157,
20714  PH_PERF_SEL_SC2_PA6_EOP_WE               = 0x00000158,
20715  PH_PERF_SEL_SC2_PA6_DATA_FIFO_EOP_RD     = 0x00000159,
20716  PH_PERF_SEL_SC2_PA6_EOPG_WE              = 0x0000015a,
20717  PH_PERF_SEL_SC2_PA6_DEALLOC_4_0_RD       = 0x0000015b,
20718  PH_PERF_SEL_SC2_PA7_DATA_FIFO_RD         = 0x0000015c,
20719  PH_PERF_SEL_SC2_PA7_DATA_FIFO_WE         = 0x0000015d,
20720  PH_PERF_SEL_SC2_PA7_FIFO_EMPTY           = 0x0000015e,
20721  PH_PERF_SEL_SC2_PA7_FIFO_FULL            = 0x0000015f,
20722  PH_PERF_SEL_SC2_PA7_NULL_WE              = 0x00000160,
20723  PH_PERF_SEL_SC2_PA7_EVENT_WE             = 0x00000161,
20724  PH_PERF_SEL_SC2_PA7_FPOV_WE              = 0x00000162,
20725  PH_PERF_SEL_SC2_PA7_LPOV_WE              = 0x00000163,
20726  PH_PERF_SEL_SC2_PA7_EOP_WE               = 0x00000164,
20727  PH_PERF_SEL_SC2_PA7_DATA_FIFO_EOP_RD     = 0x00000165,
20728  PH_PERF_SEL_SC2_PA7_EOPG_WE              = 0x00000166,
20729  PH_PERF_SEL_SC2_PA7_DEALLOC_4_0_RD       = 0x00000167,
20730  PH_PERF_SEL_SC3_SRPS_WINDOW_VALID        = 0x00000168,
20731  PH_PERF_SEL_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000169,
20732  PH_PERF_SEL_SC3_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000016a,
20733  PH_PERF_SEL_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000016b,
20734  PH_PERF_SEL_SC3_ARB_STALLED_FROM_BELOW   = 0x0000016c,
20735  PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE   = 0x0000016d,
20736  PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x0000016e,
20737  PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x0000016f,
20738  PH_PERF_SEL_SC3_ARB_BUSY                 = 0x00000170,
20739  PH_PERF_SEL_SC3_ARB_PA_BUSY_SOP          = 0x00000171,
20740  PH_PERF_SEL_SC3_ARB_EOP_POP_SYNC_POP     = 0x00000172,
20741  PH_PERF_SEL_SC3_ARB_EVENT_SYNC_POP       = 0x00000173,
20742  PH_PERF_SEL_SC3_PS_ENG_MULTICYCLE_BUBBLE = 0x00000174,
20743  PH_PERF_SEL_SC3_EOP_SYNC_WINDOW          = 0x00000175,
20744  PH_PERF_SEL_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000176,
20745  PH_PERF_SEL_SC3_BUSY_CNT_NOT_ZERO        = 0x00000177,
20746  PH_PERF_SEL_SC3_SEND                     = 0x00000178,
20747  PH_PERF_SEL_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000179,
20748  PH_PERF_SEL_SC3_CREDIT_AT_MAX            = 0x0000017a,
20749  PH_PERF_SEL_SC3_CREDIT_AT_MAX_NO_PENDING_SEND = 0x0000017b,
20750  PH_PERF_SEL_SC3_GFX_PIPE0_TO_1_TRANSITION = 0x0000017c,
20751  PH_PERF_SEL_SC3_GFX_PIPE1_TO_0_TRANSITION = 0x0000017d,
20752  PH_PERF_SEL_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x0000017e,
20753  PH_PERF_SEL_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x0000017f,
20754  PH_PERF_SEL_SC3_PA0_DATA_FIFO_RD         = 0x00000180,
20755  PH_PERF_SEL_SC3_PA0_DATA_FIFO_WE         = 0x00000181,
20756  PH_PERF_SEL_SC3_PA0_FIFO_EMPTY           = 0x00000182,
20757  PH_PERF_SEL_SC3_PA0_FIFO_FULL            = 0x00000183,
20758  PH_PERF_SEL_SC3_PA0_NULL_WE              = 0x00000184,
20759  PH_PERF_SEL_SC3_PA0_EVENT_WE             = 0x00000185,
20760  PH_PERF_SEL_SC3_PA0_FPOV_WE              = 0x00000186,
20761  PH_PERF_SEL_SC3_PA0_LPOV_WE              = 0x00000187,
20762  PH_PERF_SEL_SC3_PA0_EOP_WE               = 0x00000188,
20763  PH_PERF_SEL_SC3_PA0_DATA_FIFO_EOP_RD     = 0x00000189,
20764  PH_PERF_SEL_SC3_PA0_EOPG_WE              = 0x0000018a,
20765  PH_PERF_SEL_SC3_PA0_DEALLOC_4_0_RD       = 0x0000018b,
20766  PH_PERF_SEL_SC3_PA1_DATA_FIFO_RD         = 0x0000018c,
20767  PH_PERF_SEL_SC3_PA1_DATA_FIFO_WE         = 0x0000018d,
20768  PH_PERF_SEL_SC3_PA1_FIFO_EMPTY           = 0x0000018e,
20769  PH_PERF_SEL_SC3_PA1_FIFO_FULL            = 0x0000018f,
20770  PH_PERF_SEL_SC3_PA1_NULL_WE              = 0x00000190,
20771  PH_PERF_SEL_SC3_PA1_EVENT_WE             = 0x00000191,
20772  PH_PERF_SEL_SC3_PA1_FPOV_WE              = 0x00000192,
20773  PH_PERF_SEL_SC3_PA1_LPOV_WE              = 0x00000193,
20774  PH_PERF_SEL_SC3_PA1_EOP_WE               = 0x00000194,
20775  PH_PERF_SEL_SC3_PA1_DATA_FIFO_EOP_RD     = 0x00000195,
20776  PH_PERF_SEL_SC3_PA1_EOPG_WE              = 0x00000196,
20777  PH_PERF_SEL_SC3_PA1_DEALLOC_4_0_RD       = 0x00000197,
20778  PH_PERF_SEL_SC3_PA2_DATA_FIFO_RD         = 0x00000198,
20779  PH_PERF_SEL_SC3_PA2_DATA_FIFO_WE         = 0x00000199,
20780  PH_PERF_SEL_SC3_PA2_FIFO_EMPTY           = 0x0000019a,
20781  PH_PERF_SEL_SC3_PA2_FIFO_FULL            = 0x0000019b,
20782  PH_PERF_SEL_SC3_PA2_NULL_WE              = 0x0000019c,
20783  PH_PERF_SEL_SC3_PA2_EVENT_WE             = 0x0000019d,
20784  PH_PERF_SEL_SC3_PA2_FPOV_WE              = 0x0000019e,
20785  PH_PERF_SEL_SC3_PA2_LPOV_WE              = 0x0000019f,
20786  PH_PERF_SEL_SC3_PA2_EOP_WE               = 0x000001a0,
20787  PH_PERF_SEL_SC3_PA2_DATA_FIFO_EOP_RD     = 0x000001a1,
20788  PH_PERF_SEL_SC3_PA2_EOPG_WE              = 0x000001a2,
20789  PH_PERF_SEL_SC3_PA2_DEALLOC_4_0_RD       = 0x000001a3,
20790  PH_PERF_SEL_SC3_PA3_DATA_FIFO_RD         = 0x000001a4,
20791  PH_PERF_SEL_SC3_PA3_DATA_FIFO_WE         = 0x000001a5,
20792  PH_PERF_SEL_SC3_PA3_FIFO_EMPTY           = 0x000001a6,
20793  PH_PERF_SEL_SC3_PA3_FIFO_FULL            = 0x000001a7,
20794  PH_PERF_SEL_SC3_PA3_NULL_WE              = 0x000001a8,
20795  PH_PERF_SEL_SC3_PA3_EVENT_WE             = 0x000001a9,
20796  PH_PERF_SEL_SC3_PA3_FPOV_WE              = 0x000001aa,
20797  PH_PERF_SEL_SC3_PA3_LPOV_WE              = 0x000001ab,
20798  PH_PERF_SEL_SC3_PA3_EOP_WE               = 0x000001ac,
20799  PH_PERF_SEL_SC3_PA3_DATA_FIFO_EOP_RD     = 0x000001ad,
20800  PH_PERF_SEL_SC3_PA3_EOPG_WE              = 0x000001ae,
20801  PH_PERF_SEL_SC3_PA3_DEALLOC_4_0_RD       = 0x000001af,
20802  PH_PERF_SEL_SC3_PA4_DATA_FIFO_RD         = 0x000001b0,
20803  PH_PERF_SEL_SC3_PA4_DATA_FIFO_WE         = 0x000001b1,
20804  PH_PERF_SEL_SC3_PA4_FIFO_EMPTY           = 0x000001b2,
20805  PH_PERF_SEL_SC3_PA4_FIFO_FULL            = 0x000001b3,
20806  PH_PERF_SEL_SC3_PA4_NULL_WE              = 0x000001b4,
20807  PH_PERF_SEL_SC3_PA4_EVENT_WE             = 0x000001b5,
20808  PH_PERF_SEL_SC3_PA4_FPOV_WE              = 0x000001b6,
20809  PH_PERF_SEL_SC3_PA4_LPOV_WE              = 0x000001b7,
20810  PH_PERF_SEL_SC3_PA4_EOP_WE               = 0x000001b8,
20811  PH_PERF_SEL_SC3_PA4_DATA_FIFO_EOP_RD     = 0x000001b9,
20812  PH_PERF_SEL_SC3_PA4_EOPG_WE              = 0x000001ba,
20813  PH_PERF_SEL_SC3_PA4_DEALLOC_4_0_RD       = 0x000001bb,
20814  PH_PERF_SEL_SC3_PA5_DATA_FIFO_RD         = 0x000001bc,
20815  PH_PERF_SEL_SC3_PA5_DATA_FIFO_WE         = 0x000001bd,
20816  PH_PERF_SEL_SC3_PA5_FIFO_EMPTY           = 0x000001be,
20817  PH_PERF_SEL_SC3_PA5_FIFO_FULL            = 0x000001bf,
20818  PH_PERF_SEL_SC3_PA5_NULL_WE              = 0x000001c0,
20819  PH_PERF_SEL_SC3_PA5_EVENT_WE             = 0x000001c1,
20820  PH_PERF_SEL_SC3_PA5_FPOV_WE              = 0x000001c2,
20821  PH_PERF_SEL_SC3_PA5_LPOV_WE              = 0x000001c3,
20822  PH_PERF_SEL_SC3_PA5_EOP_WE               = 0x000001c4,
20823  PH_PERF_SEL_SC3_PA5_DATA_FIFO_EOP_RD     = 0x000001c5,
20824  PH_PERF_SEL_SC3_PA5_EOPG_WE              = 0x000001c6,
20825  PH_PERF_SEL_SC3_PA5_DEALLOC_4_0_RD       = 0x000001c7,
20826  PH_PERF_SEL_SC3_PA6_DATA_FIFO_RD         = 0x000001c8,
20827  PH_PERF_SEL_SC3_PA6_DATA_FIFO_WE         = 0x000001c9,
20828  PH_PERF_SEL_SC3_PA6_FIFO_EMPTY           = 0x000001ca,
20829  PH_PERF_SEL_SC3_PA6_FIFO_FULL            = 0x000001cb,
20830  PH_PERF_SEL_SC3_PA6_NULL_WE              = 0x000001cc,
20831  PH_PERF_SEL_SC3_PA6_EVENT_WE             = 0x000001cd,
20832  PH_PERF_SEL_SC3_PA6_FPOV_WE              = 0x000001ce,
20833  PH_PERF_SEL_SC3_PA6_LPOV_WE              = 0x000001cf,
20834  PH_PERF_SEL_SC3_PA6_EOP_WE               = 0x000001d0,
20835  PH_PERF_SEL_SC3_PA6_DATA_FIFO_EOP_RD     = 0x000001d1,
20836  PH_PERF_SEL_SC3_PA6_EOPG_WE              = 0x000001d2,
20837  PH_PERF_SEL_SC3_PA6_DEALLOC_4_0_RD       = 0x000001d3,
20838  PH_PERF_SEL_SC3_PA7_DATA_FIFO_RD         = 0x000001d4,
20839  PH_PERF_SEL_SC3_PA7_DATA_FIFO_WE         = 0x000001d5,
20840  PH_PERF_SEL_SC3_PA7_FIFO_EMPTY           = 0x000001d6,
20841  PH_PERF_SEL_SC3_PA7_FIFO_FULL            = 0x000001d7,
20842  PH_PERF_SEL_SC3_PA7_NULL_WE              = 0x000001d8,
20843  PH_PERF_SEL_SC3_PA7_EVENT_WE             = 0x000001d9,
20844  PH_PERF_SEL_SC3_PA7_FPOV_WE              = 0x000001da,
20845  PH_PERF_SEL_SC3_PA7_LPOV_WE              = 0x000001db,
20846  PH_PERF_SEL_SC3_PA7_EOP_WE               = 0x000001dc,
20847  PH_PERF_SEL_SC3_PA7_DATA_FIFO_EOP_RD     = 0x000001dd,
20848  PH_PERF_SEL_SC3_PA7_EOPG_WE              = 0x000001de,
20849  PH_PERF_SEL_SC3_PA7_DEALLOC_4_0_RD       = 0x000001df,
20850  PH_PERF_SEL_SC4_SRPS_WINDOW_VALID        = 0x000001e0,
20851  PH_PERF_SEL_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x000001e1,
20852  PH_PERF_SEL_SC4_ARB_XFC_ONLY_PRIM_CYCLES = 0x000001e2,
20853  PH_PERF_SEL_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x000001e3,
20854  PH_PERF_SEL_SC4_ARB_STALLED_FROM_BELOW   = 0x000001e4,
20855  PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE   = 0x000001e5,
20856  PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000001e6,
20857  PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000001e7,
20858  PH_PERF_SEL_SC4_ARB_BUSY                 = 0x000001e8,
20859  PH_PERF_SEL_SC4_ARB_PA_BUSY_SOP          = 0x000001e9,
20860  PH_PERF_SEL_SC4_ARB_EOP_POP_SYNC_POP     = 0x000001ea,
20861  PH_PERF_SEL_SC4_ARB_EVENT_SYNC_POP       = 0x000001eb,
20862  PH_PERF_SEL_SC4_PS_ENG_MULTICYCLE_BUBBLE = 0x000001ec,
20863  PH_PERF_SEL_SC4_EOP_SYNC_WINDOW          = 0x000001ed,
20864  PH_PERF_SEL_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x000001ee,
20865  PH_PERF_SEL_SC4_BUSY_CNT_NOT_ZERO        = 0x000001ef,
20866  PH_PERF_SEL_SC4_SEND                     = 0x000001f0,
20867  PH_PERF_SEL_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001f1,
20868  PH_PERF_SEL_SC4_CREDIT_AT_MAX            = 0x000001f2,
20869  PH_PERF_SEL_SC4_CREDIT_AT_MAX_NO_PENDING_SEND = 0x000001f3,
20870  PH_PERF_SEL_SC4_GFX_PIPE0_TO_1_TRANSITION = 0x000001f4,
20871  PH_PERF_SEL_SC4_GFX_PIPE1_TO_0_TRANSITION = 0x000001f5,
20872  PH_PERF_SEL_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x000001f6,
20873  PH_PERF_SEL_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x000001f7,
20874  PH_PERF_SEL_SC4_PA0_DATA_FIFO_RD         = 0x000001f8,
20875  PH_PERF_SEL_SC4_PA0_DATA_FIFO_WE         = 0x000001f9,
20876  PH_PERF_SEL_SC4_PA0_FIFO_EMPTY           = 0x000001fa,
20877  PH_PERF_SEL_SC4_PA0_FIFO_FULL            = 0x000001fb,
20878  PH_PERF_SEL_SC4_PA0_NULL_WE              = 0x000001fc,
20879  PH_PERF_SEL_SC4_PA0_EVENT_WE             = 0x000001fd,
20880  PH_PERF_SEL_SC4_PA0_FPOV_WE              = 0x000001fe,
20881  PH_PERF_SEL_SC4_PA0_LPOV_WE              = 0x000001ff,
20882  PH_PERF_SEL_SC4_PA0_EOP_WE               = 0x00000200,
20883  PH_PERF_SEL_SC4_PA0_DATA_FIFO_EOP_RD     = 0x00000201,
20884  PH_PERF_SEL_SC4_PA0_EOPG_WE              = 0x00000202,
20885  PH_PERF_SEL_SC4_PA0_DEALLOC_4_0_RD       = 0x00000203,
20886  PH_PERF_SEL_SC4_PA1_DATA_FIFO_RD         = 0x00000204,
20887  PH_PERF_SEL_SC4_PA1_DATA_FIFO_WE         = 0x00000205,
20888  PH_PERF_SEL_SC4_PA1_FIFO_EMPTY           = 0x00000206,
20889  PH_PERF_SEL_SC4_PA1_FIFO_FULL            = 0x00000207,
20890  PH_PERF_SEL_SC4_PA1_NULL_WE              = 0x00000208,
20891  PH_PERF_SEL_SC4_PA1_EVENT_WE             = 0x00000209,
20892  PH_PERF_SEL_SC4_PA1_FPOV_WE              = 0x0000020a,
20893  PH_PERF_SEL_SC4_PA1_LPOV_WE              = 0x0000020b,
20894  PH_PERF_SEL_SC4_PA1_EOP_WE               = 0x0000020c,
20895  PH_PERF_SEL_SC4_PA1_DATA_FIFO_EOP_RD     = 0x0000020d,
20896  PH_PERF_SEL_SC4_PA1_EOPG_WE              = 0x0000020e,
20897  PH_PERF_SEL_SC4_PA1_DEALLOC_4_0_RD       = 0x0000020f,
20898  PH_PERF_SEL_SC4_PA2_DATA_FIFO_RD         = 0x00000210,
20899  PH_PERF_SEL_SC4_PA2_DATA_FIFO_WE         = 0x00000211,
20900  PH_PERF_SEL_SC4_PA2_FIFO_EMPTY           = 0x00000212,
20901  PH_PERF_SEL_SC4_PA2_FIFO_FULL            = 0x00000213,
20902  PH_PERF_SEL_SC4_PA2_NULL_WE              = 0x00000214,
20903  PH_PERF_SEL_SC4_PA2_EVENT_WE             = 0x00000215,
20904  PH_PERF_SEL_SC4_PA2_FPOV_WE              = 0x00000216,
20905  PH_PERF_SEL_SC4_PA2_LPOV_WE              = 0x00000217,
20906  PH_PERF_SEL_SC4_PA2_EOP_WE               = 0x00000218,
20907  PH_PERF_SEL_SC4_PA2_DATA_FIFO_EOP_RD     = 0x00000219,
20908  PH_PERF_SEL_SC4_PA2_EOPG_WE              = 0x0000021a,
20909  PH_PERF_SEL_SC4_PA2_DEALLOC_4_0_RD       = 0x0000021b,
20910  PH_PERF_SEL_SC4_PA3_DATA_FIFO_RD         = 0x0000021c,
20911  PH_PERF_SEL_SC4_PA3_DATA_FIFO_WE         = 0x0000021d,
20912  PH_PERF_SEL_SC4_PA3_FIFO_EMPTY           = 0x0000021e,
20913  PH_PERF_SEL_SC4_PA3_FIFO_FULL            = 0x0000021f,
20914  PH_PERF_SEL_SC4_PA3_NULL_WE              = 0x00000220,
20915  PH_PERF_SEL_SC4_PA3_EVENT_WE             = 0x00000221,
20916  PH_PERF_SEL_SC4_PA3_FPOV_WE              = 0x00000222,
20917  PH_PERF_SEL_SC4_PA3_LPOV_WE              = 0x00000223,
20918  PH_PERF_SEL_SC4_PA3_EOP_WE               = 0x00000224,
20919  PH_PERF_SEL_SC4_PA3_DATA_FIFO_EOP_RD     = 0x00000225,
20920  PH_PERF_SEL_SC4_PA3_EOPG_WE              = 0x00000226,
20921  PH_PERF_SEL_SC4_PA3_DEALLOC_4_0_RD       = 0x00000227,
20922  PH_PERF_SEL_SC4_PA4_DATA_FIFO_RD         = 0x00000228,
20923  PH_PERF_SEL_SC4_PA4_DATA_FIFO_WE         = 0x00000229,
20924  PH_PERF_SEL_SC4_PA4_FIFO_EMPTY           = 0x0000022a,
20925  PH_PERF_SEL_SC4_PA4_FIFO_FULL            = 0x0000022b,
20926  PH_PERF_SEL_SC4_PA4_NULL_WE              = 0x0000022c,
20927  PH_PERF_SEL_SC4_PA4_EVENT_WE             = 0x0000022d,
20928  PH_PERF_SEL_SC4_PA4_FPOV_WE              = 0x0000022e,
20929  PH_PERF_SEL_SC4_PA4_LPOV_WE              = 0x0000022f,
20930  PH_PERF_SEL_SC4_PA4_EOP_WE               = 0x00000230,
20931  PH_PERF_SEL_SC4_PA4_DATA_FIFO_EOP_RD     = 0x00000231,
20932  PH_PERF_SEL_SC4_PA4_EOPG_WE              = 0x00000232,
20933  PH_PERF_SEL_SC4_PA4_DEALLOC_4_0_RD       = 0x00000233,
20934  PH_PERF_SEL_SC4_PA5_DATA_FIFO_RD         = 0x00000234,
20935  PH_PERF_SEL_SC4_PA5_DATA_FIFO_WE         = 0x00000235,
20936  PH_PERF_SEL_SC4_PA5_FIFO_EMPTY           = 0x00000236,
20937  PH_PERF_SEL_SC4_PA5_FIFO_FULL            = 0x00000237,
20938  PH_PERF_SEL_SC4_PA5_NULL_WE              = 0x00000238,
20939  PH_PERF_SEL_SC4_PA5_EVENT_WE             = 0x00000239,
20940  PH_PERF_SEL_SC4_PA5_FPOV_WE              = 0x0000023a,
20941  PH_PERF_SEL_SC4_PA5_LPOV_WE              = 0x0000023b,
20942  PH_PERF_SEL_SC4_PA5_EOP_WE               = 0x0000023c,
20943  PH_PERF_SEL_SC4_PA5_DATA_FIFO_EOP_RD     = 0x0000023d,
20944  PH_PERF_SEL_SC4_PA5_EOPG_WE              = 0x0000023e,
20945  PH_PERF_SEL_SC4_PA5_DEALLOC_4_0_RD       = 0x0000023f,
20946  PH_PERF_SEL_SC4_PA6_DATA_FIFO_RD         = 0x00000240,
20947  PH_PERF_SEL_SC4_PA6_DATA_FIFO_WE         = 0x00000241,
20948  PH_PERF_SEL_SC4_PA6_FIFO_EMPTY           = 0x00000242,
20949  PH_PERF_SEL_SC4_PA6_FIFO_FULL            = 0x00000243,
20950  PH_PERF_SEL_SC4_PA6_NULL_WE              = 0x00000244,
20951  PH_PERF_SEL_SC4_PA6_EVENT_WE             = 0x00000245,
20952  PH_PERF_SEL_SC4_PA6_FPOV_WE              = 0x00000246,
20953  PH_PERF_SEL_SC4_PA6_LPOV_WE              = 0x00000247,
20954  PH_PERF_SEL_SC4_PA6_EOP_WE               = 0x00000248,
20955  PH_PERF_SEL_SC4_PA6_DATA_FIFO_EOP_RD     = 0x00000249,
20956  PH_PERF_SEL_SC4_PA6_EOPG_WE              = 0x0000024a,
20957  PH_PERF_SEL_SC4_PA6_DEALLOC_4_0_RD       = 0x0000024b,
20958  PH_PERF_SEL_SC4_PA7_DATA_FIFO_RD         = 0x0000024c,
20959  PH_PERF_SEL_SC4_PA7_DATA_FIFO_WE         = 0x0000024d,
20960  PH_PERF_SEL_SC4_PA7_FIFO_EMPTY           = 0x0000024e,
20961  PH_PERF_SEL_SC4_PA7_FIFO_FULL            = 0x0000024f,
20962  PH_PERF_SEL_SC4_PA7_NULL_WE              = 0x00000250,
20963  PH_PERF_SEL_SC4_PA7_EVENT_WE             = 0x00000251,
20964  PH_PERF_SEL_SC4_PA7_FPOV_WE              = 0x00000252,
20965  PH_PERF_SEL_SC4_PA7_LPOV_WE              = 0x00000253,
20966  PH_PERF_SEL_SC4_PA7_EOP_WE               = 0x00000254,
20967  PH_PERF_SEL_SC4_PA7_DATA_FIFO_EOP_RD     = 0x00000255,
20968  PH_PERF_SEL_SC4_PA7_EOPG_WE              = 0x00000256,
20969  PH_PERF_SEL_SC4_PA7_DEALLOC_4_0_RD       = 0x00000257,
20970  PH_PERF_SEL_SC5_SRPS_WINDOW_VALID        = 0x00000258,
20971  PH_PERF_SEL_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000259,
20972  PH_PERF_SEL_SC5_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000025a,
20973  PH_PERF_SEL_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000025b,
20974  PH_PERF_SEL_SC5_ARB_STALLED_FROM_BELOW   = 0x0000025c,
20975  PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE   = 0x0000025d,
20976  PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x0000025e,
20977  PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x0000025f,
20978  PH_PERF_SEL_SC5_ARB_BUSY                 = 0x00000260,
20979  PH_PERF_SEL_SC5_ARB_PA_BUSY_SOP          = 0x00000261,
20980  PH_PERF_SEL_SC5_ARB_EOP_POP_SYNC_POP     = 0x00000262,
20981  PH_PERF_SEL_SC5_ARB_EVENT_SYNC_POP       = 0x00000263,
20982  PH_PERF_SEL_SC5_PS_ENG_MULTICYCLE_BUBBLE = 0x00000264,
20983  PH_PERF_SEL_SC5_EOP_SYNC_WINDOW          = 0x00000265,
20984  PH_PERF_SEL_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000266,
20985  PH_PERF_SEL_SC5_BUSY_CNT_NOT_ZERO        = 0x00000267,
20986  PH_PERF_SEL_SC5_SEND                     = 0x00000268,
20987  PH_PERF_SEL_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000269,
20988  PH_PERF_SEL_SC5_CREDIT_AT_MAX            = 0x0000026a,
20989  PH_PERF_SEL_SC5_CREDIT_AT_MAX_NO_PENDING_SEND = 0x0000026b,
20990  PH_PERF_SEL_SC5_GFX_PIPE0_TO_1_TRANSITION = 0x0000026c,
20991  PH_PERF_SEL_SC5_GFX_PIPE1_TO_0_TRANSITION = 0x0000026d,
20992  PH_PERF_SEL_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x0000026e,
20993  PH_PERF_SEL_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x0000026f,
20994  PH_PERF_SEL_SC5_PA0_DATA_FIFO_RD         = 0x00000270,
20995  PH_PERF_SEL_SC5_PA0_DATA_FIFO_WE         = 0x00000271,
20996  PH_PERF_SEL_SC5_PA0_FIFO_EMPTY           = 0x00000272,
20997  PH_PERF_SEL_SC5_PA0_FIFO_FULL            = 0x00000273,
20998  PH_PERF_SEL_SC5_PA0_NULL_WE              = 0x00000274,
20999  PH_PERF_SEL_SC5_PA0_EVENT_WE             = 0x00000275,
21000  PH_PERF_SEL_SC5_PA0_FPOV_WE              = 0x00000276,
21001  PH_PERF_SEL_SC5_PA0_LPOV_WE              = 0x00000277,
21002  PH_PERF_SEL_SC5_PA0_EOP_WE               = 0x00000278,
21003  PH_PERF_SEL_SC5_PA0_DATA_FIFO_EOP_RD     = 0x00000279,
21004  PH_PERF_SEL_SC5_PA0_EOPG_WE              = 0x0000027a,
21005  PH_PERF_SEL_SC5_PA0_DEALLOC_4_0_RD       = 0x0000027b,
21006  PH_PERF_SEL_SC5_PA1_DATA_FIFO_RD         = 0x0000027c,
21007  PH_PERF_SEL_SC5_PA1_DATA_FIFO_WE         = 0x0000027d,
21008  PH_PERF_SEL_SC5_PA1_FIFO_EMPTY           = 0x0000027e,
21009  PH_PERF_SEL_SC5_PA1_FIFO_FULL            = 0x0000027f,
21010  PH_PERF_SEL_SC5_PA1_NULL_WE              = 0x00000280,
21011  PH_PERF_SEL_SC5_PA1_EVENT_WE             = 0x00000281,
21012  PH_PERF_SEL_SC5_PA1_FPOV_WE              = 0x00000282,
21013  PH_PERF_SEL_SC5_PA1_LPOV_WE              = 0x00000283,
21014  PH_PERF_SEL_SC5_PA1_EOP_WE               = 0x00000284,
21015  PH_PERF_SEL_SC5_PA1_DATA_FIFO_EOP_RD     = 0x00000285,
21016  PH_PERF_SEL_SC5_PA1_EOPG_WE              = 0x00000286,
21017  PH_PERF_SEL_SC5_PA1_DEALLOC_4_0_RD       = 0x00000287,
21018  PH_PERF_SEL_SC5_PA2_DATA_FIFO_RD         = 0x00000288,
21019  PH_PERF_SEL_SC5_PA2_DATA_FIFO_WE         = 0x00000289,
21020  PH_PERF_SEL_SC5_PA2_FIFO_EMPTY           = 0x0000028a,
21021  PH_PERF_SEL_SC5_PA2_FIFO_FULL            = 0x0000028b,
21022  PH_PERF_SEL_SC5_PA2_NULL_WE              = 0x0000028c,
21023  PH_PERF_SEL_SC5_PA2_EVENT_WE             = 0x0000028d,
21024  PH_PERF_SEL_SC5_PA2_FPOV_WE              = 0x0000028e,
21025  PH_PERF_SEL_SC5_PA2_LPOV_WE              = 0x0000028f,
21026  PH_PERF_SEL_SC5_PA2_EOP_WE               = 0x00000290,
21027  PH_PERF_SEL_SC5_PA2_DATA_FIFO_EOP_RD     = 0x00000291,
21028  PH_PERF_SEL_SC5_PA2_EOPG_WE              = 0x00000292,
21029  PH_PERF_SEL_SC5_PA2_DEALLOC_4_0_RD       = 0x00000293,
21030  PH_PERF_SEL_SC5_PA3_DATA_FIFO_RD         = 0x00000294,
21031  PH_PERF_SEL_SC5_PA3_DATA_FIFO_WE         = 0x00000295,
21032  PH_PERF_SEL_SC5_PA3_FIFO_EMPTY           = 0x00000296,
21033  PH_PERF_SEL_SC5_PA3_FIFO_FULL            = 0x00000297,
21034  PH_PERF_SEL_SC5_PA3_NULL_WE              = 0x00000298,
21035  PH_PERF_SEL_SC5_PA3_EVENT_WE             = 0x00000299,
21036  PH_PERF_SEL_SC5_PA3_FPOV_WE              = 0x0000029a,
21037  PH_PERF_SEL_SC5_PA3_LPOV_WE              = 0x0000029b,
21038  PH_PERF_SEL_SC5_PA3_EOP_WE               = 0x0000029c,
21039  PH_PERF_SEL_SC5_PA3_DATA_FIFO_EOP_RD     = 0x0000029d,
21040  PH_PERF_SEL_SC5_PA3_EOPG_WE              = 0x0000029e,
21041  PH_PERF_SEL_SC5_PA3_DEALLOC_4_0_RD       = 0x0000029f,
21042  PH_PERF_SEL_SC5_PA4_DATA_FIFO_RD         = 0x000002a0,
21043  PH_PERF_SEL_SC5_PA4_DATA_FIFO_WE         = 0x000002a1,
21044  PH_PERF_SEL_SC5_PA4_FIFO_EMPTY           = 0x000002a2,
21045  PH_PERF_SEL_SC5_PA4_FIFO_FULL            = 0x000002a3,
21046  PH_PERF_SEL_SC5_PA4_NULL_WE              = 0x000002a4,
21047  PH_PERF_SEL_SC5_PA4_EVENT_WE             = 0x000002a5,
21048  PH_PERF_SEL_SC5_PA4_FPOV_WE              = 0x000002a6,
21049  PH_PERF_SEL_SC5_PA4_LPOV_WE              = 0x000002a7,
21050  PH_PERF_SEL_SC5_PA4_EOP_WE               = 0x000002a8,
21051  PH_PERF_SEL_SC5_PA4_DATA_FIFO_EOP_RD     = 0x000002a9,
21052  PH_PERF_SEL_SC5_PA4_EOPG_WE              = 0x000002aa,
21053  PH_PERF_SEL_SC5_PA4_DEALLOC_4_0_RD       = 0x000002ab,
21054  PH_PERF_SEL_SC5_PA5_DATA_FIFO_RD         = 0x000002ac,
21055  PH_PERF_SEL_SC5_PA5_DATA_FIFO_WE         = 0x000002ad,
21056  PH_PERF_SEL_SC5_PA5_FIFO_EMPTY           = 0x000002ae,
21057  PH_PERF_SEL_SC5_PA5_FIFO_FULL            = 0x000002af,
21058  PH_PERF_SEL_SC5_PA5_NULL_WE              = 0x000002b0,
21059  PH_PERF_SEL_SC5_PA5_EVENT_WE             = 0x000002b1,
21060  PH_PERF_SEL_SC5_PA5_FPOV_WE              = 0x000002b2,
21061  PH_PERF_SEL_SC5_PA5_LPOV_WE              = 0x000002b3,
21062  PH_PERF_SEL_SC5_PA5_EOP_WE               = 0x000002b4,
21063  PH_PERF_SEL_SC5_PA5_DATA_FIFO_EOP_RD     = 0x000002b5,
21064  PH_PERF_SEL_SC5_PA5_EOPG_WE              = 0x000002b6,
21065  PH_PERF_SEL_SC5_PA5_DEALLOC_4_0_RD       = 0x000002b7,
21066  PH_PERF_SEL_SC5_PA6_DATA_FIFO_RD         = 0x000002b8,
21067  PH_PERF_SEL_SC5_PA6_DATA_FIFO_WE         = 0x000002b9,
21068  PH_PERF_SEL_SC5_PA6_FIFO_EMPTY           = 0x000002ba,
21069  PH_PERF_SEL_SC5_PA6_FIFO_FULL            = 0x000002bb,
21070  PH_PERF_SEL_SC5_PA6_NULL_WE              = 0x000002bc,
21071  PH_PERF_SEL_SC5_PA6_EVENT_WE             = 0x000002bd,
21072  PH_PERF_SEL_SC5_PA6_FPOV_WE              = 0x000002be,
21073  PH_PERF_SEL_SC5_PA6_LPOV_WE              = 0x000002bf,
21074  PH_PERF_SEL_SC5_PA6_EOP_WE               = 0x000002c0,
21075  PH_PERF_SEL_SC5_PA6_DATA_FIFO_EOP_RD     = 0x000002c1,
21076  PH_PERF_SEL_SC5_PA6_EOPG_WE              = 0x000002c2,
21077  PH_PERF_SEL_SC5_PA6_DEALLOC_4_0_RD       = 0x000002c3,
21078  PH_PERF_SEL_SC5_PA7_DATA_FIFO_RD         = 0x000002c4,
21079  PH_PERF_SEL_SC5_PA7_DATA_FIFO_WE         = 0x000002c5,
21080  PH_PERF_SEL_SC5_PA7_FIFO_EMPTY           = 0x000002c6,
21081  PH_PERF_SEL_SC5_PA7_FIFO_FULL            = 0x000002c7,
21082  PH_PERF_SEL_SC5_PA7_NULL_WE              = 0x000002c8,
21083  PH_PERF_SEL_SC5_PA7_EVENT_WE             = 0x000002c9,
21084  PH_PERF_SEL_SC5_PA7_FPOV_WE              = 0x000002ca,
21085  PH_PERF_SEL_SC5_PA7_LPOV_WE              = 0x000002cb,
21086  PH_PERF_SEL_SC5_PA7_EOP_WE               = 0x000002cc,
21087  PH_PERF_SEL_SC5_PA7_DATA_FIFO_EOP_RD     = 0x000002cd,
21088  PH_PERF_SEL_SC5_PA7_EOPG_WE              = 0x000002ce,
21089  PH_PERF_SEL_SC5_PA7_DEALLOC_4_0_RD       = 0x000002cf,
21090  PH_PERF_SEL_SC6_SRPS_WINDOW_VALID        = 0x000002d0,
21091  PH_PERF_SEL_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x000002d1,
21092  PH_PERF_SEL_SC6_ARB_XFC_ONLY_PRIM_CYCLES = 0x000002d2,
21093  PH_PERF_SEL_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x000002d3,
21094  PH_PERF_SEL_SC6_ARB_STALLED_FROM_BELOW   = 0x000002d4,
21095  PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE   = 0x000002d5,
21096  PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000002d6,
21097  PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000002d7,
21098  PH_PERF_SEL_SC6_ARB_BUSY                 = 0x000002d8,
21099  PH_PERF_SEL_SC6_ARB_PA_BUSY_SOP          = 0x000002d9,
21100  PH_PERF_SEL_SC6_ARB_EOP_POP_SYNC_POP     = 0x000002da,
21101  PH_PERF_SEL_SC6_ARB_EVENT_SYNC_POP       = 0x000002db,
21102  PH_PERF_SEL_SC6_PS_ENG_MULTICYCLE_BUBBLE = 0x000002dc,
21103  PH_PERF_SEL_SC6_EOP_SYNC_WINDOW          = 0x000002dd,
21104  PH_PERF_SEL_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x000002de,
21105  PH_PERF_SEL_SC6_BUSY_CNT_NOT_ZERO        = 0x000002df,
21106  PH_PERF_SEL_SC6_SEND                     = 0x000002e0,
21107  PH_PERF_SEL_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000002e1,
21108  PH_PERF_SEL_SC6_CREDIT_AT_MAX            = 0x000002e2,
21109  PH_PERF_SEL_SC6_CREDIT_AT_MAX_NO_PENDING_SEND = 0x000002e3,
21110  PH_PERF_SEL_SC6_GFX_PIPE0_TO_1_TRANSITION = 0x000002e4,
21111  PH_PERF_SEL_SC6_GFX_PIPE1_TO_0_TRANSITION = 0x000002e5,
21112  PH_PERF_SEL_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x000002e6,
21113  PH_PERF_SEL_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x000002e7,
21114  PH_PERF_SEL_SC6_PA0_DATA_FIFO_RD         = 0x000002e8,
21115  PH_PERF_SEL_SC6_PA0_DATA_FIFO_WE         = 0x000002e9,
21116  PH_PERF_SEL_SC6_PA0_FIFO_EMPTY           = 0x000002ea,
21117  PH_PERF_SEL_SC6_PA0_FIFO_FULL            = 0x000002eb,
21118  PH_PERF_SEL_SC6_PA0_NULL_WE              = 0x000002ec,
21119  PH_PERF_SEL_SC6_PA0_EVENT_WE             = 0x000002ed,
21120  PH_PERF_SEL_SC6_PA0_FPOV_WE              = 0x000002ee,
21121  PH_PERF_SEL_SC6_PA0_LPOV_WE              = 0x000002ef,
21122  PH_PERF_SEL_SC6_PA0_EOP_WE               = 0x000002f0,
21123  PH_PERF_SEL_SC6_PA0_DATA_FIFO_EOP_RD     = 0x000002f1,
21124  PH_PERF_SEL_SC6_PA0_EOPG_WE              = 0x000002f2,
21125  PH_PERF_SEL_SC6_PA0_DEALLOC_4_0_RD       = 0x000002f3,
21126  PH_PERF_SEL_SC6_PA1_DATA_FIFO_RD         = 0x000002f4,
21127  PH_PERF_SEL_SC6_PA1_DATA_FIFO_WE         = 0x000002f5,
21128  PH_PERF_SEL_SC6_PA1_FIFO_EMPTY           = 0x000002f6,
21129  PH_PERF_SEL_SC6_PA1_FIFO_FULL            = 0x000002f7,
21130  PH_PERF_SEL_SC6_PA1_NULL_WE              = 0x000002f8,
21131  PH_PERF_SEL_SC6_PA1_EVENT_WE             = 0x000002f9,
21132  PH_PERF_SEL_SC6_PA1_FPOV_WE              = 0x000002fa,
21133  PH_PERF_SEL_SC6_PA1_LPOV_WE              = 0x000002fb,
21134  PH_PERF_SEL_SC6_PA1_EOP_WE               = 0x000002fc,
21135  PH_PERF_SEL_SC6_PA1_DATA_FIFO_EOP_RD     = 0x000002fd,
21136  PH_PERF_SEL_SC6_PA1_EOPG_WE              = 0x000002fe,
21137  PH_PERF_SEL_SC6_PA1_DEALLOC_4_0_RD       = 0x000002ff,
21138  PH_PERF_SEL_SC6_PA2_DATA_FIFO_RD         = 0x00000300,
21139  PH_PERF_SEL_SC6_PA2_DATA_FIFO_WE         = 0x00000301,
21140  PH_PERF_SEL_SC6_PA2_FIFO_EMPTY           = 0x00000302,
21141  PH_PERF_SEL_SC6_PA2_FIFO_FULL            = 0x00000303,
21142  PH_PERF_SEL_SC6_PA2_NULL_WE              = 0x00000304,
21143  PH_PERF_SEL_SC6_PA2_EVENT_WE             = 0x00000305,
21144  PH_PERF_SEL_SC6_PA2_FPOV_WE              = 0x00000306,
21145  PH_PERF_SEL_SC6_PA2_LPOV_WE              = 0x00000307,
21146  PH_PERF_SEL_SC6_PA2_EOP_WE               = 0x00000308,
21147  PH_PERF_SEL_SC6_PA2_DATA_FIFO_EOP_RD     = 0x00000309,
21148  PH_PERF_SEL_SC6_PA2_EOPG_WE              = 0x0000030a,
21149  PH_PERF_SEL_SC6_PA2_DEALLOC_4_0_RD       = 0x0000030b,
21150  PH_PERF_SEL_SC6_PA3_DATA_FIFO_RD         = 0x0000030c,
21151  PH_PERF_SEL_SC6_PA3_DATA_FIFO_WE         = 0x0000030d,
21152  PH_PERF_SEL_SC6_PA3_FIFO_EMPTY           = 0x0000030e,
21153  PH_PERF_SEL_SC6_PA3_FIFO_FULL            = 0x0000030f,
21154  PH_PERF_SEL_SC6_PA3_NULL_WE              = 0x00000310,
21155  PH_PERF_SEL_SC6_PA3_EVENT_WE             = 0x00000311,
21156  PH_PERF_SEL_SC6_PA3_FPOV_WE              = 0x00000312,
21157  PH_PERF_SEL_SC6_PA3_LPOV_WE              = 0x00000313,
21158  PH_PERF_SEL_SC6_PA3_EOP_WE               = 0x00000314,
21159  PH_PERF_SEL_SC6_PA3_DATA_FIFO_EOP_RD     = 0x00000315,
21160  PH_PERF_SEL_SC6_PA3_EOPG_WE              = 0x00000316,
21161  PH_PERF_SEL_SC6_PA3_DEALLOC_4_0_RD       = 0x00000317,
21162  PH_PERF_SEL_SC6_PA4_DATA_FIFO_RD         = 0x00000318,
21163  PH_PERF_SEL_SC6_PA4_DATA_FIFO_WE         = 0x00000319,
21164  PH_PERF_SEL_SC6_PA4_FIFO_EMPTY           = 0x0000031a,
21165  PH_PERF_SEL_SC6_PA4_FIFO_FULL            = 0x0000031b,
21166  PH_PERF_SEL_SC6_PA4_NULL_WE              = 0x0000031c,
21167  PH_PERF_SEL_SC6_PA4_EVENT_WE             = 0x0000031d,
21168  PH_PERF_SEL_SC6_PA4_FPOV_WE              = 0x0000031e,
21169  PH_PERF_SEL_SC6_PA4_LPOV_WE              = 0x0000031f,
21170  PH_PERF_SEL_SC6_PA4_EOP_WE               = 0x00000320,
21171  PH_PERF_SEL_SC6_PA4_DATA_FIFO_EOP_RD     = 0x00000321,
21172  PH_PERF_SEL_SC6_PA4_EOPG_WE              = 0x00000322,
21173  PH_PERF_SEL_SC6_PA4_DEALLOC_4_0_RD       = 0x00000323,
21174  PH_PERF_SEL_SC6_PA5_DATA_FIFO_RD         = 0x00000324,
21175  PH_PERF_SEL_SC6_PA5_DATA_FIFO_WE         = 0x00000325,
21176  PH_PERF_SEL_SC6_PA5_FIFO_EMPTY           = 0x00000326,
21177  PH_PERF_SEL_SC6_PA5_FIFO_FULL            = 0x00000327,
21178  PH_PERF_SEL_SC6_PA5_NULL_WE              = 0x00000328,
21179  PH_PERF_SEL_SC6_PA5_EVENT_WE             = 0x00000329,
21180  PH_PERF_SEL_SC6_PA5_FPOV_WE              = 0x0000032a,
21181  PH_PERF_SEL_SC6_PA5_LPOV_WE              = 0x0000032b,
21182  PH_PERF_SEL_SC6_PA5_EOP_WE               = 0x0000032c,
21183  PH_PERF_SEL_SC6_PA5_DATA_FIFO_EOP_RD     = 0x0000032d,
21184  PH_PERF_SEL_SC6_PA5_EOPG_WE              = 0x0000032e,
21185  PH_PERF_SEL_SC6_PA5_DEALLOC_4_0_RD       = 0x0000032f,
21186  PH_PERF_SEL_SC6_PA6_DATA_FIFO_RD         = 0x00000330,
21187  PH_PERF_SEL_SC6_PA6_DATA_FIFO_WE         = 0x00000331,
21188  PH_PERF_SEL_SC6_PA6_FIFO_EMPTY           = 0x00000332,
21189  PH_PERF_SEL_SC6_PA6_FIFO_FULL            = 0x00000333,
21190  PH_PERF_SEL_SC6_PA6_NULL_WE              = 0x00000334,
21191  PH_PERF_SEL_SC6_PA6_EVENT_WE             = 0x00000335,
21192  PH_PERF_SEL_SC6_PA6_FPOV_WE              = 0x00000336,
21193  PH_PERF_SEL_SC6_PA6_LPOV_WE              = 0x00000337,
21194  PH_PERF_SEL_SC6_PA6_EOP_WE               = 0x00000338,
21195  PH_PERF_SEL_SC6_PA6_DATA_FIFO_EOP_RD     = 0x00000339,
21196  PH_PERF_SEL_SC6_PA6_EOPG_WE              = 0x0000033a,
21197  PH_PERF_SEL_SC6_PA6_DEALLOC_4_0_RD       = 0x0000033b,
21198  PH_PERF_SEL_SC6_PA7_DATA_FIFO_RD         = 0x0000033c,
21199  PH_PERF_SEL_SC6_PA7_DATA_FIFO_WE         = 0x0000033d,
21200  PH_PERF_SEL_SC6_PA7_FIFO_EMPTY           = 0x0000033e,
21201  PH_PERF_SEL_SC6_PA7_FIFO_FULL            = 0x0000033f,
21202  PH_PERF_SEL_SC6_PA7_NULL_WE              = 0x00000340,
21203  PH_PERF_SEL_SC6_PA7_EVENT_WE             = 0x00000341,
21204  PH_PERF_SEL_SC6_PA7_FPOV_WE              = 0x00000342,
21205  PH_PERF_SEL_SC6_PA7_LPOV_WE              = 0x00000343,
21206  PH_PERF_SEL_SC6_PA7_EOP_WE               = 0x00000344,
21207  PH_PERF_SEL_SC6_PA7_DATA_FIFO_EOP_RD     = 0x00000345,
21208  PH_PERF_SEL_SC6_PA7_EOPG_WE              = 0x00000346,
21209  PH_PERF_SEL_SC6_PA7_DEALLOC_4_0_RD       = 0x00000347,
21210  PH_PERF_SEL_SC7_SRPS_WINDOW_VALID        = 0x00000348,
21211  PH_PERF_SEL_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000349,
21212  PH_PERF_SEL_SC7_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000034a,
21213  PH_PERF_SEL_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000034b,
21214  PH_PERF_SEL_SC7_ARB_STALLED_FROM_BELOW   = 0x0000034c,
21215  PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE   = 0x0000034d,
21216  PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x0000034e,
21217  PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x0000034f,
21218  PH_PERF_SEL_SC7_ARB_BUSY                 = 0x00000350,
21219  PH_PERF_SEL_SC7_ARB_PA_BUSY_SOP          = 0x00000351,
21220  PH_PERF_SEL_SC7_ARB_EOP_POP_SYNC_POP     = 0x00000352,
21221  PH_PERF_SEL_SC7_ARB_EVENT_SYNC_POP       = 0x00000353,
21222  PH_PERF_SEL_SC7_PS_ENG_MULTICYCLE_BUBBLE = 0x00000354,
21223  PH_PERF_SEL_SC7_EOP_SYNC_WINDOW          = 0x00000355,
21224  PH_PERF_SEL_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000356,
21225  PH_PERF_SEL_SC7_BUSY_CNT_NOT_ZERO        = 0x00000357,
21226  PH_PERF_SEL_SC7_SEND                     = 0x00000358,
21227  PH_PERF_SEL_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000359,
21228  PH_PERF_SEL_SC7_CREDIT_AT_MAX            = 0x0000035a,
21229  PH_PERF_SEL_SC7_CREDIT_AT_MAX_NO_PENDING_SEND = 0x0000035b,
21230  PH_PERF_SEL_SC7_GFX_PIPE0_TO_1_TRANSITION = 0x0000035c,
21231  PH_PERF_SEL_SC7_GFX_PIPE1_TO_0_TRANSITION = 0x0000035d,
21232  PH_PERF_SEL_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x0000035e,
21233  PH_PERF_SEL_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x0000035f,
21234  PH_PERF_SEL_SC7_PA0_DATA_FIFO_RD         = 0x00000360,
21235  PH_PERF_SEL_SC7_PA0_DATA_FIFO_WE         = 0x00000361,
21236  PH_PERF_SEL_SC7_PA0_FIFO_EMPTY           = 0x00000362,
21237  PH_PERF_SEL_SC7_PA0_FIFO_FULL            = 0x00000363,
21238  PH_PERF_SEL_SC7_PA0_NULL_WE              = 0x00000364,
21239  PH_PERF_SEL_SC7_PA0_EVENT_WE             = 0x00000365,
21240  PH_PERF_SEL_SC7_PA0_FPOV_WE              = 0x00000366,
21241  PH_PERF_SEL_SC7_PA0_LPOV_WE              = 0x00000367,
21242  PH_PERF_SEL_SC7_PA0_EOP_WE               = 0x00000368,
21243  PH_PERF_SEL_SC7_PA0_DATA_FIFO_EOP_RD     = 0x00000369,
21244  PH_PERF_SEL_SC7_PA0_EOPG_WE              = 0x0000036a,
21245  PH_PERF_SEL_SC7_PA0_DEALLOC_4_0_RD       = 0x0000036b,
21246  PH_PERF_SEL_SC7_PA1_DATA_FIFO_RD         = 0x0000036c,
21247  PH_PERF_SEL_SC7_PA1_DATA_FIFO_WE         = 0x0000036d,
21248  PH_PERF_SEL_SC7_PA1_FIFO_EMPTY           = 0x0000036e,
21249  PH_PERF_SEL_SC7_PA1_FIFO_FULL            = 0x0000036f,
21250  PH_PERF_SEL_SC7_PA1_NULL_WE              = 0x00000370,
21251  PH_PERF_SEL_SC7_PA1_EVENT_WE             = 0x00000371,
21252  PH_PERF_SEL_SC7_PA1_FPOV_WE              = 0x00000372,
21253  PH_PERF_SEL_SC7_PA1_LPOV_WE              = 0x00000373,
21254  PH_PERF_SEL_SC7_PA1_EOP_WE               = 0x00000374,
21255  PH_PERF_SEL_SC7_PA1_DATA_FIFO_EOP_RD     = 0x00000375,
21256  PH_PERF_SEL_SC7_PA1_EOPG_WE              = 0x00000376,
21257  PH_PERF_SEL_SC7_PA1_DEALLOC_4_0_RD       = 0x00000377,
21258  PH_PERF_SEL_SC7_PA2_DATA_FIFO_RD         = 0x00000378,
21259  PH_PERF_SEL_SC7_PA2_DATA_FIFO_WE         = 0x00000379,
21260  PH_PERF_SEL_SC7_PA2_FIFO_EMPTY           = 0x0000037a,
21261  PH_PERF_SEL_SC7_PA2_FIFO_FULL            = 0x0000037b,
21262  PH_PERF_SEL_SC7_PA2_NULL_WE              = 0x0000037c,
21263  PH_PERF_SEL_SC7_PA2_EVENT_WE             = 0x0000037d,
21264  PH_PERF_SEL_SC7_PA2_FPOV_WE              = 0x0000037e,
21265  PH_PERF_SEL_SC7_PA2_LPOV_WE              = 0x0000037f,
21266  PH_PERF_SEL_SC7_PA2_EOP_WE               = 0x00000380,
21267  PH_PERF_SEL_SC7_PA2_DATA_FIFO_EOP_RD     = 0x00000381,
21268  PH_PERF_SEL_SC7_PA2_EOPG_WE              = 0x00000382,
21269  PH_PERF_SEL_SC7_PA2_DEALLOC_4_0_RD       = 0x00000383,
21270  PH_PERF_SEL_SC7_PA3_DATA_FIFO_RD         = 0x00000384,
21271  PH_PERF_SEL_SC7_PA3_DATA_FIFO_WE         = 0x00000385,
21272  PH_PERF_SEL_SC7_PA3_FIFO_EMPTY           = 0x00000386,
21273  PH_PERF_SEL_SC7_PA3_FIFO_FULL            = 0x00000387,
21274  PH_PERF_SEL_SC7_PA3_NULL_WE              = 0x00000388,
21275  PH_PERF_SEL_SC7_PA3_EVENT_WE             = 0x00000389,
21276  PH_PERF_SEL_SC7_PA3_FPOV_WE              = 0x0000038a,
21277  PH_PERF_SEL_SC7_PA3_LPOV_WE              = 0x0000038b,
21278  PH_PERF_SEL_SC7_PA3_EOP_WE               = 0x0000038c,
21279  PH_PERF_SEL_SC7_PA3_DATA_FIFO_EOP_RD     = 0x0000038d,
21280  PH_PERF_SEL_SC7_PA3_EOPG_WE              = 0x0000038e,
21281  PH_PERF_SEL_SC7_PA3_DEALLOC_4_0_RD       = 0x0000038f,
21282  PH_PERF_SEL_SC7_PA4_DATA_FIFO_RD         = 0x00000390,
21283  PH_PERF_SEL_SC7_PA4_DATA_FIFO_WE         = 0x00000391,
21284  PH_PERF_SEL_SC7_PA4_FIFO_EMPTY           = 0x00000392,
21285  PH_PERF_SEL_SC7_PA4_FIFO_FULL            = 0x00000393,
21286  PH_PERF_SEL_SC7_PA4_NULL_WE              = 0x00000394,
21287  PH_PERF_SEL_SC7_PA4_EVENT_WE             = 0x00000395,
21288  PH_PERF_SEL_SC7_PA4_FPOV_WE              = 0x00000396,
21289  PH_PERF_SEL_SC7_PA4_LPOV_WE              = 0x00000397,
21290  PH_PERF_SEL_SC7_PA4_EOP_WE               = 0x00000398,
21291  PH_PERF_SEL_SC7_PA4_DATA_FIFO_EOP_RD     = 0x00000399,
21292  PH_PERF_SEL_SC7_PA4_EOPG_WE              = 0x0000039a,
21293  PH_PERF_SEL_SC7_PA4_DEALLOC_4_0_RD       = 0x0000039b,
21294  PH_PERF_SEL_SC7_PA5_DATA_FIFO_RD         = 0x0000039c,
21295  PH_PERF_SEL_SC7_PA5_DATA_FIFO_WE         = 0x0000039d,
21296  PH_PERF_SEL_SC7_PA5_FIFO_EMPTY           = 0x0000039e,
21297  PH_PERF_SEL_SC7_PA5_FIFO_FULL            = 0x0000039f,
21298  PH_PERF_SEL_SC7_PA5_NULL_WE              = 0x000003a0,
21299  PH_PERF_SEL_SC7_PA5_EVENT_WE             = 0x000003a1,
21300  PH_PERF_SEL_SC7_PA5_FPOV_WE              = 0x000003a2,
21301  PH_PERF_SEL_SC7_PA5_LPOV_WE              = 0x000003a3,
21302  PH_PERF_SEL_SC7_PA5_EOP_WE               = 0x000003a4,
21303  PH_PERF_SEL_SC7_PA5_DATA_FIFO_EOP_RD     = 0x000003a5,
21304  PH_PERF_SEL_SC7_PA5_EOPG_WE              = 0x000003a6,
21305  PH_PERF_SEL_SC7_PA5_DEALLOC_4_0_RD       = 0x000003a7,
21306  PH_PERF_SEL_SC7_PA6_DATA_FIFO_RD         = 0x000003a8,
21307  PH_PERF_SEL_SC7_PA6_DATA_FIFO_WE         = 0x000003a9,
21308  PH_PERF_SEL_SC7_PA6_FIFO_EMPTY           = 0x000003aa,
21309  PH_PERF_SEL_SC7_PA6_FIFO_FULL            = 0x000003ab,
21310  PH_PERF_SEL_SC7_PA6_NULL_WE              = 0x000003ac,
21311  PH_PERF_SEL_SC7_PA6_EVENT_WE             = 0x000003ad,
21312  PH_PERF_SEL_SC7_PA6_FPOV_WE              = 0x000003ae,
21313  PH_PERF_SEL_SC7_PA6_LPOV_WE              = 0x000003af,
21314  PH_PERF_SEL_SC7_PA6_EOP_WE               = 0x000003b0,
21315  PH_PERF_SEL_SC7_PA6_DATA_FIFO_EOP_RD     = 0x000003b1,
21316  PH_PERF_SEL_SC7_PA6_EOPG_WE              = 0x000003b2,
21317  PH_PERF_SEL_SC7_PA6_DEALLOC_4_0_RD       = 0x000003b3,
21318  PH_PERF_SEL_SC7_PA7_DATA_FIFO_RD         = 0x000003b4,
21319  PH_PERF_SEL_SC7_PA7_DATA_FIFO_WE         = 0x000003b5,
21320  PH_PERF_SEL_SC7_PA7_FIFO_EMPTY           = 0x000003b6,
21321  PH_PERF_SEL_SC7_PA7_FIFO_FULL            = 0x000003b7,
21322  PH_PERF_SEL_SC7_PA7_NULL_WE              = 0x000003b8,
21323  PH_PERF_SEL_SC7_PA7_EVENT_WE             = 0x000003b9,
21324  PH_PERF_SEL_SC7_PA7_FPOV_WE              = 0x000003ba,
21325  PH_PERF_SEL_SC7_PA7_LPOV_WE              = 0x000003bb,
21326  PH_PERF_SEL_SC7_PA7_EOP_WE               = 0x000003bc,
21327  PH_PERF_SEL_SC7_PA7_DATA_FIFO_EOP_RD     = 0x000003bd,
21328  PH_PERF_SEL_SC7_PA7_EOPG_WE              = 0x000003be,
21329  PH_PERF_SEL_SC7_PA7_DEALLOC_4_0_RD       = 0x000003bf,
21330  PH_PERF_SEL_1_SC_ARB_STALLED_FROM_BELOW  = 0x000003c0,
21331  PH_PERF_SEL_2_SC_ARB_STALLED_FROM_BELOW  = 0x000003c1,
21332  PH_PERF_SEL_3_SC_ARB_STALLED_FROM_BELOW  = 0x000003c2,
21333  PH_PERF_SEL_4_SC_ARB_STALLED_FROM_BELOW  = 0x000003c3,
21334  PH_PERF_SEL_5_SC_ARB_STALLED_FROM_BELOW  = 0x000003c4,
21335  PH_PERF_SEL_6_SC_ARB_STALLED_FROM_BELOW  = 0x000003c5,
21336  PH_PERF_SEL_7_SC_ARB_STALLED_FROM_BELOW  = 0x000003c6,
21337  PH_PERF_SEL_8_SC_ARB_STALLED_FROM_BELOW  = 0x000003c7,
21338  PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE  = 0x000003c8,
21339  PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE  = 0x000003c9,
21340  PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE  = 0x000003ca,
21341  PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE  = 0x000003cb,
21342  PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE  = 0x000003cc,
21343  PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE  = 0x000003cd,
21344  PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE  = 0x000003ce,
21345  PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE  = 0x000003cf,
21346  PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d0,
21347  PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d1,
21348  PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d2,
21349  PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d3,
21350  PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d4,
21351  PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d5,
21352  PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d6,
21353  PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d7,
21354  PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003d8,
21355  PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003d9,
21356  PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003da,
21357  PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003db,
21358  PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003dc,
21359  PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003dd,
21360  PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003de,
21361  PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003df,
21362  PH_PERF_SC0_FIFO_STATUS_0                = 0x000003e0,
21363  PH_PERF_SC0_FIFO_STATUS_1                = 0x000003e1,
21364  PH_PERF_SC0_FIFO_STATUS_2                = 0x000003e2,
21365  PH_PERF_SC0_FIFO_STATUS_3                = 0x000003e3,
21366  PH_PERF_SC1_FIFO_STATUS_0                = 0x000003e4,
21367  PH_PERF_SC1_FIFO_STATUS_1                = 0x000003e5,
21368  PH_PERF_SC1_FIFO_STATUS_2                = 0x000003e6,
21369  PH_PERF_SC1_FIFO_STATUS_3                = 0x000003e7,
21370  PH_PERF_SC2_FIFO_STATUS_0                = 0x000003e8,
21371  PH_PERF_SC2_FIFO_STATUS_1                = 0x000003e9,
21372  PH_PERF_SC2_FIFO_STATUS_2                = 0x000003ea,
21373  PH_PERF_SC2_FIFO_STATUS_3                = 0x000003eb,
21374  PH_PERF_SC3_FIFO_STATUS_0                = 0x000003ec,
21375  PH_PERF_SC3_FIFO_STATUS_1                = 0x000003ed,
21376  PH_PERF_SC3_FIFO_STATUS_2                = 0x000003ee,
21377  PH_PERF_SC3_FIFO_STATUS_3                = 0x000003ef,
21378  PH_PERF_SC4_FIFO_STATUS_0                = 0x000003f0,
21379  PH_PERF_SC4_FIFO_STATUS_1                = 0x000003f1,
21380  PH_PERF_SC4_FIFO_STATUS_2                = 0x000003f2,
21381  PH_PERF_SC4_FIFO_STATUS_3                = 0x000003f3,
21382  PH_PERF_SC5_FIFO_STATUS_0                = 0x000003f4,
21383  PH_PERF_SC5_FIFO_STATUS_1                = 0x000003f5,
21384  PH_PERF_SC5_FIFO_STATUS_2                = 0x000003f6,
21385  PH_PERF_SC5_FIFO_STATUS_3                = 0x000003f7,
21386  PH_PERF_SC6_FIFO_STATUS_0                = 0x000003f8,
21387  PH_PERF_SC6_FIFO_STATUS_1                = 0x000003f9,
21388  PH_PERF_SC6_FIFO_STATUS_2                = 0x000003fa,
21389  PH_PERF_SC6_FIFO_STATUS_3                = 0x000003fb,
21390  PH_PERF_SC7_FIFO_STATUS_0                = 0x000003fc,
21391  PH_PERF_SC7_FIFO_STATUS_1                = 0x000003fd,
21392  PH_PERF_SC7_FIFO_STATUS_2                = 0x000003fe,
21393  PH_PERF_SC7_FIFO_STATUS_3                = 0x000003ff,
21394  } PH_PERFCNT_SEL;
21395  
21396  /*
21397   * PhSPIstatusMode enum
21398   */
21399  
21400  typedef enum PhSPIstatusMode {
21401  PH_SPI_MODE_LARGEST_PA_PH_FIFO_COUNT     = 0x00000000,
21402  PH_SPI_MODE_ARBITER_SELECTED_PA_PH_FIFO_COUNT = 0x00000001,
21403  PH_SPI_MODE_DISABLED                     = 0x00000002,
21404  } PhSPIstatusMode;
21405  
21406  /*******************************************************
21407   * RMI Enums
21408   *******************************************************/
21409  
21410  /*
21411   * RMIPerfSel enum
21412   */
21413  
21414  typedef enum RMIPerfSel {
21415  RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID        = 0x00000000,
21416  RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID        = 0x00000001,
21417  } RMIPerfSel;
21418  
21419  /*******************************************************
21420   * PMM Enums
21421   *******************************************************/
21422  
21423  /*
21424   * GCRPerfSel enum
21425   */
21426  
21427  typedef enum GCRPerfSel {
21428  GCR_PERF_SEL_NONE                        = 0x00000000,
21429  GCR_PERF_SEL_SDMA0_ALL_REQ               = 0x00000001,
21430  GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ         = 0x00000002,
21431  GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ   = 0x00000003,
21432  GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ     = 0x00000004,
21433  GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ   = 0x00000005,
21434  GCR_PERF_SEL_SDMA0_GL2_ALL_REQ           = 0x00000006,
21435  GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ         = 0x00000007,
21436  GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ   = 0x00000008,
21437  GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ     = 0x00000009,
21438  GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ   = 0x0000000a,
21439  GCR_PERF_SEL_SDMA0_GL1_ALL_REQ           = 0x0000000b,
21440  GCR_PERF_SEL_SDMA0_METADATA_REQ          = 0x0000000c,
21441  GCR_PERF_SEL_SDMA0_SQC_DATA_REQ          = 0x0000000d,
21442  GCR_PERF_SEL_SDMA0_SQC_INST_REQ          = 0x0000000e,
21443  GCR_PERF_SEL_SDMA0_TCP_REQ               = 0x0000000f,
21444  GCR_PERF_SEL_SDMA0_TCP_TLB_SHOOTDOWN_REQ = 0x00000010,
21445  GCR_PERF_SEL_SDMA1_ALL_REQ               = 0x00000011,
21446  GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ         = 0x00000012,
21447  GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ   = 0x00000013,
21448  GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ     = 0x00000014,
21449  GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ   = 0x00000015,
21450  GCR_PERF_SEL_SDMA1_GL2_ALL_REQ           = 0x00000016,
21451  GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ         = 0x00000017,
21452  GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ   = 0x00000018,
21453  GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ     = 0x00000019,
21454  GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ   = 0x0000001a,
21455  GCR_PERF_SEL_SDMA1_GL1_ALL_REQ           = 0x0000001b,
21456  GCR_PERF_SEL_SDMA1_METADATA_REQ          = 0x0000001c,
21457  GCR_PERF_SEL_SDMA1_SQC_DATA_REQ          = 0x0000001d,
21458  GCR_PERF_SEL_SDMA1_SQC_INST_REQ          = 0x0000001e,
21459  GCR_PERF_SEL_SDMA1_TCP_REQ               = 0x0000001f,
21460  GCR_PERF_SEL_SDMA1_TCP_TLB_SHOOTDOWN_REQ = 0x00000020,
21461  GCR_PERF_SEL_CPC_ALL_REQ                 = 0x00000021,
21462  GCR_PERF_SEL_CPC_GL2_RANGE_REQ           = 0x00000022,
21463  GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ     = 0x00000023,
21464  GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ       = 0x00000024,
21465  GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ     = 0x00000025,
21466  GCR_PERF_SEL_CPC_GL2_ALL_REQ             = 0x00000026,
21467  GCR_PERF_SEL_CPC_GL1_RANGE_REQ           = 0x00000027,
21468  GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ     = 0x00000028,
21469  GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ       = 0x00000029,
21470  GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ     = 0x0000002a,
21471  GCR_PERF_SEL_CPC_GL1_ALL_REQ             = 0x0000002b,
21472  GCR_PERF_SEL_CPC_METADATA_REQ            = 0x0000002c,
21473  GCR_PERF_SEL_CPC_SQC_DATA_REQ            = 0x0000002d,
21474  GCR_PERF_SEL_CPC_SQC_INST_REQ            = 0x0000002e,
21475  GCR_PERF_SEL_CPC_TCP_REQ                 = 0x0000002f,
21476  GCR_PERF_SEL_CPC_TCP_TLB_SHOOTDOWN_REQ   = 0x00000030,
21477  GCR_PERF_SEL_CPG_ALL_REQ                 = 0x00000031,
21478  GCR_PERF_SEL_CPG_GL2_RANGE_REQ           = 0x00000032,
21479  GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ     = 0x00000033,
21480  GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ       = 0x00000034,
21481  GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ     = 0x00000035,
21482  GCR_PERF_SEL_CPG_GL2_ALL_REQ             = 0x00000036,
21483  GCR_PERF_SEL_CPG_GL1_RANGE_REQ           = 0x00000037,
21484  GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ     = 0x00000038,
21485  GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ       = 0x00000039,
21486  GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ     = 0x0000003a,
21487  GCR_PERF_SEL_CPG_GL1_ALL_REQ             = 0x0000003b,
21488  GCR_PERF_SEL_CPG_METADATA_REQ            = 0x0000003c,
21489  GCR_PERF_SEL_CPG_SQC_DATA_REQ            = 0x0000003d,
21490  GCR_PERF_SEL_CPG_SQC_INST_REQ            = 0x0000003e,
21491  GCR_PERF_SEL_CPG_TCP_REQ                 = 0x0000003f,
21492  GCR_PERF_SEL_CPG_TCP_TLB_SHOOTDOWN_REQ   = 0x00000040,
21493  GCR_PERF_SEL_CPF_ALL_REQ                 = 0x00000041,
21494  GCR_PERF_SEL_CPF_GL2_RANGE_REQ           = 0x00000042,
21495  GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ     = 0x00000043,
21496  GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ       = 0x00000044,
21497  GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ     = 0x00000045,
21498  GCR_PERF_SEL_CPF_GL2_ALL_REQ             = 0x00000046,
21499  GCR_PERF_SEL_CPF_GL1_RANGE_REQ           = 0x00000047,
21500  GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ     = 0x00000048,
21501  GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ       = 0x00000049,
21502  GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ     = 0x0000004a,
21503  GCR_PERF_SEL_CPF_GL1_ALL_REQ             = 0x0000004b,
21504  GCR_PERF_SEL_CPF_METADATA_REQ            = 0x0000004c,
21505  GCR_PERF_SEL_CPF_SQC_DATA_REQ            = 0x0000004d,
21506  GCR_PERF_SEL_CPF_SQC_INST_REQ            = 0x0000004e,
21507  GCR_PERF_SEL_CPF_TCP_REQ                 = 0x0000004f,
21508  GCR_PERF_SEL_CPF_TCP_TLB_SHOOTDOWN_REQ   = 0x00000050,
21509  GCR_PERF_SEL_VIRT_REQ                    = 0x00000051,
21510  GCR_PERF_SEL_PHY_REQ                     = 0x00000052,
21511  GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ     = 0x00000053,
21512  GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ     = 0x00000054,
21513  GCR_PERF_SEL_ALL_REQ                     = 0x00000055,
21514  GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ = 0x00000056,
21515  GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ = 0x00000057,
21516  GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ = 0x00000058,
21517  GCR_PERF_SEL_UTCL2_REQ                   = 0x00000059,
21518  GCR_PERF_SEL_UTCL2_RET                   = 0x0000005a,
21519  GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT   = 0x0000005b,
21520  GCR_PERF_SEL_UTCL2_INFLIGHT_REQ          = 0x0000005c,
21521  GCR_PERF_SEL_UTCL2_FILTERED_RET          = 0x0000005d,
21522  GCR_PERF_SEL_RLC_ALL_REQ                 = 0x0000005e,
21523  GCR_PERF_SEL_RLC_GL2_RANGE_REQ           = 0x0000005f,
21524  GCR_PERF_SEL_RLC_GL2_RANGE_LT16K_REQ     = 0x00000060,
21525  GCR_PERF_SEL_RLC_GL2_RANGE_16K_REQ       = 0x00000061,
21526  GCR_PERF_SEL_RLC_GL2_RANGE_GT16K_REQ     = 0x00000062,
21527  GCR_PERF_SEL_RLC_GL2_ALL_REQ             = 0x00000063,
21528  GCR_PERF_SEL_RLC_GL1_RANGE_REQ           = 0x00000064,
21529  GCR_PERF_SEL_RLC_GL1_RANGE_LT16K_REQ     = 0x00000065,
21530  GCR_PERF_SEL_RLC_GL1_RANGE_16K_REQ       = 0x00000066,
21531  GCR_PERF_SEL_RLC_GL1_RANGE_GT16K_REQ     = 0x00000067,
21532  GCR_PERF_SEL_RLC_GL1_ALL_REQ             = 0x00000068,
21533  GCR_PERF_SEL_RLC_METADATA_REQ            = 0x00000069,
21534  GCR_PERF_SEL_RLC_SQC_DATA_REQ            = 0x0000006a,
21535  GCR_PERF_SEL_RLC_SQC_INST_REQ            = 0x0000006b,
21536  GCR_PERF_SEL_RLC_TCP_REQ                 = 0x0000006c,
21537  GCR_PERF_SEL_RLC_TCP_TLB_SHOOTDOWN_REQ   = 0x0000006d,
21538  GCR_PERF_SEL_PM_ALL_REQ                  = 0x0000006e,
21539  GCR_PERF_SEL_PM_GL2_RANGE_REQ            = 0x0000006f,
21540  GCR_PERF_SEL_PM_GL2_RANGE_LT16K_REQ      = 0x00000070,
21541  GCR_PERF_SEL_PM_GL2_RANGE_16K_REQ        = 0x00000071,
21542  GCR_PERF_SEL_PM_GL2_RANGE_GT16K_REQ      = 0x00000072,
21543  GCR_PERF_SEL_PM_GL2_ALL_REQ              = 0x00000073,
21544  GCR_PERF_SEL_PM_GL1_RANGE_REQ            = 0x00000074,
21545  GCR_PERF_SEL_PM_GL1_RANGE_LT16K_REQ      = 0x00000075,
21546  GCR_PERF_SEL_PM_GL1_RANGE_16K_REQ        = 0x00000076,
21547  GCR_PERF_SEL_PM_GL1_RANGE_GT16K_REQ      = 0x00000077,
21548  GCR_PERF_SEL_PM_GL1_ALL_REQ              = 0x00000078,
21549  GCR_PERF_SEL_PM_METADATA_REQ             = 0x00000079,
21550  GCR_PERF_SEL_PM_SQC_DATA_REQ             = 0x0000007a,
21551  GCR_PERF_SEL_PM_SQC_INST_REQ             = 0x0000007b,
21552  GCR_PERF_SEL_PM_TCP_REQ                  = 0x0000007c,
21553  GCR_PERF_SEL_PM_TCP_TLB_SHOOTDOWN_REQ    = 0x0000007d,
21554  GCR_PERF_SEL_PIO_ALL_REQ                 = 0x0000007e,
21555  GCR_PERF_SEL_PIO_GL2_RANGE_REQ           = 0x0000007f,
21556  GCR_PERF_SEL_PIO_GL2_RANGE_LT16K_REQ     = 0x00000080,
21557  GCR_PERF_SEL_PIO_GL2_RANGE_16K_REQ       = 0x00000081,
21558  GCR_PERF_SEL_PIO_GL2_RANGE_GT16K_REQ     = 0x00000082,
21559  GCR_PERF_SEL_PIO_GL2_ALL_REQ             = 0x00000083,
21560  GCR_PERF_SEL_PIO_GL1_RANGE_REQ           = 0x00000084,
21561  GCR_PERF_SEL_PIO_GL1_RANGE_LT16K_REQ     = 0x00000085,
21562  GCR_PERF_SEL_PIO_GL1_RANGE_16K_REQ       = 0x00000086,
21563  GCR_PERF_SEL_PIO_GL1_RANGE_GT16K_REQ     = 0x00000087,
21564  GCR_PERF_SEL_PIO_GL1_ALL_REQ             = 0x00000088,
21565  GCR_PERF_SEL_PIO_METADATA_REQ            = 0x00000089,
21566  GCR_PERF_SEL_PIO_SQC_DATA_REQ            = 0x0000008a,
21567  GCR_PERF_SEL_PIO_SQC_INST_REQ            = 0x0000008b,
21568  GCR_PERF_SEL_PIO_TCP_REQ                 = 0x0000008c,
21569  GCR_PERF_SEL_PIO_TCP_TLB_SHOOTDOWN_REQ   = 0x0000008d,
21570  } GCRPerfSel;
21571  
21572  /*******************************************************
21573   * UTCL1 Enums
21574   *******************************************************/
21575  
21576  /*
21577   * UTCL1PerfSel enum
21578   */
21579  
21580  typedef enum UTCL1PerfSel {
21581  UTCL1_PERF_SEL_NONE                      = 0x00000000,
21582  UTCL1_PERF_SEL_REQS                      = 0x00000001,
21583  UTCL1_PERF_SEL_HITS                      = 0x00000002,
21584  UTCL1_PERF_SEL_MISSES                    = 0x00000003,
21585  UTCL1_PERF_SEL_MH_RECENT_BUF_HIT         = 0x00000004,
21586  UTCL1_PERF_SEL_MH_DUPLICATE_DETECT       = 0x00000005,
21587  UTCL1_PERF_SEL_UTCL2_REQS                = 0x00000006,
21588  UTCL1_PERF_SEL_UTCL2_RET_XNACK_RETRY     = 0x00000007,
21589  UTCL1_PERF_SEL_UTCL2_RET_FAULT           = 0x00000008,
21590  UTCL1_PERF_SEL_STALL_UTCL2_CREDITS       = 0x00000009,
21591  UTCL1_PERF_SEL_STALL_MH_FULL             = 0x0000000a,
21592  UTCL1_PERF_SEL_UTCL2_REQS_OUTSTANDING_ACCUM = 0x0000000b,
21593  UTCL1_PERF_SEL_UTCL2_RET_CNT             = 0x0000000c,
21594  UTCL1_PERF_SEL_RTNS                      = 0x0000000d,
21595  UTCL1_PERF_SEL_XLAT_REQ_BUSY             = 0x0000000e,
21596  UTCL1_PERF_SEL_BYPASS_REQS               = 0x0000000f,
21597  UTCL1_PERF_SEL_HIT_INV_FILTER_REQS       = 0x00000010,
21598  UTCL1_PERF_SEL_UTCL2_RET_PERM_FAULT      = 0x00000011,
21599  UTCL1_PERF_SEL_UTCL2_RET_PRT_FAULT       = 0x00000012,
21600  UTCL1_PERF_SEL_CP_INVREQS                = 0x00000013,
21601  UTCL1_PERF_SEL_UTCL2_UTCL1_INVREQS       = 0x00000014,
21602  UTCL1_PERF_SEL_RANGE_INVREQS             = 0x00000015,
21603  UTCL1_PERF_SEL_INV_ALL_VMID_INVREQS      = 0x00000016,
21604  } UTCL1PerfSel;
21605  
21606  /*******************************************************
21607   * IH Enums
21608   *******************************************************/
21609  
21610  /*
21611   * IH_CLIENT_TYPE enum
21612   */
21613  
21614  typedef enum IH_CLIENT_TYPE {
21615  IH_GFX_VMID_CLIENT                       = 0x00000000,
21616  IH_MM_VMID_CLIENT                        = 0x00000001,
21617  IH_MULTI_VMID_CLIENT                     = 0x00000002,
21618  IH_CLIENT_TYPE_RESERVED                  = 0x00000003,
21619  } IH_CLIENT_TYPE;
21620  
21621  /*
21622   * IH_INTERFACE_TYPE enum
21623   */
21624  
21625  typedef enum IH_INTERFACE_TYPE {
21626  IH_LEGACY_INTERFACE                      = 0x00000000,
21627  IH_REGISTER_WRITE_INTERFACE              = 0x00000001,
21628  } IH_INTERFACE_TYPE;
21629  
21630  /*
21631   * IH_PERF_SEL enum
21632   */
21633  
21634  typedef enum IH_PERF_SEL {
21635  IH_PERF_SEL_CYCLE                        = 0x00000000,
21636  IH_PERF_SEL_IDLE                         = 0x00000001,
21637  IH_PERF_SEL_INPUT_IDLE                   = 0x00000002,
21638  IH_PERF_SEL_BUFFER_IDLE                  = 0x00000003,
21639  IH_PERF_SEL_RB0_FULL                     = 0x00000004,
21640  IH_PERF_SEL_RB0_OVERFLOW                 = 0x00000005,
21641  IH_PERF_SEL_RB0_WPTR_WRITEBACK           = 0x00000006,
21642  IH_PERF_SEL_RB0_WPTR_WRAP                = 0x00000007,
21643  IH_PERF_SEL_RB0_RPTR_WRAP                = 0x00000008,
21644  IH_PERF_SEL_MC_WR_IDLE                   = 0x00000009,
21645  IH_PERF_SEL_MC_WR_COUNT                  = 0x0000000a,
21646  IH_PERF_SEL_MC_WR_STALL                  = 0x0000000b,
21647  IH_PERF_SEL_MC_WR_CLEAN_PENDING          = 0x0000000c,
21648  IH_PERF_SEL_MC_WR_CLEAN_STALL            = 0x0000000d,
21649  IH_PERF_SEL_BIF_LINE0_RISING             = 0x0000000e,
21650  IH_PERF_SEL_BIF_LINE0_FALLING            = 0x0000000f,
21651  IH_PERF_SEL_RB1_FULL                     = 0x00000010,
21652  IH_PERF_SEL_RB1_OVERFLOW                 = 0x00000011,
21653  IH_PERF_SEL_COOKIE_REC_ERROR             = 0x00000012,
21654  IH_PERF_SEL_RB1_WPTR_WRAP                = 0x00000013,
21655  IH_PERF_SEL_RB1_RPTR_WRAP                = 0x00000014,
21656  IH_PERF_SEL_RB2_FULL                     = 0x00000015,
21657  IH_PERF_SEL_RB2_OVERFLOW                 = 0x00000016,
21658  IH_PERF_SEL_CLIENT_CREDIT_ERROR          = 0x00000017,
21659  IH_PERF_SEL_RB2_WPTR_WRAP                = 0x00000018,
21660  IH_PERF_SEL_RB2_RPTR_WRAP                = 0x00000019,
21661  IH_PERF_SEL_STORM_CLIENT_INT_DROP        = 0x0000001a,
21662  IH_PERF_SEL_SELF_IV_VALID                = 0x0000001b,
21663  IH_PERF_SEL_BUFFER_FIFO_FULL             = 0x0000001c,
21664  IH_PERF_SEL_RB0_FULL_VF0                 = 0x0000001d,
21665  IH_PERF_SEL_RB0_FULL_VF1                 = 0x0000001e,
21666  IH_PERF_SEL_RB0_FULL_VF2                 = 0x0000001f,
21667  IH_PERF_SEL_RB0_FULL_VF3                 = 0x00000020,
21668  IH_PERF_SEL_RB0_FULL_VF4                 = 0x00000021,
21669  IH_PERF_SEL_RB0_FULL_VF5                 = 0x00000022,
21670  IH_PERF_SEL_RB0_FULL_VF6                 = 0x00000023,
21671  IH_PERF_SEL_RB0_FULL_VF7                 = 0x00000024,
21672  IH_PERF_SEL_RB0_FULL_VF8                 = 0x00000025,
21673  IH_PERF_SEL_RB0_FULL_VF9                 = 0x00000026,
21674  IH_PERF_SEL_RB0_FULL_VF10                = 0x00000027,
21675  IH_PERF_SEL_RB0_FULL_VF11                = 0x00000028,
21676  IH_PERF_SEL_RB0_FULL_VF12                = 0x00000029,
21677  IH_PERF_SEL_RB0_FULL_VF13                = 0x0000002a,
21678  IH_PERF_SEL_RB0_FULL_VF14                = 0x0000002b,
21679  IH_PERF_SEL_RB0_FULL_VF15                = 0x0000002c,
21680  IH_PERF_SEL_RB0_OVERFLOW_VF0             = 0x0000002d,
21681  IH_PERF_SEL_RB0_OVERFLOW_VF1             = 0x0000002e,
21682  IH_PERF_SEL_RB0_OVERFLOW_VF2             = 0x0000002f,
21683  IH_PERF_SEL_RB0_OVERFLOW_VF3             = 0x00000030,
21684  IH_PERF_SEL_RB0_OVERFLOW_VF4             = 0x00000031,
21685  IH_PERF_SEL_RB0_OVERFLOW_VF5             = 0x00000032,
21686  IH_PERF_SEL_RB0_OVERFLOW_VF6             = 0x00000033,
21687  IH_PERF_SEL_RB0_OVERFLOW_VF7             = 0x00000034,
21688  IH_PERF_SEL_RB0_OVERFLOW_VF8             = 0x00000035,
21689  IH_PERF_SEL_RB0_OVERFLOW_VF9             = 0x00000036,
21690  IH_PERF_SEL_RB0_OVERFLOW_VF10            = 0x00000037,
21691  IH_PERF_SEL_RB0_OVERFLOW_VF11            = 0x00000038,
21692  IH_PERF_SEL_RB0_OVERFLOW_VF12            = 0x00000039,
21693  IH_PERF_SEL_RB0_OVERFLOW_VF13            = 0x0000003a,
21694  IH_PERF_SEL_RB0_OVERFLOW_VF14            = 0x0000003b,
21695  IH_PERF_SEL_RB0_OVERFLOW_VF15            = 0x0000003c,
21696  IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0       = 0x0000003d,
21697  IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1       = 0x0000003e,
21698  IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2       = 0x0000003f,
21699  IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3       = 0x00000040,
21700  IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4       = 0x00000041,
21701  IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5       = 0x00000042,
21702  IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6       = 0x00000043,
21703  IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7       = 0x00000044,
21704  IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8       = 0x00000045,
21705  IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9       = 0x00000046,
21706  IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10      = 0x00000047,
21707  IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11      = 0x00000048,
21708  IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12      = 0x00000049,
21709  IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13      = 0x0000004a,
21710  IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14      = 0x0000004b,
21711  IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15      = 0x0000004c,
21712  IH_PERF_SEL_RB0_WPTR_WRAP_VF0            = 0x0000004d,
21713  IH_PERF_SEL_RB0_WPTR_WRAP_VF1            = 0x0000004e,
21714  IH_PERF_SEL_RB0_WPTR_WRAP_VF2            = 0x0000004f,
21715  IH_PERF_SEL_RB0_WPTR_WRAP_VF3            = 0x00000050,
21716  IH_PERF_SEL_RB0_WPTR_WRAP_VF4            = 0x00000051,
21717  IH_PERF_SEL_RB0_WPTR_WRAP_VF5            = 0x00000052,
21718  IH_PERF_SEL_RB0_WPTR_WRAP_VF6            = 0x00000053,
21719  IH_PERF_SEL_RB0_WPTR_WRAP_VF7            = 0x00000054,
21720  IH_PERF_SEL_RB0_WPTR_WRAP_VF8            = 0x00000055,
21721  IH_PERF_SEL_RB0_WPTR_WRAP_VF9            = 0x00000056,
21722  IH_PERF_SEL_RB0_WPTR_WRAP_VF10           = 0x00000057,
21723  IH_PERF_SEL_RB0_WPTR_WRAP_VF11           = 0x00000058,
21724  IH_PERF_SEL_RB0_WPTR_WRAP_VF12           = 0x00000059,
21725  IH_PERF_SEL_RB0_WPTR_WRAP_VF13           = 0x0000005a,
21726  IH_PERF_SEL_RB0_WPTR_WRAP_VF14           = 0x0000005b,
21727  IH_PERF_SEL_RB0_WPTR_WRAP_VF15           = 0x0000005c,
21728  IH_PERF_SEL_RB0_RPTR_WRAP_VF0            = 0x0000005d,
21729  IH_PERF_SEL_RB0_RPTR_WRAP_VF1            = 0x0000005e,
21730  IH_PERF_SEL_RB0_RPTR_WRAP_VF2            = 0x0000005f,
21731  IH_PERF_SEL_RB0_RPTR_WRAP_VF3            = 0x00000060,
21732  IH_PERF_SEL_RB0_RPTR_WRAP_VF4            = 0x00000061,
21733  IH_PERF_SEL_RB0_RPTR_WRAP_VF5            = 0x00000062,
21734  IH_PERF_SEL_RB0_RPTR_WRAP_VF6            = 0x00000063,
21735  IH_PERF_SEL_RB0_RPTR_WRAP_VF7            = 0x00000064,
21736  IH_PERF_SEL_RB0_RPTR_WRAP_VF8            = 0x00000065,
21737  IH_PERF_SEL_RB0_RPTR_WRAP_VF9            = 0x00000066,
21738  IH_PERF_SEL_RB0_RPTR_WRAP_VF10           = 0x00000067,
21739  IH_PERF_SEL_RB0_RPTR_WRAP_VF11           = 0x00000068,
21740  IH_PERF_SEL_RB0_RPTR_WRAP_VF12           = 0x00000069,
21741  IH_PERF_SEL_RB0_RPTR_WRAP_VF13           = 0x0000006a,
21742  IH_PERF_SEL_RB0_RPTR_WRAP_VF14           = 0x0000006b,
21743  IH_PERF_SEL_RB0_RPTR_WRAP_VF15           = 0x0000006c,
21744  IH_PERF_SEL_BIF_LINE0_RISING_VF0         = 0x0000006d,
21745  IH_PERF_SEL_BIF_LINE0_RISING_VF1         = 0x0000006e,
21746  IH_PERF_SEL_BIF_LINE0_RISING_VF2         = 0x0000006f,
21747  IH_PERF_SEL_BIF_LINE0_RISING_VF3         = 0x00000070,
21748  IH_PERF_SEL_BIF_LINE0_RISING_VF4         = 0x00000071,
21749  IH_PERF_SEL_BIF_LINE0_RISING_VF5         = 0x00000072,
21750  IH_PERF_SEL_BIF_LINE0_RISING_VF6         = 0x00000073,
21751  IH_PERF_SEL_BIF_LINE0_RISING_VF7         = 0x00000074,
21752  IH_PERF_SEL_BIF_LINE0_RISING_VF8         = 0x00000075,
21753  IH_PERF_SEL_BIF_LINE0_RISING_VF9         = 0x00000076,
21754  IH_PERF_SEL_BIF_LINE0_RISING_VF10        = 0x00000077,
21755  IH_PERF_SEL_BIF_LINE0_RISING_VF11        = 0x00000078,
21756  IH_PERF_SEL_BIF_LINE0_RISING_VF12        = 0x00000079,
21757  IH_PERF_SEL_BIF_LINE0_RISING_VF13        = 0x0000007a,
21758  IH_PERF_SEL_BIF_LINE0_RISING_VF14        = 0x0000007b,
21759  IH_PERF_SEL_BIF_LINE0_RISING_VF15        = 0x0000007c,
21760  IH_PERF_SEL_BIF_LINE0_FALLING_VF0        = 0x0000007d,
21761  IH_PERF_SEL_BIF_LINE0_FALLING_VF1        = 0x0000007e,
21762  IH_PERF_SEL_BIF_LINE0_FALLING_VF2        = 0x0000007f,
21763  IH_PERF_SEL_BIF_LINE0_FALLING_VF3        = 0x00000080,
21764  IH_PERF_SEL_BIF_LINE0_FALLING_VF4        = 0x00000081,
21765  IH_PERF_SEL_BIF_LINE0_FALLING_VF5        = 0x00000082,
21766  IH_PERF_SEL_BIF_LINE0_FALLING_VF6        = 0x00000083,
21767  IH_PERF_SEL_BIF_LINE0_FALLING_VF7        = 0x00000084,
21768  IH_PERF_SEL_BIF_LINE0_FALLING_VF8        = 0x00000085,
21769  IH_PERF_SEL_BIF_LINE0_FALLING_VF9        = 0x00000086,
21770  IH_PERF_SEL_BIF_LINE0_FALLING_VF10       = 0x00000087,
21771  IH_PERF_SEL_BIF_LINE0_FALLING_VF11       = 0x00000088,
21772  IH_PERF_SEL_BIF_LINE0_FALLING_VF12       = 0x00000089,
21773  IH_PERF_SEL_BIF_LINE0_FALLING_VF13       = 0x0000008a,
21774  IH_PERF_SEL_BIF_LINE0_FALLING_VF14       = 0x0000008b,
21775  IH_PERF_SEL_BIF_LINE0_FALLING_VF15       = 0x0000008c,
21776  IH_PERF_SEL_CLIENT0_INT                  = 0x0000008d,
21777  IH_PERF_SEL_CLIENT1_INT                  = 0x0000008e,
21778  IH_PERF_SEL_CLIENT2_INT                  = 0x0000008f,
21779  IH_PERF_SEL_CLIENT3_INT                  = 0x00000090,
21780  IH_PERF_SEL_CLIENT4_INT                  = 0x00000091,
21781  IH_PERF_SEL_CLIENT5_INT                  = 0x00000092,
21782  IH_PERF_SEL_CLIENT6_INT                  = 0x00000093,
21783  IH_PERF_SEL_CLIENT7_INT                  = 0x00000094,
21784  IH_PERF_SEL_CLIENT8_INT                  = 0x00000095,
21785  IH_PERF_SEL_CLIENT9_INT                  = 0x00000096,
21786  IH_PERF_SEL_CLIENT10_INT                 = 0x00000097,
21787  IH_PERF_SEL_CLIENT11_INT                 = 0x00000098,
21788  IH_PERF_SEL_CLIENT12_INT                 = 0x00000099,
21789  IH_PERF_SEL_CLIENT13_INT                 = 0x0000009a,
21790  IH_PERF_SEL_CLIENT14_INT                 = 0x0000009b,
21791  IH_PERF_SEL_CLIENT15_INT                 = 0x0000009c,
21792  IH_PERF_SEL_CLIENT16_INT                 = 0x0000009d,
21793  IH_PERF_SEL_CLIENT17_INT                 = 0x0000009e,
21794  IH_PERF_SEL_CLIENT18_INT                 = 0x0000009f,
21795  IH_PERF_SEL_CLIENT19_INT                 = 0x000000a0,
21796  IH_PERF_SEL_CLIENT20_INT                 = 0x000000a1,
21797  IH_PERF_SEL_CLIENT21_INT                 = 0x000000a2,
21798  IH_PERF_SEL_CLIENT22_INT                 = 0x000000a3,
21799  IH_PERF_SEL_CLIENT23_INT                 = 0x000000a4,
21800  IH_PERF_SEL_CLIENT24_INT                 = 0x000000a5,
21801  IH_PERF_SEL_CLIENT25_INT                 = 0x000000a6,
21802  IH_PERF_SEL_CLIENT26_INT                 = 0x000000a7,
21803  IH_PERF_SEL_CLIENT27_INT                 = 0x000000a8,
21804  IH_PERF_SEL_CLIENT28_INT                 = 0x000000a9,
21805  IH_PERF_SEL_CLIENT29_INT                 = 0x000000aa,
21806  IH_PERF_SEL_CLIENT30_INT                 = 0x000000ab,
21807  IH_PERF_SEL_CLIENT31_INT                 = 0x000000ac,
21808  IH_PERF_SEL_RB1_FULL_VF0                 = 0x000000ad,
21809  IH_PERF_SEL_RB1_FULL_VF1                 = 0x000000ae,
21810  IH_PERF_SEL_RB1_FULL_VF2                 = 0x000000af,
21811  IH_PERF_SEL_RB1_FULL_VF3                 = 0x000000b0,
21812  IH_PERF_SEL_RB1_FULL_VF4                 = 0x000000b1,
21813  IH_PERF_SEL_RB1_FULL_VF5                 = 0x000000b2,
21814  IH_PERF_SEL_RB1_FULL_VF6                 = 0x000000b3,
21815  IH_PERF_SEL_RB1_FULL_VF7                 = 0x000000b4,
21816  IH_PERF_SEL_RB1_FULL_VF8                 = 0x000000b5,
21817  IH_PERF_SEL_RB1_FULL_VF9                 = 0x000000b6,
21818  IH_PERF_SEL_RB1_FULL_VF10                = 0x000000b7,
21819  IH_PERF_SEL_RB1_FULL_VF11                = 0x000000b8,
21820  IH_PERF_SEL_RB1_FULL_VF12                = 0x000000b9,
21821  IH_PERF_SEL_RB1_FULL_VF13                = 0x000000ba,
21822  IH_PERF_SEL_RB1_FULL_VF14                = 0x000000bb,
21823  IH_PERF_SEL_RB1_FULL_VF15                = 0x000000bc,
21824  IH_PERF_SEL_RB1_OVERFLOW_VF0             = 0x000000bd,
21825  IH_PERF_SEL_RB1_OVERFLOW_VF1             = 0x000000be,
21826  IH_PERF_SEL_RB1_OVERFLOW_VF2             = 0x000000bf,
21827  IH_PERF_SEL_RB1_OVERFLOW_VF3             = 0x000000c0,
21828  IH_PERF_SEL_RB1_OVERFLOW_VF4             = 0x000000c1,
21829  IH_PERF_SEL_RB1_OVERFLOW_VF5             = 0x000000c2,
21830  IH_PERF_SEL_RB1_OVERFLOW_VF6             = 0x000000c3,
21831  IH_PERF_SEL_RB1_OVERFLOW_VF7             = 0x000000c4,
21832  IH_PERF_SEL_RB1_OVERFLOW_VF8             = 0x000000c5,
21833  IH_PERF_SEL_RB1_OVERFLOW_VF9             = 0x000000c6,
21834  IH_PERF_SEL_RB1_OVERFLOW_VF10            = 0x000000c7,
21835  IH_PERF_SEL_RB1_OVERFLOW_VF11            = 0x000000c8,
21836  IH_PERF_SEL_RB1_OVERFLOW_VF12            = 0x000000c9,
21837  IH_PERF_SEL_RB1_OVERFLOW_VF13            = 0x000000ca,
21838  IH_PERF_SEL_RB1_OVERFLOW_VF14            = 0x000000cb,
21839  IH_PERF_SEL_RB1_OVERFLOW_VF15            = 0x000000cc,
21840  IH_PERF_SEL_RB1_WPTR_WRAP_VF0            = 0x000000cd,
21841  IH_PERF_SEL_RB1_WPTR_WRAP_VF1            = 0x000000ce,
21842  IH_PERF_SEL_RB1_WPTR_WRAP_VF2            = 0x000000cf,
21843  IH_PERF_SEL_RB1_WPTR_WRAP_VF3            = 0x000000d0,
21844  IH_PERF_SEL_RB1_WPTR_WRAP_VF4            = 0x000000d1,
21845  IH_PERF_SEL_RB1_WPTR_WRAP_VF5            = 0x000000d2,
21846  IH_PERF_SEL_RB1_WPTR_WRAP_VF6            = 0x000000d3,
21847  IH_PERF_SEL_RB1_WPTR_WRAP_VF7            = 0x000000d4,
21848  IH_PERF_SEL_RB1_WPTR_WRAP_VF8            = 0x000000d5,
21849  IH_PERF_SEL_RB1_WPTR_WRAP_VF9            = 0x000000d6,
21850  IH_PERF_SEL_RB1_WPTR_WRAP_VF10           = 0x000000d7,
21851  IH_PERF_SEL_RB1_WPTR_WRAP_VF11           = 0x000000d8,
21852  IH_PERF_SEL_RB1_WPTR_WRAP_VF12           = 0x000000d9,
21853  IH_PERF_SEL_RB1_WPTR_WRAP_VF13           = 0x000000da,
21854  IH_PERF_SEL_RB1_WPTR_WRAP_VF14           = 0x000000db,
21855  IH_PERF_SEL_RB1_WPTR_WRAP_VF15           = 0x000000dc,
21856  IH_PERF_SEL_RB1_RPTR_WRAP_VF0            = 0x000000dd,
21857  IH_PERF_SEL_RB1_RPTR_WRAP_VF1            = 0x000000de,
21858  IH_PERF_SEL_RB1_RPTR_WRAP_VF2            = 0x000000df,
21859  IH_PERF_SEL_RB1_RPTR_WRAP_VF3            = 0x000000e0,
21860  IH_PERF_SEL_RB1_RPTR_WRAP_VF4            = 0x000000e1,
21861  IH_PERF_SEL_RB1_RPTR_WRAP_VF5            = 0x000000e2,
21862  IH_PERF_SEL_RB1_RPTR_WRAP_VF6            = 0x000000e3,
21863  IH_PERF_SEL_RB1_RPTR_WRAP_VF7            = 0x000000e4,
21864  IH_PERF_SEL_RB1_RPTR_WRAP_VF8            = 0x000000e5,
21865  IH_PERF_SEL_RB1_RPTR_WRAP_VF9            = 0x000000e6,
21866  IH_PERF_SEL_RB1_RPTR_WRAP_VF10           = 0x000000e7,
21867  IH_PERF_SEL_RB1_RPTR_WRAP_VF11           = 0x000000e8,
21868  IH_PERF_SEL_RB1_RPTR_WRAP_VF12           = 0x000000e9,
21869  IH_PERF_SEL_RB1_RPTR_WRAP_VF13           = 0x000000ea,
21870  IH_PERF_SEL_RB1_RPTR_WRAP_VF14           = 0x000000eb,
21871  IH_PERF_SEL_RB1_RPTR_WRAP_VF15           = 0x000000ec,
21872  IH_PERF_SEL_RB2_FULL_VF0                 = 0x000000ed,
21873  IH_PERF_SEL_RB2_FULL_VF1                 = 0x000000ee,
21874  IH_PERF_SEL_RB2_FULL_VF2                 = 0x000000ef,
21875  IH_PERF_SEL_RB2_FULL_VF3                 = 0x000000f0,
21876  IH_PERF_SEL_RB2_FULL_VF4                 = 0x000000f1,
21877  IH_PERF_SEL_RB2_FULL_VF5                 = 0x000000f2,
21878  IH_PERF_SEL_RB2_FULL_VF6                 = 0x000000f3,
21879  IH_PERF_SEL_RB2_FULL_VF7                 = 0x000000f4,
21880  IH_PERF_SEL_RB2_FULL_VF8                 = 0x000000f5,
21881  IH_PERF_SEL_RB2_FULL_VF9                 = 0x000000f6,
21882  IH_PERF_SEL_RB2_FULL_VF10                = 0x000000f7,
21883  IH_PERF_SEL_RB2_FULL_VF11                = 0x000000f8,
21884  IH_PERF_SEL_RB2_FULL_VF12                = 0x000000f9,
21885  IH_PERF_SEL_RB2_FULL_VF13                = 0x000000fa,
21886  IH_PERF_SEL_RB2_FULL_VF14                = 0x000000fb,
21887  IH_PERF_SEL_RB2_FULL_VF15                = 0x000000fc,
21888  IH_PERF_SEL_RB2_OVERFLOW_VF0             = 0x000000fd,
21889  IH_PERF_SEL_RB2_OVERFLOW_VF1             = 0x000000fe,
21890  IH_PERF_SEL_RB2_OVERFLOW_VF2             = 0x000000ff,
21891  IH_PERF_SEL_RB2_OVERFLOW_VF3             = 0x00000100,
21892  IH_PERF_SEL_RB2_OVERFLOW_VF4             = 0x00000101,
21893  IH_PERF_SEL_RB2_OVERFLOW_VF5             = 0x00000102,
21894  IH_PERF_SEL_RB2_OVERFLOW_VF6             = 0x00000103,
21895  IH_PERF_SEL_RB2_OVERFLOW_VF7             = 0x00000104,
21896  IH_PERF_SEL_RB2_OVERFLOW_VF8             = 0x00000105,
21897  IH_PERF_SEL_RB2_OVERFLOW_VF9             = 0x00000106,
21898  IH_PERF_SEL_RB2_OVERFLOW_VF10            = 0x00000107,
21899  IH_PERF_SEL_RB2_OVERFLOW_VF11            = 0x00000108,
21900  IH_PERF_SEL_RB2_OVERFLOW_VF12            = 0x00000109,
21901  IH_PERF_SEL_RB2_OVERFLOW_VF13            = 0x0000010a,
21902  IH_PERF_SEL_RB2_OVERFLOW_VF14            = 0x0000010b,
21903  IH_PERF_SEL_RB2_OVERFLOW_VF15            = 0x0000010c,
21904  IH_PERF_SEL_RB2_WPTR_WRAP_VF0            = 0x0000010d,
21905  IH_PERF_SEL_RB2_WPTR_WRAP_VF1            = 0x0000010e,
21906  IH_PERF_SEL_RB2_WPTR_WRAP_VF2            = 0x0000010f,
21907  IH_PERF_SEL_RB2_WPTR_WRAP_VF3            = 0x00000110,
21908  IH_PERF_SEL_RB2_WPTR_WRAP_VF4            = 0x00000111,
21909  IH_PERF_SEL_RB2_WPTR_WRAP_VF5            = 0x00000112,
21910  IH_PERF_SEL_RB2_WPTR_WRAP_VF6            = 0x00000113,
21911  IH_PERF_SEL_RB2_WPTR_WRAP_VF7            = 0x00000114,
21912  IH_PERF_SEL_RB2_WPTR_WRAP_VF8            = 0x00000115,
21913  IH_PERF_SEL_RB2_WPTR_WRAP_VF9            = 0x00000116,
21914  IH_PERF_SEL_RB2_WPTR_WRAP_VF10           = 0x00000117,
21915  IH_PERF_SEL_RB2_WPTR_WRAP_VF11           = 0x00000118,
21916  IH_PERF_SEL_RB2_WPTR_WRAP_VF12           = 0x00000119,
21917  IH_PERF_SEL_RB2_WPTR_WRAP_VF13           = 0x0000011a,
21918  IH_PERF_SEL_RB2_WPTR_WRAP_VF14           = 0x0000011b,
21919  IH_PERF_SEL_RB2_WPTR_WRAP_VF15           = 0x0000011c,
21920  IH_PERF_SEL_RB2_RPTR_WRAP_VF0            = 0x0000011d,
21921  IH_PERF_SEL_RB2_RPTR_WRAP_VF1            = 0x0000011e,
21922  IH_PERF_SEL_RB2_RPTR_WRAP_VF2            = 0x0000011f,
21923  IH_PERF_SEL_RB2_RPTR_WRAP_VF3            = 0x00000120,
21924  IH_PERF_SEL_RB2_RPTR_WRAP_VF4            = 0x00000121,
21925  IH_PERF_SEL_RB2_RPTR_WRAP_VF5            = 0x00000122,
21926  IH_PERF_SEL_RB2_RPTR_WRAP_VF6            = 0x00000123,
21927  IH_PERF_SEL_RB2_RPTR_WRAP_VF7            = 0x00000124,
21928  IH_PERF_SEL_RB2_RPTR_WRAP_VF8            = 0x00000125,
21929  IH_PERF_SEL_RB2_RPTR_WRAP_VF9            = 0x00000126,
21930  IH_PERF_SEL_RB2_RPTR_WRAP_VF10           = 0x00000127,
21931  IH_PERF_SEL_RB2_RPTR_WRAP_VF11           = 0x00000128,
21932  IH_PERF_SEL_RB2_RPTR_WRAP_VF12           = 0x00000129,
21933  IH_PERF_SEL_RB2_RPTR_WRAP_VF13           = 0x0000012a,
21934  IH_PERF_SEL_RB2_RPTR_WRAP_VF14           = 0x0000012b,
21935  IH_PERF_SEL_RB2_RPTR_WRAP_VF15           = 0x0000012c,
21936  IH_PERF_SEL_RB0_FULL_DRAIN_DROP          = 0x0000012d,
21937  IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF0      = 0x0000012e,
21938  IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF1      = 0x0000012f,
21939  IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF2      = 0x00000130,
21940  IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF3      = 0x00000131,
21941  IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF4      = 0x00000132,
21942  IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF5      = 0x00000133,
21943  IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF6      = 0x00000134,
21944  IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF7      = 0x00000135,
21945  IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF8      = 0x00000136,
21946  IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF9      = 0x00000137,
21947  IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF10     = 0x00000138,
21948  IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF11     = 0x00000139,
21949  IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF12     = 0x0000013a,
21950  IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF13     = 0x0000013b,
21951  IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF14     = 0x0000013c,
21952  IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF15     = 0x0000013d,
21953  IH_PERF_SEL_RB1_FULL_DRAIN_DROP          = 0x0000013e,
21954  IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF0      = 0x0000013f,
21955  IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF1      = 0x00000140,
21956  IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF2      = 0x00000141,
21957  IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF3      = 0x00000142,
21958  IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF4      = 0x00000143,
21959  IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF5      = 0x00000144,
21960  IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF6      = 0x00000145,
21961  IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF7      = 0x00000146,
21962  IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF8      = 0x00000147,
21963  IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF9      = 0x00000148,
21964  IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF10     = 0x00000149,
21965  IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF11     = 0x0000014a,
21966  IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF12     = 0x0000014b,
21967  IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF13     = 0x0000014c,
21968  IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF14     = 0x0000014d,
21969  IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF15     = 0x0000014e,
21970  IH_PERF_SEL_RB2_FULL_DRAIN_DROP          = 0x0000014f,
21971  IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF0      = 0x00000150,
21972  IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF1      = 0x00000151,
21973  IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF2      = 0x00000152,
21974  IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF3      = 0x00000153,
21975  IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF4      = 0x00000154,
21976  IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF5      = 0x00000155,
21977  IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF6      = 0x00000156,
21978  IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF7      = 0x00000157,
21979  IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF8      = 0x00000158,
21980  IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF9      = 0x00000159,
21981  IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF10     = 0x0000015a,
21982  IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF11     = 0x0000015b,
21983  IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF12     = 0x0000015c,
21984  IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF13     = 0x0000015d,
21985  IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF14     = 0x0000015e,
21986  IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF15     = 0x0000015f,
21987  IH_PERF_SEL_RB0_LOAD_RPTR                = 0x00000160,
21988  IH_PERF_SEL_RB0_LOAD_RPTR_VF0            = 0x00000161,
21989  IH_PERF_SEL_RB0_LOAD_RPTR_VF1            = 0x00000162,
21990  IH_PERF_SEL_RB0_LOAD_RPTR_VF2            = 0x00000163,
21991  IH_PERF_SEL_RB0_LOAD_RPTR_VF3            = 0x00000164,
21992  IH_PERF_SEL_RB0_LOAD_RPTR_VF4            = 0x00000165,
21993  IH_PERF_SEL_RB0_LOAD_RPTR_VF5            = 0x00000166,
21994  IH_PERF_SEL_RB0_LOAD_RPTR_VF6            = 0x00000167,
21995  IH_PERF_SEL_RB0_LOAD_RPTR_VF7            = 0x00000168,
21996  IH_PERF_SEL_RB0_LOAD_RPTR_VF8            = 0x00000169,
21997  IH_PERF_SEL_RB0_LOAD_RPTR_VF9            = 0x0000016a,
21998  IH_PERF_SEL_RB0_LOAD_RPTR_VF10           = 0x0000016b,
21999  IH_PERF_SEL_RB0_LOAD_RPTR_VF11           = 0x0000016c,
22000  IH_PERF_SEL_RB0_LOAD_RPTR_VF12           = 0x0000016d,
22001  IH_PERF_SEL_RB0_LOAD_RPTR_VF13           = 0x0000016e,
22002  IH_PERF_SEL_RB0_LOAD_RPTR_VF14           = 0x0000016f,
22003  IH_PERF_SEL_RB0_LOAD_RPTR_VF15           = 0x00000170,
22004  IH_PERF_SEL_RB1_LOAD_RPTR                = 0x00000171,
22005  IH_PERF_SEL_RB1_LOAD_RPTR_VF0            = 0x00000172,
22006  IH_PERF_SEL_RB1_LOAD_RPTR_VF1            = 0x00000173,
22007  IH_PERF_SEL_RB1_LOAD_RPTR_VF2            = 0x00000174,
22008  IH_PERF_SEL_RB1_LOAD_RPTR_VF3            = 0x00000175,
22009  IH_PERF_SEL_RB1_LOAD_RPTR_VF4            = 0x00000176,
22010  IH_PERF_SEL_RB1_LOAD_RPTR_VF5            = 0x00000177,
22011  IH_PERF_SEL_RB1_LOAD_RPTR_VF6            = 0x00000178,
22012  IH_PERF_SEL_RB1_LOAD_RPTR_VF7            = 0x00000179,
22013  IH_PERF_SEL_RB1_LOAD_RPTR_VF8            = 0x0000017a,
22014  IH_PERF_SEL_RB1_LOAD_RPTR_VF9            = 0x0000017b,
22015  IH_PERF_SEL_RB1_LOAD_RPTR_VF10           = 0x0000017c,
22016  IH_PERF_SEL_RB1_LOAD_RPTR_VF11           = 0x0000017d,
22017  IH_PERF_SEL_RB1_LOAD_RPTR_VF12           = 0x0000017e,
22018  IH_PERF_SEL_RB1_LOAD_RPTR_VF13           = 0x0000017f,
22019  IH_PERF_SEL_RB1_LOAD_RPTR_VF14           = 0x00000180,
22020  IH_PERF_SEL_RB1_LOAD_RPTR_VF15           = 0x00000181,
22021  IH_PERF_SEL_RB2_LOAD_RPTR                = 0x00000182,
22022  IH_PERF_SEL_RB2_LOAD_RPTR_VF0            = 0x00000183,
22023  IH_PERF_SEL_RB2_LOAD_RPTR_VF1            = 0x00000184,
22024  IH_PERF_SEL_RB2_LOAD_RPTR_VF2            = 0x00000185,
22025  IH_PERF_SEL_RB2_LOAD_RPTR_VF3            = 0x00000186,
22026  IH_PERF_SEL_RB2_LOAD_RPTR_VF4            = 0x00000187,
22027  IH_PERF_SEL_RB2_LOAD_RPTR_VF5            = 0x00000188,
22028  IH_PERF_SEL_RB2_LOAD_RPTR_VF6            = 0x00000189,
22029  IH_PERF_SEL_RB2_LOAD_RPTR_VF7            = 0x0000018a,
22030  IH_PERF_SEL_RB2_LOAD_RPTR_VF8            = 0x0000018b,
22031  IH_PERF_SEL_RB2_LOAD_RPTR_VF9            = 0x0000018c,
22032  IH_PERF_SEL_RB2_LOAD_RPTR_VF10           = 0x0000018d,
22033  IH_PERF_SEL_RB2_LOAD_RPTR_VF11           = 0x0000018e,
22034  IH_PERF_SEL_RB2_LOAD_RPTR_VF12           = 0x0000018f,
22035  IH_PERF_SEL_RB2_LOAD_RPTR_VF13           = 0x00000190,
22036  IH_PERF_SEL_RB2_LOAD_RPTR_VF14           = 0x00000191,
22037  IH_PERF_SEL_RB2_LOAD_RPTR_VF15           = 0x00000192,
22038  } IH_PERF_SEL;
22039  
22040  /*
22041   * IH_RING_ID enum
22042   */
22043  
22044  typedef enum IH_RING_ID {
22045  IH_RING_ID_INTERRUPT                     = 0x00000000,
22046  IH_RING_ID_REQUEST                       = 0x00000001,
22047  IH_RING_ID_TRANSLATION                   = 0x00000002,
22048  IH_RING_ID_RESERVED                      = 0x00000003,
22049  } IH_RING_ID;
22050  
22051  /*
22052   * IH_VF_RB_SELECT enum
22053   */
22054  
22055  typedef enum IH_VF_RB_SELECT {
22056  IH_VF_RB_SELECT_CLIENT_FCN_ID            = 0x00000000,
22057  IH_VF_RB_SELECT_IH_FCN_ID                = 0x00000001,
22058  IH_VF_RB_SELECT_PF                       = 0x00000002,
22059  IH_VF_RB_SELECT_RESERVED                 = 0x00000003,
22060  } IH_VF_RB_SELECT;
22061  
22062  /*******************************************************
22063   * SEM Enums
22064   *******************************************************/
22065  
22066  /*
22067   * SEM_PERF_SEL enum
22068   */
22069  
22070  typedef enum SEM_PERF_SEL {
22071  SEM_PERF_SEL_CYCLE                       = 0x00000000,
22072  SEM_PERF_SEL_IDLE                        = 0x00000001,
22073  SEM_PERF_SEL_SDMA0_REQ_SIGNAL            = 0x00000002,
22074  SEM_PERF_SEL_SDMA1_REQ_SIGNAL            = 0x00000003,
22075  SEM_PERF_SEL_SDMA2_REQ_SIGNAL            = 0x00000004,
22076  SEM_PERF_SEL_SDMA3_REQ_SIGNAL            = 0x00000005,
22077  SEM_PERF_SEL_UVD_REQ_SIGNAL              = 0x00000006,
22078  SEM_PERF_SEL_UVD1_REQ_SIGNAL             = 0x00000007,
22079  SEM_PERF_SEL_VCE0_REQ_SIGNAL             = 0x00000008,
22080  SEM_PERF_SEL_ACP_REQ_SIGNAL              = 0x00000009,
22081  SEM_PERF_SEL_ISP_REQ_SIGNAL              = 0x0000000a,
22082  SEM_PERF_SEL_VCE1_REQ_SIGNAL             = 0x0000000b,
22083  SEM_PERF_SEL_VP8_REQ_SIGNAL              = 0x0000000c,
22084  SEM_PERF_SEL_CPG_E0_REQ_SIGNAL           = 0x0000000d,
22085  SEM_PERF_SEL_CPG_E1_REQ_SIGNAL           = 0x0000000e,
22086  SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL     = 0x0000000f,
22087  SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL     = 0x00000010,
22088  SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL     = 0x00000011,
22089  SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL     = 0x00000012,
22090  SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL     = 0x00000013,
22091  SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL     = 0x00000014,
22092  SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL     = 0x00000015,
22093  SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL     = 0x00000016,
22094  SEM_PERF_SEL_SDMA0_REQ_WAIT              = 0x00000017,
22095  SEM_PERF_SEL_SDMA1_REQ_WAIT              = 0x00000018,
22096  SEM_PERF_SEL_SDMA2_REQ_WAIT              = 0x00000019,
22097  SEM_PERF_SEL_SDMA3_REQ_WAIT              = 0x0000001a,
22098  SEM_PERF_SEL_UVD_REQ_WAIT                = 0x0000001b,
22099  SEM_PERF_SEL_UVD1_REQ_WAIT               = 0x0000001c,
22100  SEM_PERF_SEL_VCE0_REQ_WAIT               = 0x0000001d,
22101  SEM_PERF_SEL_ACP_REQ_WAIT                = 0x0000001e,
22102  SEM_PERF_SEL_ISP_REQ_WAIT                = 0x0000001f,
22103  SEM_PERF_SEL_VCE1_REQ_WAIT               = 0x00000020,
22104  SEM_PERF_SEL_VP8_REQ_WAIT                = 0x00000021,
22105  SEM_PERF_SEL_CPG_E0_REQ_WAIT             = 0x00000022,
22106  SEM_PERF_SEL_CPG_E1_REQ_WAIT             = 0x00000023,
22107  SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT       = 0x00000024,
22108  SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT       = 0x00000025,
22109  SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT       = 0x00000026,
22110  SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT       = 0x00000027,
22111  SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT       = 0x00000028,
22112  SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT       = 0x00000029,
22113  SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT       = 0x0000002a,
22114  SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT       = 0x0000002b,
22115  SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT       = 0x0000002c,
22116  SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT       = 0x0000002d,
22117  SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT       = 0x0000002e,
22118  SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT       = 0x0000002f,
22119  SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT       = 0x00000030,
22120  SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT       = 0x00000031,
22121  SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT       = 0x00000032,
22122  SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT       = 0x00000033,
22123  SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT       = 0x00000034,
22124  SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT       = 0x00000035,
22125  SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT      = 0x00000036,
22126  SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT      = 0x00000037,
22127  SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT      = 0x00000038,
22128  SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT      = 0x00000039,
22129  SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT      = 0x0000003a,
22130  SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT      = 0x0000003b,
22131  SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT      = 0x0000003c,
22132  SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT      = 0x0000003d,
22133  SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT      = 0x0000003e,
22134  SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT      = 0x0000003f,
22135  SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT      = 0x00000040,
22136  SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT      = 0x00000041,
22137  SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT      = 0x00000042,
22138  SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT      = 0x00000043,
22139  SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT      = 0x00000044,
22140  SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT      = 0x00000045,
22141  SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT      = 0x00000046,
22142  SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT      = 0x00000047,
22143  SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT      = 0x00000048,
22144  SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT      = 0x00000049,
22145  SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT      = 0x0000004a,
22146  SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT      = 0x0000004b,
22147  SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT       = 0x0000004c,
22148  SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT       = 0x0000004d,
22149  SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT       = 0x0000004e,
22150  SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT       = 0x0000004f,
22151  SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT       = 0x00000050,
22152  SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT       = 0x00000051,
22153  SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT       = 0x00000052,
22154  SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT       = 0x00000053,
22155  SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT       = 0x00000054,
22156  SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT       = 0x00000055,
22157  SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT      = 0x00000056,
22158  SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT      = 0x00000057,
22159  SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT      = 0x00000058,
22160  SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT      = 0x00000059,
22161  SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT      = 0x0000005a,
22162  SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT      = 0x0000005b,
22163  SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT      = 0x0000005c,
22164  SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT      = 0x0000005d,
22165  SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT      = 0x0000005e,
22166  SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT      = 0x0000005f,
22167  SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT      = 0x00000060,
22168  SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT      = 0x00000061,
22169  SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT      = 0x00000062,
22170  SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT      = 0x00000063,
22171  SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT      = 0x00000064,
22172  SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT      = 0x00000065,
22173  SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT      = 0x00000066,
22174  SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT      = 0x00000067,
22175  SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT      = 0x00000068,
22176  SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT      = 0x00000069,
22177  SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT      = 0x0000006a,
22178  SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT      = 0x0000006b,
22179  SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT      = 0x0000006c,
22180  SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT      = 0x0000006d,
22181  SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT      = 0x0000006e,
22182  SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT      = 0x0000006f,
22183  SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT      = 0x00000070,
22184  SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT      = 0x00000071,
22185  SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT      = 0x00000072,
22186  SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT      = 0x00000073,
22187  SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT      = 0x00000074,
22188  SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT      = 0x00000075,
22189  SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT     = 0x00000076,
22190  SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT     = 0x00000077,
22191  SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT     = 0x00000078,
22192  SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT     = 0x00000079,
22193  SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT     = 0x0000007a,
22194  SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT     = 0x0000007b,
22195  SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT     = 0x0000007c,
22196  SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT     = 0x0000007d,
22197  SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT     = 0x0000007e,
22198  SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT     = 0x0000007f,
22199  SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT     = 0x00000080,
22200  SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT     = 0x00000081,
22201  SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT     = 0x00000082,
22202  SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT     = 0x00000083,
22203  SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT     = 0x00000084,
22204  SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT     = 0x00000085,
22205  SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT     = 0x00000086,
22206  SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT     = 0x00000087,
22207  SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT     = 0x00000088,
22208  SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT     = 0x00000089,
22209  SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT     = 0x0000008a,
22210  SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT     = 0x0000008b,
22211  SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT      = 0x0000008c,
22212  SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT      = 0x0000008d,
22213  SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT      = 0x0000008e,
22214  SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT      = 0x0000008f,
22215  SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT      = 0x00000090,
22216  SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT      = 0x00000091,
22217  SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT      = 0x00000092,
22218  SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT      = 0x00000093,
22219  SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT      = 0x00000094,
22220  SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT      = 0x00000095,
22221  SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT     = 0x00000096,
22222  SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT     = 0x00000097,
22223  SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT     = 0x00000098,
22224  SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT     = 0x00000099,
22225  SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT     = 0x0000009a,
22226  SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT     = 0x0000009b,
22227  SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT     = 0x0000009c,
22228  SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT     = 0x0000009d,
22229  SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT     = 0x0000009e,
22230  SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT     = 0x0000009f,
22231  SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT     = 0x000000a0,
22232  SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT     = 0x000000a1,
22233  SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT     = 0x000000a2,
22234  SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT     = 0x000000a3,
22235  SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT     = 0x000000a4,
22236  SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT     = 0x000000a5,
22237  SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT     = 0x000000a6,
22238  SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT     = 0x000000a7,
22239  SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT     = 0x000000a8,
22240  SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT     = 0x000000a9,
22241  SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT     = 0x000000aa,
22242  SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT     = 0x000000ab,
22243  SEM_PERF_SEL_MC_RD_REQ                   = 0x000000ac,
22244  SEM_PERF_SEL_MC_RD_RET                   = 0x000000ad,
22245  SEM_PERF_SEL_MC_WR_REQ                   = 0x000000ae,
22246  SEM_PERF_SEL_MC_WR_RET                   = 0x000000af,
22247  SEM_PERF_SEL_ATC_REQ                     = 0x000000b0,
22248  SEM_PERF_SEL_ATC_RET                     = 0x000000b1,
22249  SEM_PERF_SEL_ATC_XNACK                   = 0x000000b2,
22250  SEM_PERF_SEL_ATC_INVALIDATION            = 0x000000b3,
22251  SEM_PERF_SEL_ATC_VM_INVALIDATION         = 0x000000b4,
22252  } SEM_PERF_SEL;
22253  
22254  /*******************************************************
22255   * LSDMA Enums
22256   *******************************************************/
22257  
22258  /*
22259   * LSDMA_PERF_SEL enum
22260   */
22261  
22262  typedef enum LSDMA_PERF_SEL {
22263  LSDMA_PERF_SEL_CYCLE                     = 0x00000000,
22264  LSDMA_PERF_SEL_IDLE                      = 0x00000001,
22265  LSDMA_PERF_SEL_REG_IDLE                  = 0x00000002,
22266  LSDMA_PERF_SEL_RB_EMPTY                  = 0x00000003,
22267  LSDMA_PERF_SEL_RB_FULL                   = 0x00000004,
22268  LSDMA_PERF_SEL_RB_WPTR_WRAP              = 0x00000005,
22269  LSDMA_PERF_SEL_RB_RPTR_WRAP              = 0x00000006,
22270  LSDMA_PERF_SEL_RB_WPTR_POLL_READ         = 0x00000007,
22271  LSDMA_PERF_SEL_RB_RPTR_WB                = 0x00000008,
22272  LSDMA_PERF_SEL_RB_CMD_IDLE               = 0x00000009,
22273  LSDMA_PERF_SEL_RB_CMD_FULL               = 0x0000000a,
22274  LSDMA_PERF_SEL_IB_CMD_IDLE               = 0x0000000b,
22275  LSDMA_PERF_SEL_IB_CMD_FULL               = 0x0000000c,
22276  LSDMA_PERF_SEL_EX_IDLE                   = 0x0000000d,
22277  LSDMA_PERF_SEL_SRBM_REG_SEND             = 0x0000000e,
22278  LSDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0x0000000f,
22279  LSDMA_PERF_SEL_MC_WR_IDLE                = 0x00000010,
22280  LSDMA_PERF_SEL_MC_WR_COUNT               = 0x00000011,
22281  LSDMA_PERF_SEL_MC_RD_IDLE                = 0x00000012,
22282  LSDMA_PERF_SEL_MC_RD_COUNT               = 0x00000013,
22283  LSDMA_PERF_SEL_MC_RD_RET_STALL           = 0x00000014,
22284  LSDMA_PERF_SEL_MC_RD_NO_POLL_IDLE        = 0x00000015,
22285  LSDMA_PERF_SEL_SEM_IDLE                  = 0x00000018,
22286  LSDMA_PERF_SEL_SEM_REQ_STALL             = 0x00000019,
22287  LSDMA_PERF_SEL_SEM_REQ_COUNT             = 0x0000001a,
22288  LSDMA_PERF_SEL_SEM_RESP_INCOMPLETE       = 0x0000001b,
22289  LSDMA_PERF_SEL_SEM_RESP_FAIL             = 0x0000001c,
22290  LSDMA_PERF_SEL_SEM_RESP_PASS             = 0x0000001d,
22291  LSDMA_PERF_SEL_INT_IDLE                  = 0x0000001e,
22292  LSDMA_PERF_SEL_INT_REQ_STALL             = 0x0000001f,
22293  LSDMA_PERF_SEL_INT_REQ_COUNT             = 0x00000020,
22294  LSDMA_PERF_SEL_INT_RESP_ACCEPTED         = 0x00000021,
22295  LSDMA_PERF_SEL_INT_RESP_RETRY            = 0x00000022,
22296  LSDMA_PERF_SEL_NUM_PACKET                = 0x00000023,
22297  LSDMA_PERF_SEL_CE_WREQ_IDLE              = 0x00000025,
22298  LSDMA_PERF_SEL_CE_WR_IDLE                = 0x00000026,
22299  LSDMA_PERF_SEL_CE_SPLIT_IDLE             = 0x00000027,
22300  LSDMA_PERF_SEL_CE_RREQ_IDLE              = 0x00000028,
22301  LSDMA_PERF_SEL_CE_OUT_IDLE               = 0x00000029,
22302  LSDMA_PERF_SEL_CE_IN_IDLE                = 0x0000002a,
22303  LSDMA_PERF_SEL_CE_DST_IDLE               = 0x0000002b,
22304  LSDMA_PERF_SEL_CE_AFIFO_FULL             = 0x0000002e,
22305  LSDMA_PERF_SEL_CE_INFO_FULL              = 0x00000031,
22306  LSDMA_PERF_SEL_CE_INFO1_FULL             = 0x00000032,
22307  LSDMA_PERF_SEL_CE_RD_STALL               = 0x00000033,
22308  LSDMA_PERF_SEL_CE_WR_STALL               = 0x00000034,
22309  LSDMA_PERF_SEL_GFX_SELECT                = 0x00000035,
22310  LSDMA_PERF_SEL_RLC0_SELECT               = 0x00000036,
22311  LSDMA_PERF_SEL_RLC1_SELECT               = 0x00000037,
22312  LSDMA_PERF_SEL_PAGE_SELECT               = 0x00000038,
22313  LSDMA_PERF_SEL_CTX_CHANGE                = 0x00000039,
22314  LSDMA_PERF_SEL_CTX_CHANGE_EXPIRED        = 0x0000003a,
22315  LSDMA_PERF_SEL_CTX_CHANGE_EXCEPTION      = 0x0000003b,
22316  LSDMA_PERF_SEL_DOORBELL                  = 0x0000003c,
22317  LSDMA_PERF_SEL_RD_BA_RTR                 = 0x0000003d,
22318  LSDMA_PERF_SEL_WR_BA_RTR                 = 0x0000003e,
22319  LSDMA_PERF_SEL_F32_L1_WR_VLD             = 0x0000003f,
22320  LSDMA_PERF_SEL_CE_L1_WR_VLD              = 0x00000040,
22321  LSDMA_PERF_SEL_CE_L1_STALL               = 0x00000041,
22322  LSDMA_PERF_SEL_SDMA_INVACK_NFLUSH        = 0x00000042,
22323  LSDMA_PERF_SEL_SDMA_INVACK_FLUSH         = 0x00000043,
22324  LSDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH       = 0x00000044,
22325  LSDMA_PERF_SEL_ATCL2_INVREQ_FLUSH        = 0x00000045,
22326  LSDMA_PERF_SEL_ATCL2_RET_XNACK           = 0x00000046,
22327  LSDMA_PERF_SEL_ATCL2_RET_ACK             = 0x00000047,
22328  LSDMA_PERF_SEL_ATCL2_FREE                = 0x00000048,
22329  LSDMA_PERF_SEL_SDMA_ATCL2_SEND           = 0x00000049,
22330  LSDMA_PERF_SEL_DMA_L1_WR_SEND            = 0x0000004a,
22331  LSDMA_PERF_SEL_DMA_L1_RD_SEND            = 0x0000004b,
22332  LSDMA_PERF_SEL_DMA_MC_WR_SEND            = 0x0000004c,
22333  LSDMA_PERF_SEL_DMA_MC_RD_SEND            = 0x0000004d,
22334  LSDMA_PERF_SEL_L1_WR_FIFO_IDLE           = 0x0000004e,
22335  LSDMA_PERF_SEL_L1_RD_FIFO_IDLE           = 0x0000004f,
22336  LSDMA_PERF_SEL_L1_WRL2_IDLE              = 0x00000050,
22337  LSDMA_PERF_SEL_L1_RDL2_IDLE              = 0x00000051,
22338  LSDMA_PERF_SEL_L1_WRMC_IDLE              = 0x00000052,
22339  LSDMA_PERF_SEL_L1_RDMC_IDLE              = 0x00000053,
22340  LSDMA_PERF_SEL_L1_WR_INV_IDLE            = 0x00000054,
22341  LSDMA_PERF_SEL_L1_RD_INV_IDLE            = 0x00000055,
22342  LSDMA_PERF_SEL_L1_WR_INV_EN              = 0x00000056,
22343  LSDMA_PERF_SEL_L1_RD_INV_EN              = 0x00000057,
22344  LSDMA_PERF_SEL_L1_WR_WAIT_INVADR         = 0x00000058,
22345  LSDMA_PERF_SEL_L1_RD_WAIT_INVADR         = 0x00000059,
22346  LSDMA_PERF_SEL_IS_INVREQ_ADDR_WR         = 0x0000005a,
22347  LSDMA_PERF_SEL_IS_INVREQ_ADDR_RD         = 0x0000005b,
22348  LSDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT       = 0x0000005c,
22349  LSDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT       = 0x0000005d,
22350  LSDMA_PERF_SEL_L1_INV_MIDDLE             = 0x0000005e,
22351  LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_REQ    = 0x0000005f,
22352  LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_RET    = 0x00000060,
22353  LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_REQ       = 0x00000061,
22354  LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_RET       = 0x00000062,
22355  LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_REQ    = 0x00000063,
22356  LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_RET    = 0x00000064,
22357  LSDMA_PERF_SEL_RB_MMHUB_RD_REQ           = 0x00000065,
22358  LSDMA_PERF_SEL_RB_MMHUB_RD_RET           = 0x00000066,
22359  LSDMA_PERF_SEL_IB_MMHUB_RD_REQ           = 0x00000067,
22360  LSDMA_PERF_SEL_IB_MMHUB_RD_RET           = 0x00000068,
22361  LSDMA_PERF_SEL_WPTR_MMHUB_RD_REQ         = 0x00000069,
22362  LSDMA_PERF_SEL_WPTR_MMHUB_RD_RET         = 0x0000006a,
22363  LSDMA_PERF_SEL_UTCL1_UTCL2_REQ           = 0x0000006b,
22364  LSDMA_PERF_SEL_UTCL1_UTCL2_RET           = 0x0000006c,
22365  LSDMA_PERF_SEL_CMD_OP_MATCH              = 0x0000006d,
22366  LSDMA_PERF_SEL_CMD_OP_START              = 0x0000006e,
22367  LSDMA_PERF_SEL_CMD_OP_END                = 0x0000006f,
22368  LSDMA_PERF_SEL_CE_BUSY                   = 0x00000070,
22369  LSDMA_PERF_SEL_CE_BUSY_START             = 0x00000071,
22370  LSDMA_PERF_SEL_CE_BUSY_END               = 0x00000072,
22371  LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER       = 0x00000073,
22372  LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START = 0x00000074,
22373  LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END   = 0x00000075,
22374  LSDMA_PERF_SEL_CE_MMHUB_WRREQ_SEND       = 0x00000076,
22375  LSDMA_PERF_SEL_MMHUB_CE_WRRET_VALID      = 0x00000077,
22376  LSDMA_PERF_SEL_CE_MMHUB_RDREQ_SEND       = 0x00000078,
22377  LSDMA_PERF_SEL_MMHUB_CE_RDRET_VALID      = 0x00000079,
22378  LSDMA_PERF_SEL_DRAM_ECC                  = 0x0000007a,
22379  LSDMA_PERF_SEL_NACK_GEN_ERR              = 0x0000007b,
22380  } LSDMA_PERF_SEL;
22381  
22382  /*******************************************************
22383   * SMUIO_ROM Enums
22384   *******************************************************/
22385  
22386  /*
22387   * ROM_SIGNATURE value
22388   */
22389  
22390  #define ROM_SIGNATURE                  0x0000aa55
22391  
22392  /*******************************************************
22393   * UVD_EFC Enums
22394   *******************************************************/
22395  
22396  /*
22397   * EFC_SURFACE_PIXEL_FORMAT enum
22398   */
22399  
22400  typedef enum EFC_SURFACE_PIXEL_FORMAT {
22401  EFC_ARGB1555                             = 0x00000001,
22402  EFC_RGBA5551                             = 0x00000002,
22403  EFC_RGB565                               = 0x00000003,
22404  EFC_BGR565                               = 0x00000004,
22405  EFC_ARGB4444                             = 0x00000005,
22406  EFC_RGBA4444                             = 0x00000006,
22407  EFC_ARGB8888                             = 0x00000008,
22408  EFC_RGBA8888                             = 0x00000009,
22409  EFC_ARGB2101010                          = 0x0000000a,
22410  EFC_RGBA1010102                          = 0x0000000b,
22411  EFC_AYCrCb8888                           = 0x0000000c,
22412  EFC_YCrCbA8888                           = 0x0000000d,
22413  EFC_ACrYCb8888                           = 0x0000000e,
22414  EFC_CrYCbA8888                           = 0x0000000f,
22415  EFC_ARGB16161616_10MSB                   = 0x00000010,
22416  EFC_RGBA16161616_10MSB                   = 0x00000011,
22417  EFC_ARGB16161616_10LSB                   = 0x00000012,
22418  EFC_RGBA16161616_10LSB                   = 0x00000013,
22419  EFC_ARGB16161616_12MSB                   = 0x00000014,
22420  EFC_RGBA16161616_12MSB                   = 0x00000015,
22421  EFC_ARGB16161616_12LSB                   = 0x00000016,
22422  EFC_RGBA16161616_12LSB                   = 0x00000017,
22423  EFC_ARGB16161616_FLOAT                   = 0x00000018,
22424  EFC_RGBA16161616_FLOAT                   = 0x00000019,
22425  EFC_ARGB16161616_UNORM                   = 0x0000001a,
22426  EFC_RGBA16161616_UNORM                   = 0x0000001b,
22427  EFC_ARGB16161616_SNORM                   = 0x0000001c,
22428  EFC_RGBA16161616_SNORM                   = 0x0000001d,
22429  EFC_AYCrCb16161616_10MSB                 = 0x00000020,
22430  EFC_AYCrCb16161616_10LSB                 = 0x00000021,
22431  EFC_YCrCbA16161616_10MSB                 = 0x00000022,
22432  EFC_YCrCbA16161616_10LSB                 = 0x00000023,
22433  EFC_ACrYCb16161616_10MSB                 = 0x00000024,
22434  EFC_ACrYCb16161616_10LSB                 = 0x00000025,
22435  EFC_CrYCbA16161616_10MSB                 = 0x00000026,
22436  EFC_CrYCbA16161616_10LSB                 = 0x00000027,
22437  EFC_AYCrCb16161616_12MSB                 = 0x00000028,
22438  EFC_AYCrCb16161616_12LSB                 = 0x00000029,
22439  EFC_YCrCbA16161616_12MSB                 = 0x0000002a,
22440  EFC_YCrCbA16161616_12LSB                 = 0x0000002b,
22441  EFC_ACrYCb16161616_12MSB                 = 0x0000002c,
22442  EFC_ACrYCb16161616_12LSB                 = 0x0000002d,
22443  EFC_CrYCbA16161616_12MSB                 = 0x0000002e,
22444  EFC_CrYCbA16161616_12LSB                 = 0x0000002f,
22445  EFC_Y8_CrCb88_420_PLANAR                 = 0x00000040,
22446  EFC_Y8_CbCr88_420_PLANAR                 = 0x00000041,
22447  EFC_Y10_CrCb1010_420_PLANAR              = 0x00000042,
22448  EFC_Y10_CbCr1010_420_PLANAR              = 0x00000043,
22449  EFC_Y12_CrCb1212_420_PLANAR              = 0x00000044,
22450  EFC_Y12_CbCr1212_420_PLANAR              = 0x00000045,
22451  EFC_YCrYCb8888_422_PACKED                = 0x00000048,
22452  EFC_YCbYCr8888_422_PACKED                = 0x00000049,
22453  EFC_CrYCbY8888_422_PACKED                = 0x0000004a,
22454  EFC_CbYCrY8888_422_PACKED                = 0x0000004b,
22455  EFC_YCrYCb10101010_422_PACKED            = 0x0000004c,
22456  EFC_YCbYCr10101010_422_PACKED            = 0x0000004d,
22457  EFC_CrYCbY10101010_422_PACKED            = 0x0000004e,
22458  EFC_CbYCrY10101010_422_PACKED            = 0x0000004f,
22459  EFC_YCrYCb12121212_422_PACKED            = 0x00000050,
22460  EFC_YCbYCr12121212_422_PACKED            = 0x00000051,
22461  EFC_CrYCbY12121212_422_PACKED            = 0x00000052,
22462  EFC_CbYCrY12121212_422_PACKED            = 0x00000053,
22463  EFC_RGB111110_FIX                        = 0x00000070,
22464  EFC_BGR101111_FIX                        = 0x00000071,
22465  EFC_ACrYCb2101010                        = 0x00000072,
22466  EFC_CrYCbA1010102                        = 0x00000073,
22467  EFC_RGB111110_FLOAT                      = 0x00000076,
22468  EFC_BGR101111_FLOAT                      = 0x00000077,
22469  EFC_MONO_8                               = 0x00000078,
22470  EFC_MONO_10MSB                           = 0x00000079,
22471  EFC_MONO_10LSB                           = 0x0000007a,
22472  EFC_MONO_12MSB                           = 0x0000007b,
22473  EFC_MONO_12LSB                           = 0x0000007c,
22474  EFC_MONO_16                              = 0x0000007d,
22475  } EFC_SURFACE_PIXEL_FORMAT;
22476  
22477  #endif /*_soc21_ENUM_HEADER*/
22478