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Searched refs:TCSR (Results 1 – 7 of 7) sorted by relevance

/openbmc/qemu/hw/timer/
H A Drenesas_tmr.c37 REG8(TCSR, 2)
38 FIELD(TCSR, OSA, 0, 2)
39 FIELD(TCSR, OSB, 2, 2)
40 FIELD(TCSR, ADTE, 4, 2)
219 ret = FIELD_DP8(ret, TCSR, OSA, in tmr_read()
220 FIELD_EX8(tmr->tcsr[ch], TCSR, OSA)); in tmr_read()
221 ret = FIELD_DP8(ret, TCSR, OSB, in tmr_read()
222 FIELD_EX8(tmr->tcsr[ch], TCSR, OSB)); in tmr_read()
225 ret = FIELD_DP8(ret, TCSR, ADTE, in tmr_read()
226 FIELD_EX8(tmr->tcsr[ch], TCSR, ADTE)); in tmr_read()
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/openbmc/linux/Documentation/translations/zh_CN/arch/mips/
H A Dingenic-tcu.rst25 - 每个TCU通道都有自己的时钟源，可以通过 TCSR 寄存器设置通道的父级时钟
28 - 看门狗和OST硬件模块在它们的寄存器空间中也有相同形式的TCSR寄存器。
/openbmc/linux/Documentation/arch/mips/
H A Dingenic-tcu.rst19 different clocks (pclk, ext, rtc), gated, and reclocked, through their TCSR register.
21 - The watchdog and OST hardware blocks also feature a TCSR register with the same
/openbmc/linux/drivers/net/wan/
H A Dhd64570.h92 #define TCSR 0x04 /* Control/Status */ macro
H A Dhd64572.h117 #define TCSR 0x206 /* Timer Control/Status Register */ macro
/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dqcom,q6v5.txt90 Definition: a phandle reference to a syscon representing TCSR followed
/openbmc/linux/drivers/clk/qcom/
H A DKconfig1008 tristate "SM8550 TCSR Clock Controller"
1012 Support for the TCSR clock controller on SM8550 devices.