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Searched refs:TCR_EL1 (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/arch/arm64/kvm/hyp/include/hyp/
H A Dsysreg-sr.h46 ctxt_sys_reg(ctxt, TCR_EL1) = read_sysreg_el1(SYS_TCR); in __sysreg_save_el1_state()
107 write_sysreg_el1(ctxt_sys_reg(ctxt, TCR_EL1), SYS_TCR); in __sysreg_restore_el1_state()
114 write_sysreg_el1((ctxt_sys_reg(ctxt, TCR_EL1) | in __sysreg_restore_el1_state()
161 write_sysreg_el1(ctxt_sys_reg(ctxt, TCR_EL1), SYS_TCR); in __sysreg_restore_el1_state()
/openbmc/linux/arch/arm64/kvm/
H A Dinject_fault.c134 if (vcpu_read_sys_reg(vcpu, TCR_EL1) & TTBCR_EAE) { in inject_abt32()
210 !(vcpu_read_sys_reg(vcpu, TCR_EL1) & TTBCR_EAE)) in kvm_inject_size_fault()
H A Dsys_regs.c2128 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },
2658 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 },
2660 { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 },
H A Demulate-nested.c1006 SR_FGT(SYS_TCR_EL1, HFGxTR, TCR_EL1, 1),
/openbmc/linux/arch/arm64/include/asm/
H A Dkvm_host.h300 TCR_EL1, /* Translation Control Register */ enumerator
825 case TCR_EL1: *val = read_sysreg_s(SYS_TCR_EL12); break; in __vcpu_read_sys_reg_from_cpu()
869 case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break; in __vcpu_write_sys_reg_to_cpu()
/openbmc/qemu/target/arm/
H A Dcpregs.h380 FIELD(HFGRTR_EL2, TCR_EL1, 32, 1)
427 FIELD(HFGWTR_EL2, TCR_EL1, 32, 1)
720 DO_BIT(HFGRTR, TCR_EL1),
/openbmc/linux/arch/arm64/kvm/hyp/nvhe/
H A Dswitch.c80 write_sysreg_el1(ctxt_sys_reg(ctxt, TCR_EL1), SYS_TCR); in __activate_traps()
/openbmc/linux/Documentation/arch/arm64/
H A Dtagged-address-abi.rst16 On AArch64 the ``TCR_EL1.TBI0`` bit is set by default, allowing
/openbmc/linux/Documentation/admin-guide/kdump/
H A Dvmcoreinfo.rst480 TCR_EL1.T1SZ
/openbmc/linux/arch/arm64/
H A DKconfig1198 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
1200 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
1810 table entries. When enabled in TCR_EL1 (HA and HD bits) on
/openbmc/linux/arch/arm64/tools/
H A Dsysreg2055 Field 32 TCR_EL1