xref: /openbmc/u-boot/drivers/timer/ag101p_timer.c (revision 1d6edcbfed2af33c748f2beb399810a0441888da)
1  // SPDX-License-Identifier: GPL-2.0+
2  /*
3   * Andestech ATFTMR010 timer driver
4   *
5   * (C) Copyright 2016
6   * Rick Chen, NDS32 Software Engineering, rick@andestech.com
7   */
8  #include <common.h>
9  #include <dm.h>
10  #include <errno.h>
11  #include <timer.h>
12  #include <linux/io.h>
13  
14  /*
15   * Timer Control Register
16   */
17  #define T3_UPDOWN	(1 << 11)
18  #define T2_UPDOWN	(1 << 10)
19  #define T1_UPDOWN	(1 << 9)
20  #define T3_OFENABLE	(1 << 8)
21  #define T3_CLOCK	(1 << 7)
22  #define T3_ENABLE	(1 << 6)
23  #define T2_OFENABLE	(1 << 5)
24  #define T2_CLOCK	(1 << 4)
25  #define T2_ENABLE	(1 << 3)
26  #define T1_OFENABLE	(1 << 2)
27  #define T1_CLOCK	(1 << 1)
28  #define T1_ENABLE	(1 << 0)
29  
30  /*
31   * Timer Interrupt State & Mask Registers
32   */
33  #define T3_OVERFLOW	(1 << 8)
34  #define T3_MATCH2	(1 << 7)
35  #define T3_MATCH1	(1 << 6)
36  #define T2_OVERFLOW	(1 << 5)
37  #define T2_MATCH2	(1 << 4)
38  #define T2_MATCH1	(1 << 3)
39  #define T1_OVERFLOW	(1 << 2)
40  #define T1_MATCH2	(1 << 1)
41  #define T1_MATCH1	(1 << 0)
42  
43  struct atftmr_timer_regs {
44  	u32	t1_counter;		/* 0x00 */
45  	u32	t1_load;		/* 0x04 */
46  	u32	t1_match1;		/* 0x08 */
47  	u32	t1_match2;		/* 0x0c */
48  	u32	t2_counter;		/* 0x10 */
49  	u32	t2_load;		/* 0x14 */
50  	u32	t2_match1;		/* 0x18 */
51  	u32	t2_match2;		/* 0x1c */
52  	u32	t3_counter;		/* 0x20 */
53  	u32	t3_load;		/* 0x24 */
54  	u32	t3_match1;		/* 0x28 */
55  	u32	t3_match2;		/* 0x2c */
56  	u32	cr;			/* 0x30 */
57  	u32	int_state;		/* 0x34 */
58  	u32	int_mask;		/* 0x38 */
59  };
60  
61  struct atftmr_timer_platdata {
62  	struct atftmr_timer_regs *regs;
63  };
64  
atftmr_timer_get_count(struct udevice * dev,u64 * count)65  static int atftmr_timer_get_count(struct udevice *dev, u64 *count)
66  {
67  	struct atftmr_timer_platdata *plat = dev->platdata;
68  	struct atftmr_timer_regs *const regs = plat->regs;
69  	u32 val;
70  	val = readl(&regs->t3_counter);
71  	*count = timer_conv_64(val);
72  	return 0;
73  }
74  
atftmr_timer_probe(struct udevice * dev)75  static int atftmr_timer_probe(struct udevice *dev)
76  {
77  	struct atftmr_timer_platdata *plat = dev->platdata;
78  	struct atftmr_timer_regs *const regs = plat->regs;
79  	u32 cr;
80  	writel(0, &regs->t3_load);
81  	writel(0, &regs->t3_counter);
82  	writel(TIMER_LOAD_VAL, &regs->t3_match1);
83  	writel(TIMER_LOAD_VAL, &regs->t3_match2);
84  	/* disable interrupts */
85  	writel(T3_MATCH1|T3_MATCH2|T3_OVERFLOW , &regs->int_mask);
86  	cr = readl(&regs->cr);
87  	cr |= (T3_ENABLE|T3_UPDOWN);
88  	writel(cr, &regs->cr);
89  	return 0;
90  }
91  
atftme_timer_ofdata_to_platdata(struct udevice * dev)92  static int atftme_timer_ofdata_to_platdata(struct udevice *dev)
93  {
94  	struct atftmr_timer_platdata *plat = dev_get_platdata(dev);
95  	plat->regs = map_physmem(devfdt_get_addr(dev),
96  				 sizeof(struct atftmr_timer_regs),
97  				 MAP_NOCACHE);
98  	return 0;
99  }
100  
101  static const struct timer_ops ag101p_timer_ops = {
102  	.get_count = atftmr_timer_get_count,
103  };
104  
105  static const struct udevice_id ag101p_timer_ids[] = {
106  	{ .compatible = "andestech,attmr010" },
107  	{}
108  };
109  
110  U_BOOT_DRIVER(altera_timer) = {
111  	.name	= "ag101p_timer",
112  	.id	= UCLASS_TIMER,
113  	.of_match = ag101p_timer_ids,
114  	.ofdata_to_platdata = atftme_timer_ofdata_to_platdata,
115  	.platdata_auto_alloc_size = sizeof(struct atftmr_timer_platdata),
116  	.probe = atftmr_timer_probe,
117  	.ops	= &ag101p_timer_ops,
118  };
119