1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2019 MediaTek Inc. 4 * Author: jitao.shi <jitao.shi@mediatek.com> 5 */ 6 7 #include "phy-mtk-io.h" 8 #include "phy-mtk-mipi-dsi.h" 9 10 #define MIPITX_DSI_CON 0x00 11 #define RG_DSI_LDOCORE_EN BIT(0) 12 #define RG_DSI_CKG_LDOOUT_EN BIT(1) 13 #define RG_DSI_BCLK_SEL GENMASK(3, 2) 14 #define RG_DSI_LD_IDX_SEL GENMASK(6, 4) 15 #define RG_DSI_PHYCLK_SEL GENMASK(9, 8) 16 #define RG_DSI_DSICLK_FREQ_SEL BIT(10) 17 #define RG_DSI_LPTX_CLMP_EN BIT(11) 18 19 #define MIPITX_DSI_CLOCK_LANE 0x04 20 #define MIPITX_DSI_DATA_LANE0 0x08 21 #define MIPITX_DSI_DATA_LANE1 0x0c 22 #define MIPITX_DSI_DATA_LANE2 0x10 23 #define MIPITX_DSI_DATA_LANE3 0x14 24 #define RG_DSI_LNTx_LDOOUT_EN BIT(0) 25 #define RG_DSI_LNTx_CKLANE_EN BIT(1) 26 #define RG_DSI_LNTx_LPTX_IPLUS1 BIT(2) 27 #define RG_DSI_LNTx_LPTX_IPLUS2 BIT(3) 28 #define RG_DSI_LNTx_LPTX_IMINUS BIT(4) 29 #define RG_DSI_LNTx_LPCD_IPLUS BIT(5) 30 #define RG_DSI_LNTx_LPCD_IMINUS BIT(6) 31 #define RG_DSI_LNTx_RT_CODE GENMASK(11, 8) 32 33 #define MIPITX_DSI_TOP_CON 0x40 34 #define RG_DSI_LNT_INTR_EN BIT(0) 35 #define RG_DSI_LNT_HS_BIAS_EN BIT(1) 36 #define RG_DSI_LNT_IMP_CAL_EN BIT(2) 37 #define RG_DSI_LNT_TESTMODE_EN BIT(3) 38 #define RG_DSI_LNT_IMP_CAL_CODE GENMASK(7, 4) 39 #define RG_DSI_LNT_AIO_SEL GENMASK(10, 8) 40 #define RG_DSI_PAD_TIE_LOW_EN BIT(11) 41 #define RG_DSI_DEBUG_INPUT_EN BIT(12) 42 #define RG_DSI_PRESERVE GENMASK(15, 13) 43 44 #define MIPITX_DSI_BG_CON 0x44 45 #define RG_DSI_BG_CORE_EN BIT(0) 46 #define RG_DSI_BG_CKEN BIT(1) 47 #define RG_DSI_BG_DIV GENMASK(3, 2) 48 #define RG_DSI_BG_FAST_CHARGE BIT(4) 49 50 #define RG_DSI_V12_SEL GENMASK(7, 5) 51 #define RG_DSI_V10_SEL GENMASK(10, 8) 52 #define RG_DSI_V072_SEL GENMASK(13, 11) 53 #define RG_DSI_V04_SEL GENMASK(16, 14) 54 #define RG_DSI_V032_SEL GENMASK(19, 17) 55 #define RG_DSI_V02_SEL GENMASK(22, 20) 56 #define RG_DSI_VOUT_MSK \ 57 (RG_DSI_V12_SEL | RG_DSI_V10_SEL | RG_DSI_V072_SEL | \ 58 RG_DSI_V04_SEL | RG_DSI_V032_SEL | RG_DSI_V02_SEL) 59 #define RG_DSI_BG_R1_TRIM GENMASK(27, 24) 60 #define RG_DSI_BG_R2_TRIM GENMASK(31, 28) 61 62 #define MIPITX_DSI_PLL_CON0 0x50 63 #define RG_DSI_MPPLL_PLL_EN BIT(0) 64 #define RG_DSI_MPPLL_PREDIV GENMASK(2, 1) 65 #define RG_DSI_MPPLL_TXDIV0 GENMASK(4, 3) 66 #define RG_DSI_MPPLL_TXDIV1 GENMASK(6, 5) 67 #define RG_DSI_MPPLL_POSDIV GENMASK(9, 7) 68 #define RG_DSI_MPPLL_DIV_MSK \ 69 (RG_DSI_MPPLL_PREDIV | RG_DSI_MPPLL_TXDIV0 | \ 70 RG_DSI_MPPLL_TXDIV1 | RG_DSI_MPPLL_POSDIV) 71 #define RG_DSI_MPPLL_MONVC_EN BIT(10) 72 #define RG_DSI_MPPLL_MONREF_EN BIT(11) 73 #define RG_DSI_MPPLL_VOD_EN BIT(12) 74 75 #define MIPITX_DSI_PLL_CON1 0x54 76 #define RG_DSI_MPPLL_SDM_FRA_EN BIT(0) 77 #define RG_DSI_MPPLL_SDM_SSC_PH_INIT BIT(1) 78 #define RG_DSI_MPPLL_SDM_SSC_EN BIT(2) 79 #define RG_DSI_MPPLL_SDM_SSC_PRD GENMASK(31, 16) 80 81 #define MIPITX_DSI_PLL_CON2 0x58 82 83 #define MIPITX_DSI_PLL_TOP 0x64 84 #define RG_DSI_MPPLL_PRESERVE GENMASK(15, 8) 85 86 #define MIPITX_DSI_PLL_PWR 0x68 87 #define RG_DSI_MPPLL_SDM_PWR_ON BIT(0) 88 #define RG_DSI_MPPLL_SDM_ISO_EN BIT(1) 89 #define RG_DSI_MPPLL_SDM_PWR_ACK BIT(8) 90 91 #define MIPITX_DSI_SW_CTRL 0x80 92 #define SW_CTRL_EN BIT(0) 93 94 #define MIPITX_DSI_SW_CTRL_CON0 0x84 95 #define SW_LNTC_LPTX_PRE_OE BIT(0) 96 #define SW_LNTC_LPTX_OE BIT(1) 97 #define SW_LNTC_LPTX_P BIT(2) 98 #define SW_LNTC_LPTX_N BIT(3) 99 #define SW_LNTC_HSTX_PRE_OE BIT(4) 100 #define SW_LNTC_HSTX_OE BIT(5) 101 #define SW_LNTC_HSTX_ZEROCLK BIT(6) 102 #define SW_LNT0_LPTX_PRE_OE BIT(7) 103 #define SW_LNT0_LPTX_OE BIT(8) 104 #define SW_LNT0_LPTX_P BIT(9) 105 #define SW_LNT0_LPTX_N BIT(10) 106 #define SW_LNT0_HSTX_PRE_OE BIT(11) 107 #define SW_LNT0_HSTX_OE BIT(12) 108 #define SW_LNT0_LPRX_EN BIT(13) 109 #define SW_LNT1_LPTX_PRE_OE BIT(14) 110 #define SW_LNT1_LPTX_OE BIT(15) 111 #define SW_LNT1_LPTX_P BIT(16) 112 #define SW_LNT1_LPTX_N BIT(17) 113 #define SW_LNT1_HSTX_PRE_OE BIT(18) 114 #define SW_LNT1_HSTX_OE BIT(19) 115 #define SW_LNT2_LPTX_PRE_OE BIT(20) 116 #define SW_LNT2_LPTX_OE BIT(21) 117 #define SW_LNT2_LPTX_P BIT(22) 118 #define SW_LNT2_LPTX_N BIT(23) 119 #define SW_LNT2_HSTX_PRE_OE BIT(24) 120 #define SW_LNT2_HSTX_OE BIT(25) 121 mtk_mipi_tx_pll_prepare(struct clk_hw * hw)122 static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw) 123 { 124 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw); 125 void __iomem *base = mipi_tx->regs; 126 u8 txdiv, txdiv0, txdiv1; 127 u64 pcw; 128 129 dev_dbg(mipi_tx->dev, "prepare: %u Hz\n", mipi_tx->data_rate); 130 131 if (mipi_tx->data_rate >= 500000000) { 132 txdiv = 1; 133 txdiv0 = 0; 134 txdiv1 = 0; 135 } else if (mipi_tx->data_rate >= 250000000) { 136 txdiv = 2; 137 txdiv0 = 1; 138 txdiv1 = 0; 139 } else if (mipi_tx->data_rate >= 125000000) { 140 txdiv = 4; 141 txdiv0 = 2; 142 txdiv1 = 0; 143 } else if (mipi_tx->data_rate > 62000000) { 144 txdiv = 8; 145 txdiv0 = 2; 146 txdiv1 = 1; 147 } else if (mipi_tx->data_rate >= 50000000) { 148 txdiv = 16; 149 txdiv0 = 2; 150 txdiv1 = 2; 151 } else { 152 return -EINVAL; 153 } 154 155 mtk_phy_update_bits(base + MIPITX_DSI_BG_CON, 156 RG_DSI_VOUT_MSK | RG_DSI_BG_CKEN | 157 RG_DSI_BG_CORE_EN, 158 FIELD_PREP(RG_DSI_V02_SEL, 4) | 159 FIELD_PREP(RG_DSI_V032_SEL, 4) | 160 FIELD_PREP(RG_DSI_V04_SEL, 4) | 161 FIELD_PREP(RG_DSI_V072_SEL, 4) | 162 FIELD_PREP(RG_DSI_V10_SEL, 4) | 163 FIELD_PREP(RG_DSI_V12_SEL, 4) | 164 RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN); 165 166 usleep_range(30, 100); 167 168 mtk_phy_update_bits(base + MIPITX_DSI_TOP_CON, 169 RG_DSI_LNT_IMP_CAL_CODE | RG_DSI_LNT_HS_BIAS_EN, 170 FIELD_PREP(RG_DSI_LNT_IMP_CAL_CODE, 8) | 171 RG_DSI_LNT_HS_BIAS_EN); 172 173 mtk_phy_set_bits(base + MIPITX_DSI_CON, 174 RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN); 175 176 mtk_phy_update_bits(base + MIPITX_DSI_PLL_PWR, 177 RG_DSI_MPPLL_SDM_PWR_ON | RG_DSI_MPPLL_SDM_ISO_EN, 178 RG_DSI_MPPLL_SDM_PWR_ON); 179 180 mtk_phy_clear_bits(base + MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN); 181 182 mtk_phy_update_bits(base + MIPITX_DSI_PLL_CON0, 183 RG_DSI_MPPLL_TXDIV0 | RG_DSI_MPPLL_TXDIV1 | 184 RG_DSI_MPPLL_PREDIV, 185 FIELD_PREP(RG_DSI_MPPLL_TXDIV0, txdiv0) | 186 FIELD_PREP(RG_DSI_MPPLL_TXDIV1, txdiv1)); 187 188 /* 189 * PLL PCW config 190 * PCW bit 24~30 = integer part of pcw 191 * PCW bit 0~23 = fractional part of pcw 192 * pcw = data_Rate*4*txdiv/(Ref_clk*2); 193 * Post DIV =4, so need data_Rate*4 194 * Ref_clk is 26MHz 195 */ 196 pcw = div_u64(((u64)mipi_tx->data_rate * 2 * txdiv) << 24, 26000000); 197 writel(pcw, base + MIPITX_DSI_PLL_CON2); 198 199 mtk_phy_set_bits(base + MIPITX_DSI_PLL_CON1, RG_DSI_MPPLL_SDM_FRA_EN); 200 201 mtk_phy_set_bits(base + MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN); 202 203 usleep_range(20, 100); 204 205 mtk_phy_clear_bits(base + MIPITX_DSI_PLL_CON1, RG_DSI_MPPLL_SDM_SSC_EN); 206 207 mtk_phy_update_field(base + MIPITX_DSI_PLL_TOP, 208 RG_DSI_MPPLL_PRESERVE, 209 mipi_tx->driver_data->mppll_preserve); 210 211 return 0; 212 } 213 mtk_mipi_tx_pll_unprepare(struct clk_hw * hw)214 static void mtk_mipi_tx_pll_unprepare(struct clk_hw *hw) 215 { 216 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw); 217 void __iomem *base = mipi_tx->regs; 218 219 dev_dbg(mipi_tx->dev, "unprepare\n"); 220 221 mtk_phy_clear_bits(base + MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN); 222 223 mtk_phy_clear_bits(base + MIPITX_DSI_PLL_TOP, RG_DSI_MPPLL_PRESERVE); 224 225 mtk_phy_update_bits(base + MIPITX_DSI_PLL_PWR, 226 RG_DSI_MPPLL_SDM_ISO_EN | RG_DSI_MPPLL_SDM_PWR_ON, 227 RG_DSI_MPPLL_SDM_ISO_EN); 228 229 mtk_phy_clear_bits(base + MIPITX_DSI_TOP_CON, RG_DSI_LNT_HS_BIAS_EN); 230 231 mtk_phy_clear_bits(base + MIPITX_DSI_CON, 232 RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN); 233 234 mtk_phy_clear_bits(base + MIPITX_DSI_BG_CON, 235 RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN); 236 237 mtk_phy_clear_bits(base + MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_DIV_MSK); 238 } 239 mtk_mipi_tx_pll_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)240 static long mtk_mipi_tx_pll_round_rate(struct clk_hw *hw, unsigned long rate, 241 unsigned long *prate) 242 { 243 return clamp_val(rate, 50000000, 1250000000); 244 } 245 246 static const struct clk_ops mtk_mipi_tx_pll_ops = { 247 .prepare = mtk_mipi_tx_pll_prepare, 248 .unprepare = mtk_mipi_tx_pll_unprepare, 249 .round_rate = mtk_mipi_tx_pll_round_rate, 250 .set_rate = mtk_mipi_tx_pll_set_rate, 251 .recalc_rate = mtk_mipi_tx_pll_recalc_rate, 252 }; 253 mtk_mipi_tx_power_on_signal(struct phy * phy)254 static void mtk_mipi_tx_power_on_signal(struct phy *phy) 255 { 256 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy); 257 u32 reg; 258 259 for (reg = MIPITX_DSI_CLOCK_LANE; 260 reg <= MIPITX_DSI_DATA_LANE3; reg += 4) 261 mtk_phy_set_bits(mipi_tx->regs + reg, RG_DSI_LNTx_LDOOUT_EN); 262 263 mtk_phy_clear_bits(mipi_tx->regs + MIPITX_DSI_TOP_CON, 264 RG_DSI_PAD_TIE_LOW_EN); 265 } 266 mtk_mipi_tx_power_off_signal(struct phy * phy)267 static void mtk_mipi_tx_power_off_signal(struct phy *phy) 268 { 269 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy); 270 u32 reg; 271 272 mtk_phy_set_bits(mipi_tx->regs + MIPITX_DSI_TOP_CON, 273 RG_DSI_PAD_TIE_LOW_EN); 274 275 for (reg = MIPITX_DSI_CLOCK_LANE; 276 reg <= MIPITX_DSI_DATA_LANE3; reg += 4) 277 mtk_phy_clear_bits(mipi_tx->regs + reg, RG_DSI_LNTx_LDOOUT_EN); 278 } 279 280 const struct mtk_mipitx_data mt2701_mipitx_data = { 281 .mppll_preserve = 3, 282 .mipi_tx_clk_ops = &mtk_mipi_tx_pll_ops, 283 .mipi_tx_enable_signal = mtk_mipi_tx_power_on_signal, 284 .mipi_tx_disable_signal = mtk_mipi_tx_power_off_signal, 285 }; 286 287 const struct mtk_mipitx_data mt8173_mipitx_data = { 288 .mppll_preserve = 0, 289 .mipi_tx_clk_ops = &mtk_mipi_tx_pll_ops, 290 .mipi_tx_enable_signal = mtk_mipi_tx_power_on_signal, 291 .mipi_tx_disable_signal = mtk_mipi_tx_power_off_signal, 292 }; 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