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Searched refs:SW (Results 1 – 25 of 105) sorted by relevance

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/openbmc/linux/arch/ia64/kernel/
H A Dentry.h25 #define SW(f) (IA64_SWITCH_STACK_##f##_OFFSET) macro
43 .savesp ar.unat,SW(CALLER_UNAT)+16+(off); \
44 .savesp ar.fpsr,SW(AR_FPSR)+16+(off); \
45 .spillsp f2,SW(F2)+16+(off); .spillsp f3,SW(F3)+16+(off); \
46 .spillsp f4,SW(F4)+16+(off); .spillsp f5,SW(F5)+16+(off); \
47 .spillsp f16,SW(F16)+16+(off); .spillsp f17,SW(F17)+16+(off); \
48 .spillsp f18,SW(F18)+16+(off); .spillsp f19,SW(F19)+16+(off); \
49 .spillsp f20,SW(F20)+16+(off); .spillsp f21,SW(F21)+16+(off); \
50 .spillsp f22,SW(F22)+16+(off); .spillsp f23,SW(F23)+16+(off); \
51 .spillsp f24,SW(F24)+16+(off); .spillsp f25,SW(F25)+16+(off); \
[all …]
H A Dentry.S245 adds r14=SW(R4)+16,sp
255 adds r15=SW(R5)+16,sp
259 add r14=SW(R4)+16,sp
261 st8.spill [r14]=r4,SW(R6)-SW(R4) // spill r4 and prefetch offset 0x1c0
269 adds r15=SW(R5)+16,sp
272 st8.spill [r15]=r5,SW(R7)-SW(R5) // spill r5
274 add r2=SW(F2)+16,sp // r2 = &sw->f2
276 st8.spill [r14]=r6,SW(B0)-SW(R6) // spill r6
278 add r3=SW(F3)+16,sp // r3 = &sw->f3
285 st8.spill [r15]=r7,SW(B2)-SW(R7) // spill r7
[all …]
H A Dmca_asm.S567 add temp1=SW(F2), regs
568 add temp2=SW(F3), regs
603 stf.spill [temp1]=f30,SW(B2)-SW(F30)
604 stf.spill [temp2]=f31,SW(B3)-SW(F31)
613 st8 [temp1]=temp3,SW(AR_LC)-SW(B4) // save b4
726 add temp1=SW(F2), regs
727 add temp2=SW(F3), regs
762 ldf.fill f30=[temp1],SW(B2)-SW(F30)
763 ldf.fill f31=[temp2],SW(B3)-SW(F31)
770 ld8 temp3=[temp1],SW(AR_LC)-SW(B4) // restore b4
H A Dunwind.c2253 unw.sw_off[unw.preg_index[UNW_REG_PRI_UNAT_GR]] = SW(CALLER_UNAT); in unw_init()
2254 unw.sw_off[unw.preg_index[UNW_REG_BSPSTORE]] = SW(AR_BSPSTORE); in unw_init()
2255 unw.sw_off[unw.preg_index[UNW_REG_PFS]] = SW(AR_PFS); in unw_init()
2256 unw.sw_off[unw.preg_index[UNW_REG_RP]] = SW(B0); in unw_init()
2257 unw.sw_off[unw.preg_index[UNW_REG_UNAT]] = SW(CALLER_UNAT); in unw_init()
2258 unw.sw_off[unw.preg_index[UNW_REG_PR]] = SW(PR); in unw_init()
2259 unw.sw_off[unw.preg_index[UNW_REG_LC]] = SW(AR_LC); in unw_init()
2260 unw.sw_off[unw.preg_index[UNW_REG_FPSR]] = SW(AR_FPSR); in unw_init()
2261 for (i = UNW_REG_R4, off = SW(R4); i <= UNW_REG_R7; ++i, off += 8) in unw_init()
2263 for (i = UNW_REG_B1, off = SW(B1); i <= UNW_REG_B5; ++i, off += 8) in unw_init()
[all …]
/openbmc/qemu/audio/
H A Daudio_template.h30 #define SW SWVoiceOut macro
35 #define SW SWVoiceIn macro
103 static void glue (audio_pcm_sw_free_resources_, TYPE) (SW *sw) in glue()
115 static int glue (audio_pcm_sw_alloc_resources_, TYPE) (SW *sw) in glue()
159 SW *sw, in glue()
202 static void glue (audio_pcm_sw_fini_, TYPE) (SW *sw) in glue()
209 static void glue (audio_pcm_hw_add_sw_, TYPE) (HW *hw, SW *sw) in glue()
214 static void glue (audio_pcm_hw_del_sw_, TYPE) (SW *sw) in glue()
422 static SW *glue(audio_pcm_create_voice_pair_, TYPE)( in glue()
428 SW *sw; in glue()
[all …]
/openbmc/linux/Documentation/misc-devices/
H A Deeprom.rst38 Atmel 34C02B 2K 0x50 - 0x57, SW write protect at 0x30-37
39 Catalyst 34FC02 2K 0x50 - 0x57, SW write protect at 0x30-37
40 Catalyst 34RC02 2K 0x50 - 0x57, SW write protect at 0x30-37
41 Fairchild 34W02 2K 0x50 - 0x57, SW write protect at 0x30-37
42 Microchip 24AA52 2K 0x50 - 0x57, SW write protect at 0x30-37
43 ST M34C02 2K 0x50 - 0x57, SW write protect at 0x30-37
/openbmc/linux/arch/parisc/include/asm/
H A Dfloppy.h28 #define SW fd_routine[use_virtual_dma&1] macro
40 #define fd_get_dma_residue() SW._get_dma_residue(FLOPPY_DMA)
41 #define fd_dma_mem_alloc(size) SW._dma_mem_alloc(size)
42 #define fd_dma_setup(addr, size, mode, io) SW._dma_setup(addr, size, mode, io)
/openbmc/linux/arch/x86/include/asm/
H A Dfloppy.h30 #define SW fd_routine[use_virtual_dma & 1] macro
42 #define fd_get_dma_residue() SW._get_dma_residue(FLOPPY_DMA)
43 #define fd_dma_mem_alloc(size) SW._dma_mem_alloc(size)
44 #define fd_dma_setup(addr, size, mode, io) SW._dma_setup(addr, size, mode, io)
/openbmc/u-boot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-core.h98 #define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW)
180 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
192 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
203 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
213 .flags = FLAG(GATE, SW)|FLAG(GATE, SW_MANAGED)| \
/openbmc/u-boot/arch/arm/cpu/armv7/bcm281xx/
H A Dclk-core.h98 #define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW)
180 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
192 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
203 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
213 .flags = FLAG(GATE, SW)|FLAG(GATE, SW_MANAGED)| \
/openbmc/linux/drivers/clk/bcm/
H A Dclk-kona.h49 #define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW)
157 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
169 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
180 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
190 .flags = FLAG(GATE, SW)|FLAG(GATE, SW_MANAGED)| \
/openbmc/u-boot/board/freescale/t104xrdb/
H A DREADME285 NOR boot SW setting:
290 NAND boot SW setting:
295 SPI boot SW setting:
300 SD boot SW setting:
307 NOR boot SW setting:
312 NAND boot SW setting:
317 SPI boot SW setting:
322 SD boot SW setting:
/openbmc/openbmc/meta-arm/meta-arm-bsp/documentation/corstone1000/
H A Dchange-log.rst24 - SW components upgrades.
92 - SW components upgrades
164 - SW components upgrades
230 - Upgrading the SW stack recipes
296 - Upgrading the SW stack recipes
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos5250-arndale.dts39 label = "SW-TACT2";
46 label = "SW-TACT3";
53 label = "SW-TACT4";
60 label = "SW-TACT5";
67 label = "SW-TACT6";
74 label = "SW-TACT7";
/openbmc/linux/Documentation/devicetree/bindings/power/reset/
H A Dst-reset.txt1 *Device-Tree bindings for ST SW reset functionality
/openbmc/u-boot/doc/
H A DREADME.omap368 To make U-Boot for OMAP3 support NAND device SW or HW ECC calculation, U-Boot
73 To be compatible with NAND drivers using SW ECC (e.g. kernel code)
77 enables SW ECC calculation. HW ECC enabled with
/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-driver-hid-corsair5 Description: Get/set the current playback mode. "SW" for software mode
/openbmc/linux/Documentation/devicetree/bindings/reset/
H A Dsnps,hsdk-reset.txt10 configuration register and second for corresponding SW reset and status bits
/openbmc/u-boot/arch/arm/mach-zynqmp/
H A DKconfig157 bool "SW USBHOST_MODE"
160 bool "SW SATA_MODE"
/openbmc/linux/Documentation/networking/device_drivers/wifi/intel/
H A Dipw2100.rst178 1 SW based RF kill active (radio off)
180 3 Both HW and SW RF kill active (radio off)
186 0 If SW based RF kill active, turn the radio back on
187 1 If radio is on, activate SW based RF kill
192 If you enable the SW based RF kill and then toggle the HW
/openbmc/linux/arch/powerpc/kernel/
H A Dalign.c41 #define SW 0x20 /* byte swap */ macro
227 if (flags & SW) { in emulate_spe()
/openbmc/linux/Documentation/hwmon/
H A Dfam15h_power.rst102 iii. At time x, SW reads CpuSwPwrAcc MSR and samples the PTSC.
106 iv. At time y, SW reads CpuSwPwrAcc MSR and samples the PTSC.
/openbmc/u-boot/arch/arm/dts/
H A Dr8a77995-draak.dts207 * CVBS and HDMI inputs through SW[49-53]
243 * CVBS and HDMI inputs through SW[49-53]
/openbmc/openbmc/meta-arm/meta-arm/recipes-bsp/trusted-firmware-a/files/
H A D0001-qemu_measured_boot.c-ignore-TPM-error-and-continue-w.patch10 missing TPM is detected further up the SW stack and correct
/openbmc/linux/Documentation/hid/
H A Dhid-alps.rst149 SW ON/OFF status
174 SW ON/OFF status

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