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Searched refs:SSSR (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/input/mouse/
H A Dnavpoint.c124 status = pxa_ssp_read_reg(ssp, SSSR); in navpoint_irq()
128 pxa_ssp_write_reg(ssp, SSSR, (status & sssr)); in navpoint_irq()
143 status = pxa_ssp_read_reg(ssp, SSSR); in navpoint_irq()
158 pxa_ssp_write_reg(ssp, SSSR, sssr); in navpoint_up()
164 if (!(pxa_ssp_read_reg(ssp, SSSR) & SSSR_CSS)) in navpoint_up()
/openbmc/linux/sound/soc/pxa/
H A Dpxa-ssp.c60 pxa_ssp_read_reg(ssp, SSPSP), pxa_ssp_read_reg(ssp, SSSR), in dump_registers()
144 __raw_writel(sssr, ssp->mmio_base + SSSR); in pxa_ssp_resume()
493 while (pxa_ssp_read_reg(ssp, SSSR) & SSSR_BSY) in pxa_ssp_configure_dai_fmt()
681 uint32_t sssr = pxa_ssp_read_reg(ssp, SSSR); in pxa_ssp_set_running_bit()
701 pxa_ssp_write_reg(ssp, SSSR, sssr); in pxa_ssp_set_running_bit()
721 val = pxa_ssp_read_reg(ssp, SSSR); in pxa_ssp_trigger()
722 pxa_ssp_write_reg(ssp, SSSR, val); in pxa_ssp_trigger()
/openbmc/linux/drivers/spi/
H A Dspi-pxa2xx.h102 return pxa2xx_spi_read(drv_data, SSSR) & bits; in read_SSSR_bits()
111 pxa2xx_spi_write(drv_data, SSSR, val); in write_SSSR_CS()
H A Dspi-pxa2xx.c432 pxa2xx_spi_write(drv_data, SSSR, spi_get_chipselect(spi, 0)); in cs_assert()
451 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY && in cs_deassert()
474 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit); in pxa2xx_spi_flush()
657 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT); in interrupt_transfer()
746 status = pxa2xx_spi_read(drv_data, SSSR); in ssp_int()
1034 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr); in pxa2xx_spi_transfer_one()
/openbmc/linux/include/linux/
H A Dpxa2xx_ssp.h36 #define SSSR (0x08) /* SSP Status Register */ macro
/openbmc/qemu/hw/arm/
H A Dstrongarm.c1382 #define SSSR 0x74 /* SSP Status register */ macro
1446 case SSSR: in strongarm_ssp_read()
1499 case SSSR: in strongarm_ssp_write()
/openbmc/linux/sound/soc/intel/catpt/
H A Ddsp.c344 catpt_writel_ssp(cdev, i, SSSR, CATPT_SSS_DEFAULT); in catpt_dsp_set_regs_defaults()
/openbmc/u-boot/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2061 #define SSSR 0x41000008 /* SSP Status Register */ macro