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Searched refs:SSCG_PLL_REF_DIVR2_VAL (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-imx/imx8m/
H A Dclock.c594 val |= SSCG_PLL_REF_DIVR2_VAL(29); in dram_pll_init()
606 val |= SSCG_PLL_REF_DIVR2_VAL(29); in dram_pll_init()
618 val |= SSCG_PLL_REF_DIVR2_VAL(29); in dram_pll_init()
630 val |= SSCG_PLL_REF_DIVR2_VAL(30); in dram_pll_init()
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dclock.h568 #define SSCG_PLL_REF_DIVR2_VAL(n) (((n) << 19) & SSCG_PLL_REF_DIVR2_MASK) macro