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Searched refs:SSCG_PLL_REF_DIVR2_MASK (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-imx/imx8m/
H A Dclock.c226 divr2 = (pll_cfg2 & SSCG_PLL_REF_DIVR2_MASK) >> in decode_sscg_pll()
590 SSCG_PLL_REF_DIVR2_MASK); in dram_pll_init()
602 SSCG_PLL_REF_DIVR2_MASK); in dram_pll_init()
614 SSCG_PLL_REF_DIVR2_MASK); in dram_pll_init()
626 SSCG_PLL_REF_DIVR2_MASK); in dram_pll_init()
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dclock.h566 #define SSCG_PLL_REF_DIVR2_MASK (0x3f << 19) macro
568 #define SSCG_PLL_REF_DIVR2_VAL(n) (((n) << 19) & SSCG_PLL_REF_DIVR2_MASK)