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Searched refs:SSCG_PLL_FEEDBACK_DIV_F2_VAL (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-imx/imx8m/
H A Dclock.c592 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11); in dram_pll_init()
604 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(17); in dram_pll_init()
616 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11); in dram_pll_init()
628 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(8); in dram_pll_init()
706 SSCG_PLL_FEEDBACK_DIV_F2_VAL(3); in sscg_pll_init()
721 SSCG_PLL_FEEDBACK_DIV_F2_VAL(4); in sscg_pll_init()
736 SSCG_PLL_FEEDBACK_DIV_F2_VAL(3); in sscg_pll_init()
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dclock.h575 #define SSCG_PLL_FEEDBACK_DIV_F2_VAL(n) (((n) << 7) & \ macro