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Searched refs:SRDS_PLLCR0_FRATE_SEL_3_0 (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dfsl_corenet2_serdes.c239 case SRDS_PLLCR0_FRATE_SEL_3_0: in serdes_init()
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dimmap_85xx.h2559 #define SRDS_PLLCR0_FRATE_SEL_3_0 0x000a0000 macro