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Searched refs:SRC_A7RCR0 (Results 1 – 4 of 4) sorted by relevance

/openbmc/qemu/hw/misc/
H A Dimx7_src.c31 case SRC_A7RCR0: in imx7_src_reg_name()
141 s->regs[SRC_A7RCR0] = deposit32(s->regs[SRC_A7RCR0], ri->reset_bit, 1, 0); in imx7_clear_reset_bit()
143 trace_imx7_src_write(imx7_src_reg_name(SRC_A7RCR0), s->regs[SRC_A7RCR0]); in imx7_clear_reset_bit()
181 trace_imx7_src_write(imx7_src_reg_name(SRC_A7RCR0), s->regs[SRC_A7RCR0]); in imx7_src_write()
186 case SRC_A7RCR0: in imx7_src_write()
/openbmc/linux/drivers/reset/
H A Dreset-imx7.c37 SRC_A7RCR0 = 0x0004, enumerator
58 [IMX7_RESET_A7_CORE_POR_RESET0] = { SRC_A7RCR0, BIT(0) },
59 [IMX7_RESET_A7_CORE_POR_RESET1] = { SRC_A7RCR0, BIT(1) },
60 [IMX7_RESET_A7_CORE_RESET0] = { SRC_A7RCR0, BIT(4) },
61 [IMX7_RESET_A7_CORE_RESET1] = { SRC_A7RCR0, BIT(5) },
62 [IMX7_RESET_A7_DBG_RESET0] = { SRC_A7RCR0, BIT(8) },
63 [IMX7_RESET_A7_DBG_RESET1] = { SRC_A7RCR0, BIT(9) },
64 [IMX7_RESET_A7_ETM_RESET0] = { SRC_A7RCR0, BIT(12) },
65 [IMX7_RESET_A7_ETM_RESET1] = { SRC_A7RCR0, BIT(13) },
66 [IMX7_RESET_A7_SOC_DBG_RESET] = { SRC_A7RCR0, BIT(20) },
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/openbmc/qemu/include/hw/misc/
H A Dimx7_src.h18 #define SRC_A7RCR0 1 macro
/openbmc/u-boot/arch/arm/mach-imx/mx7/
H A Dpsci-mx7.c82 #define SRC_A7RCR0 0x004 macro