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Searched refs:SPRN_L2CSR1 (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/arch/powerpc/include/asm/
H A Dprocessor.h522 #define SPRN_L2CSR1 0x3fa /* L2 Data Cache Control and Status Register 1 */ macro
740 #define L2CSR1 SPRN_L2CSR1
/openbmc/linux/arch/powerpc/include/asm/
H A Dreg_booke.h179 #define SPRN_L2CSR1 0x3FA /* L2 Data Cache Control and Status Register 1 */ macro
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Drelease.S276 mtspr SPRN_L2CSR1,r3
H A Dcpu_init.c690 mtspr(SPRN_L2CSR1, (32 + 1)); in l2cache_init()