Searched refs:SPRN_DCWR (Results 1 – 3 of 3) sorted by relevance
73 mtspr(SPRN_DCWR, 0x00000000); /* All caching is write-back */ in MMU_init_hw()
167 #define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ macro
181 #define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ macro