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Searched refs:SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h7724 #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x00000300L macro
H A Dgfx_7_2_sh_mask.h8303 #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x300 macro
H A Dgfx_8_1_sh_mask.h9943 #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x300 macro
H A Dgfx_8_0_sh_mask.h9545 #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x300 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h15544 #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK … macro
H A Dgc_9_1_sh_mask.h16853 #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK … macro
H A Dgc_9_2_1_sh_mask.h16728 #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK … macro
H A Dgc_9_4_3_sh_mask.h19027 #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK … macro
H A Dgc_9_4_2_sh_mask.h8977 #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK … macro
H A Dgc_11_0_0_sh_mask.h20651 #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK … macro
H A Dgc_10_1_0_sh_mask.h23049 #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK … macro
H A Dgc_11_0_3_sh_mask.h22981 #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK … macro
H A Dgc_10_3_0_sh_mask.h21158 #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK … macro