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Searched refs:SOR_LANE_SEQ_CTL (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/drivers/gpu/drm/tegra/
H A Dsor.h156 #define SOR_LANE_SEQ_CTL 0x21 macro
H A Dsor.c677 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_power_up_lanes()
682 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_power_up_lanes()
709 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_power_down_lanes()
714 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_power_down_lanes()
1566 DEBUGFS_REG32(SOR_LANE_SEQ_CTL),
2316 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2325 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2328 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()