Searched refs:SOFT_RST (Results 1 – 6 of 6) sorted by relevance
| /openbmc/linux/Documentation/devicetree/bindings/power/reset/ |
| H A D | ocelot-reset.txt | 3 The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the
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| /openbmc/linux/drivers/i3c/master/mipi-i3c-hci/ |
| H A D | core.c | 77 #define SOFT_RST BIT(0) /* Core Reset */ macro
650 !(regval & SOFT_RST), 1, 10000); in i3c_hci_init()
653 reg_write(RESET_CONTROL, SOFT_RST); in i3c_hci_init()
655 !(regval & SOFT_RST), 1, 10000); in i3c_hci_init()
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| /openbmc/qemu/hw/misc/ |
| H A D | zynq_slcr.c | 103 FIELD(PSS_RST_CTRL, SOFT_RST, 0, 1)
568 if (FIELD_EX32(val, PSS_RST_CTRL, SOFT_RST)) { in zynq_slcr_write()
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| /openbmc/linux/drivers/net/ethernet/qualcomm/emac/ |
| H A D | emac.h | 108 #define SOFT_RST 0x1 macro
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| H A D | emac-mac.c | 474 emac_reg_update32(adpt->base + EMAC_DMA_MAS_CTRL, 0, SOFT_RST); in emac_mac_reset()
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| /openbmc/linux/sound/soc/sh/ |
| H A D | fsi.c | 1251 fsi_master_mask_set(master, SOFT_RST, IR, 0); in fsi_interrupt()
1252 fsi_master_mask_set(master, SOFT_RST, IR, IR); in fsi_interrupt()
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