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Searched refs:SIFIVE_E_DEV_UART1 (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/include/hw/riscv/
H A Dsifive_e.h71 SIFIVE_E_DEV_UART1, enumerator
/openbmc/qemu/hw/riscv/
H A Dsifive_e.c64 [SIFIVE_E_DEV_UART1] = { 0x10023000, 0x1000 },
267 sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART1].base, in sifive_e_soc_realize()