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Searched refs:SIFIVE_E_DEV_CLINT (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/hw/riscv/
H A Dsifive_e.c55 [SIFIVE_E_DEV_CLINT] = { 0x2000000, 0x10000 },
221 riscv_aclint_swi_create(memmap[SIFIVE_E_DEV_CLINT].base, in sifive_e_soc_realize()
223 riscv_aclint_mtimer_create(memmap[SIFIVE_E_DEV_CLINT].base + in sifive_e_soc_realize()
/openbmc/qemu/include/hw/riscv/
H A Dsifive_e.h62 SIFIVE_E_DEV_CLINT, enumerator