| /openbmc/qemu/target/arm/tcg/ |
| H A D | iwmmxt_helper.c | 82 #define SADB(SHR) abs((int) ((a >> SHR) & 0xff) - (int) ((b >> SHR) & 0xff)) in HELPER() argument
91 #define SADW(SHR) \ in HELPER() argument
92 abs((int) ((a >> SHR) & 0xffff) - (int) ((b >> SHR) & 0xffff)) in HELPER()
99 #define MULS(SHR) ((uint64_t) ((( \ in HELPER() argument
100 EXTEND16S((a >> SHR) & 0xffff) * EXTEND16S((b >> SHR) & 0xffff) \ in HELPER()
101 ) >> 0) & 0xffff) << SHR) in HELPER()
108 #define MULS(SHR) ((uint64_t) ((( \ in HELPER() argument
109 EXTEND16S((a >> SHR) & 0xffff) * EXTEND16S((b >> SHR) & 0xffff) \ in HELPER()
110 ) >> 16) & 0xffff) << SHR) in HELPER()
117 #define MULU(SHR) ((uint64_t) ((( \ in HELPER() argument
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| /openbmc/u-boot/lib/ |
| H A D | sha256.c | 81 #define SHR(x,n) ((x & 0xFFFFFFFF) >> n) in sha256_process() macro
82 #define ROTR(x,n) (SHR(x,n) | (x << (32 - n))) in sha256_process()
84 #define S0(x) (ROTR(x, 7) ^ ROTR(x,18) ^ SHR(x, 3)) in sha256_process()
85 #define S1(x) (ROTR(x,17) ^ ROTR(x,19) ^ SHR(x,10)) in sha256_process()
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| /openbmc/u-boot/include/ |
| H A D | lattice.h | 149 #define SHR 0x23 /* macro
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| /openbmc/qemu/target/i386/ |
| H A D | ops_sse.h | 1552 #define SHR(v, i) (i < 64 && i > -64 ? i > 0 ? v >> (i) : (v << -(i)) : 0) in SSE_HELPER_W() macro
1554 d->Q(0) = SHR(s->Q(0), shift - 0) | in SSE_HELPER_W()
1555 SHR(v->Q(0), shift - 64); in SSE_HELPER_W()
1560 r0 = SHR(s->Q(i), shift - 0) | in SSE_HELPER_W()
1561 SHR(s->Q(i + 1), shift - 64) | in SSE_HELPER_W()
1562 SHR(v->Q(i), shift - 128) | in SSE_HELPER_W()
1563 SHR(v->Q(i + 1), shift - 192); in SSE_HELPER_W()
1564 r1 = SHR(s->Q(i), shift + 64) | in SSE_HELPER_W()
1565 SHR(s->Q(i + 1), shift - 0) | in SSE_HELPER_W()
1566 SHR(v->Q(i), shift - 64) | in SSE_HELPER_W()
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| /openbmc/u-boot/drivers/fpga/ |
| H A D | ivm_core.c | 968 case SHR: in ispVMCode()
1282 ispVMBitShift(SHR, g_usShiftValue); in ispVMDataCode()
1952 case SHR: in ispVMBitShift()
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| /openbmc/linux/Documentation/admin-guide/thermal/ |
| H A D | intel_powerclamp.rst | 311 PID USER PR NI VIRT RES SHR S %CPU %MEM TIME+ COMMAND
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| /openbmc/qemu/tests/tcg/i386/ |
| H A D | x86.csv | 14 # 1. The Intel manual instruction mnemonic. For example, "SHR r/m32, imm8".
31 # the Intel mnemonic. For example, "rw,r" to denote that "SHR r/m32, imm8"
1961 "SHR r/m8, 1","SHRB 1, r/m8","shrb 1, r/m8","D0 /5","V","V","","","rw,r","Y","8"
1962 "SHR r/m8, 1","SHRB 1, r/m8","shrb 1, r/m8","REX D0 /5","N.E.","V","","pseudo64","rw,r","Y","8"
1963 "SHR r/m8, CL","SHRB CL, r/m8","shrb CL, r/m8","D2 /5","V","V","","","rw,r","Y","8"
1964 "SHR r/m8, CL","SHRB CL, r/m8","shrb CL, r/m8","REX D2 /5","N.E.","V","","pseudo64","rw,r","Y","8"
1965 "SHR r/m8, imm8","SHRB imm8, r/m8","shrb imm8, r/m8","REX C0 /5 ib","N.E.","V","","pseudo64","rw,r"…
1966 "SHR r/m8, imm8u","SHRB imm8u, r/m8","shrb imm8u, r/m8","C0 /5 ib","V","V","","","rw,r","Y","8"
1967 "SHR r/m32, 1","SHRL 1, r/m32","shrl 1, r/m32","D1 /5","V","V","","operand32","rw,r","Y","32"
1968 "SHR r/m32, CL","SHRL CL, r/m32","shrl CL, r/m32","D3 /5","V","V","","operand32","rw,r","Y","32"
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| /openbmc/linux/tools/arch/x86/lib/ |
| H A D | x86-opcode-map.txt | 999 5: SHR
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| /openbmc/linux/arch/x86/lib/ |
| H A D | x86-opcode-map.txt | 999 5: SHR
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| /openbmc/qemu/target/i386/tcg/ |
| H A D | emit.c.inc | 3332 * SHR/RCR/SHR/RCR/... is a relatively common occurrence of RCR.
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| /openbmc/openbmc/poky/meta/recipes-bsp/v86d/v86d/ |
| H A D | Update-x86emu-from-X.org.patch | 16675 Implements the SHR instruction and side effects.
16747 Implements the SHR instruction and side effects.
16814 Implements the SHR instruction and side effects.
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