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Searched refs:SET_RS1 (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dinstmap.h323 #define SET_RS1(inst, val) deposit32(inst, 15, 5, val) macro
H A Dcpu_helper.c1760 xinsn = SET_RS1(xinsn, (taddr - (env->gpr[access_rs1] + access_imm)) & in riscv_transformed_insn()