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Searched refs:SDMA0_HWIP (Results 1 – 22 of 22) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v4_0.c399 return (adev->reg_offset[SDMA0_HWIP][0][0] + offset); in sdma_v4_0_get_reg_offset()
472 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v4_0_init_golden_registers()
542 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v4_0_setup_ulv()
581 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) || in sdma_v4_0_init_microcode()
582 adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0)) { in sdma_v4_0_init_microcode()
981 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && in sdma_v4_0_ctx_switch_enable()
1258 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v4_0_init_pg()
1701 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v4_0_fw_support_paging_queue()
1726 if ((adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 0, 0)) && in sdma_v4_0_early_init()
1826 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && i >= 5) in sdma_v4_0_sw_init()
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H A Damdgpu_discovery.c183 [SDMA0_HWIP] = SDMA0_HWID,
1976 switch (adev->ip_versions[SDMA0_HWIP][0]) { in amdgpu_discovery_set_sdma_ip_blocks()
2016 adev->ip_versions[SDMA0_HWIP][0]); in amdgpu_discovery_set_sdma_ip_blocks()
2167 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0); in amdgpu_discovery_set_ip_blocks()
2189 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1); in amdgpu_discovery_set_ip_blocks()
2213 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1); in amdgpu_discovery_set_ip_blocks()
2229 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0); in amdgpu_discovery_set_ip_blocks()
2250 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0); in amdgpu_discovery_set_ip_blocks()
2274 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2); in amdgpu_discovery_set_ip_blocks()
2302 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0); in amdgpu_discovery_set_ip_blocks()
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H A Ddimgrey_cavefish_reg_init.c46 adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
H A Damdgpu_sdma.c213 amdgpu_ucode_ip_version_decode(adev, SDMA0_HWIP, ucode_prefix, sizeof(ucode_prefix)); in amdgpu_sdma_init_microcode()
254 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 2) && in amdgpu_sdma_init_microcode()
H A Daldebaran_reg_init.c43 adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i])); in aldebaran_reg_base_init()
H A Darct_reg_init.c44 adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i])); in arct_reg_base_init()
H A Dvega10_reg_init.c47 adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i])); in vega10_reg_base_init()
H A Dsdma_v4_4.c40 uint32_t sdma_base = adev->reg_offset[SDMA0_HWIP][0][0]; in sdma_v4_4_get_reg_offset()
H A Dvega20_reg_init.c46 adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i])); in vega20_reg_base_init()
H A Daqua_vanjaram.c224 case SDMA0_HWIP: in aqua_vanjaram_logical_to_dev_inst()
275 { SDMA0_HWIP, adev->sdma.sdma_mask }, in aqua_vanjaram_ip_map_init()
H A Damdgpu_ucode.c1140 } else if (block_type == SDMA0_HWIP) { in amdgpu_ucode_legacy_naming()
1141 switch (adev->ip_versions[SDMA0_HWIP][0]) { in amdgpu_ucode_legacy_naming()
1288 case SDMA0_HWIP: in amdgpu_ucode_ip_version_decode()
H A Dsdma_v4_4_2.c64 return (adev->reg_offset[SDMA0_HWIP][dev_inst][0] + offset); in sdma_v4_4_2_get_reg_offset()
135 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 2)) { in sdma_v4_4_2_init_microcode()
1235 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v4_4_2_fw_support_paging_queue()
1405 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 2)) in sdma_v4_4_2_sw_fini()
H A Dsdma_v5_2.c1525 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v5_2_firmware_mgcg_support()
1591 …if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2,… in sdma_v5_2_update_medium_grain_light_sleep()
1620 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v5_2_set_clockgating_state()
H A Damdgpu_fence.c573 if (adev->ip_versions[SDMA0_HWIP][0] >= IP_VERSION(5, 0, 0)) in amdgpu_fence_need_ring_interrupt_restore()
H A Dsdma_v5_0.c187 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v5_0_init_golden_registers()
1700 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v5_0_set_clockgating_state()
H A Damdgpu.h638 SDMA0_HWIP, enumerator
H A Damdgpu_mes.c135 if (adev->ip_versions[SDMA0_HWIP][0] < IP_VERSION(6, 0, 0)) in amdgpu_mes_init()
H A Dsdma_v6_0.c1249 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v6_0_set_ras_funcs()
H A Damdgpu_kms.c497 result->ip_discovery_version = adev->ip_versions[SDMA0_HWIP][0]; in amdgpu_hw_ip_info()
H A Damdgpu_device.c2995 (adev->ip_versions[SDMA0_HWIP][0] >= IP_VERSION(5, 0, 0)) && in amdgpu_device_ip_suspend_phase2()
/openbmc/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_packet_manager_v9.c208 return dev->adev->ip_versions[SDMA0_HWIP][0] >= IP_VERSION(5, 2, 0); in pm_use_ext_eng()
H A Dkfd_device.c68 uint32_t sdma_version = kfd->adev->ip_versions[SDMA0_HWIP][0]; in kfd_device_info_set_sdma_info()