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Searched refs:SDC (Results 1 – 10 of 10) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dbrcm,bcm2835-armctrl-ic.txt82 3: SDC
/openbmc/linux/drivers/gpu/drm/radeon/
H A Dsumod.h204 # define SDC(x) ((x) << 9) macro
H A Dr600_dpm.c417 WREG32_P(CG_CTX_CGTT3D_R, SDC(s), ~SDC_MASK); in r600_set_ctxcgtt3d_rsdc()
432 WREG32_P(CG_VDDC3D_OOR, SDC(s), ~SDC_MASK); in r600_set_vddc3d_oorsdc()
H A Dr600d.h1423 # define SDC(x) ((x) << 9) macro
H A Dsumo_dpm.c139 WREG32(CG_GCOOR, PHC(grs) | SDC(p) | SU(u)); in sumo_program_grsd()
/openbmc/linux/drivers/input/serio/
H A DKconfig130 The SDC itself contains a 10ms resolution timer/clock capable
132 The SDC may also be connected to a battery-backed real-time
/openbmc/u-boot/arch/arm/mach-tegra/tegra20/
H A Dpinmux.c322 PIN(SDC, PWM, TWC, SDIO3, SPI3),
/openbmc/qemu/include/hw/misc/
H A Dbcm2835_cprman_internals.h704 FILL_CLOCK_MUX_INIT_INFO(SDC, core),
/openbmc/linux/drivers/input/misc/
H A DKconfig553 tristate "HP SDC Real Time Clock"
558 of the HP SDC controller.
/openbmc/openbmc/meta-arm/meta-arm-bsp/documentation/corstone1000/
H A Duser-guide.rst1820 The MPS3 supports Authenticated Debug Access Control (ADAC), using the CoreSight SDC-600 IP.
1824 - `CoreSight SDC-600 <https://developer.arm.com/Processors/CoreSight%20SDC-600>`__