Searched refs:SCLK_UPHY0_TCPDCORE (Results 1 – 6 of 6) sorted by relevance
/openbmc/linux/Documentation/devicetree/bindings/phy/ |
H A D | phy-rockchip-typec.txt | 11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or 43 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 46 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
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/openbmc/u-boot/include/dt-bindings/clock/ |
H A D | rk3399-cru.h | 82 #define SCLK_UPHY0_TCPDCORE 126 macro
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/openbmc/linux/include/dt-bindings/clock/ |
H A D | rk3399-cru.h | 83 #define SCLK_UPHY0_TCPDCORE 126 macro
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/openbmc/u-boot/arch/arm/dts/ |
H A D | rk3399.dtsi | 1043 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1401 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1404 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
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/openbmc/linux/arch/arm64/boot/dts/rockchip/ |
H A D | rk3399.dtsi | 1162 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1630 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1633 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
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/openbmc/linux/drivers/clk/rockchip/ |
H A D | clk-rk3399.c | 456 COMPOSITE(SCLK_UPHY0_TCPDCORE, "clk_uphy0_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, 0,
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