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Searched refs:SCLK_SRC_ISP_VAL (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-exynos/
H A Dexynos5_setup.h171 #define SCLK_SRC_ISP_VAL (SPI1_ISP_SEL << 4) \ macro
H A Dclock_init_exynos5.c766 writel(SCLK_SRC_ISP_VAL, &clk->sclk_src_isp); in exynos5250_system_clock_init()