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Searched refs:SCLK_PCIEPHY_REF (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Drockchip-pcie-phy.txt31 clocks = <&cru SCLK_PCIEPHY_REF>;
/openbmc/u-boot/include/dt-bindings/clock/
H A Drk3399-cru.h94 #define SCLK_PCIEPHY_REF 138 macro
/openbmc/linux/include/dt-bindings/clock/
H A Drk3399-cru.h95 #define SCLK_PCIEPHY_REF 138 macro
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-nanopi4.dtsi508 assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
H A Drk3399.dtsi1618 clocks = <&cru SCLK_PCIEPHY_REF>;
/openbmc/u-boot/arch/arm/dts/
H A Drk3399-puma.dtsi457 assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
H A Drk3399.dtsi1389 clocks = <&cru SCLK_PCIEPHY_REF>;
/openbmc/linux/drivers/clk/rockchip/
H A Dclk-rk3399.c916 MUX(SCLK_PCIEPHY_REF, "clk_pciephy_ref", mux_pll_src_24m_pciephy_p, CLK_SET_RATE_PARENT,