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Searched refs:SARL (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/clk/mvebu/
H A Darmada-39x.c32 #define SARL 0 macro
49 tclk_freq_select = ((readl(sar + SARL) >> SARL_A390_TCLK_FREQ_OPT) & in armada_39x_get_tclk_freq()
72 cpu_freq_select = ((readl(sar + SARL) >> SARL_A390_CPU_DDR_L2_FREQ_OPT) & in armada_39x_get_cpu_freq()
H A Darmada-xp.c26 #define SARL 0 /* Low part [0:31] */ macro
73 cpu_freq_select = ((readl(sar + SARL) >> SARL_AXP_PCLK_FREQ_OPT) & in axp_get_cpu_freq()
126 u32 opt = ((readl(sar + SARL) >> SARL_AXP_FAB_FREQ_OPT) & in axp_get_clk_ratio()
H A Darmada-370.c23 #define SARL 0 /* Low part [0:31] */ macro
/openbmc/linux/drivers/net/wan/
H A Dhd64570.h116 #define SARL 0x04 /* TX Source Address L (single block) */ macro
H A Dhd64572.h147 #define SARL 0x80 /* Source Addr Register L (single-block, TX only) */ macro
/openbmc/qemu/tests/tcg/i386/
H A Dx86.csv1816 "SAR r/m32, 1","SARL 1, r/m32","sarl 1, r/m32","D1 /7","V","V","","operand32","rw,r","Y","32"
1817 "SAR r/m32, CL","SARL CL, r/m32","sarl CL, r/m32","D3 /7","V","V","","operand32","rw,r","Y","32"
1818 "SAR r/m32, imm8u","SARL imm8u, r/m32","sarl imm8u, r/m32","C1 /7 ib","V","V","","operand32","rw,r"…