/openbmc/qemu/target/hexagon/ |
H A D | arch.c | 244 float32 RsV, RtV, RdV; in arch_sf_recip_common() local 247 RtV = *Rt; in arch_sf_recip_common() 248 if (float32_is_any_nan(RsV) && float32_is_any_nan(RtV)) { in arch_sf_recip_common() 249 if (extract32(RsV & RtV, 22, 1) == 0) { in arch_sf_recip_common() 252 RdV = RsV = RtV = float32_nan; in arch_sf_recip_common() 257 RdV = RsV = RtV = float32_nan; in arch_sf_recip_common() 258 } else if (float32_is_any_nan(RtV)) { in arch_sf_recip_common() 260 if (extract32(RtV, 22, 1) == 0) { in arch_sf_recip_common() 263 RdV = RsV = RtV = float32_nan; in arch_sf_recip_common() 264 } else if (float32_is_infinity(RsV) && float32_is_infinity(RtV)) { in arch_sf_recip_common() [all …]
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H A D | gen_tcg.h | 173 fGEN_TCG_loadbXw2(fEA_IRs(UiV, RtV, uiV), false) 177 fGEN_TCG_loadbXw2(fEA_IRs(UiV, RtV, uiV), true) 225 fGEN_TCG_loadbXw4(fEA_IRs(UiV, RtV, uiV), false) 229 fGEN_TCG_loadbXw4(fEA_IRs(UiV, RtV, uiV), true) 272 fGEN_TCG_loadalignh(fEA_IRs(UiV, RtV, uiV)) 303 fGEN_TCG_loadalignb(fEA_IRs(UiV, RtV, uiV)) 438 fGEN_TCG_STORE_pcr(0, fSTORE(1, 1, EA, fGETBYTE(0, RtV))) 445 fGEN_TCG_STORE_pcr(1, fSTORE(1, 2, EA, fGETHALF(0, RtV))) 452 fGEN_TCG_STORE_pcr(1, fSTORE(1, 2, EA, fGETHALF(1, RtV))) 459 fGEN_TCG_STORE_pcr(2, fSTORE(1, 4, EA, RtV)) [all …]
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H A D | op_helper.c | 315 uint64_t HELPER(sfrecipa)(CPUHexagonState *env, float32 RsV, float32 RtV) in HELPER() 325 if (arch_sf_recip_common(&RsV, &RtV, &RdV, &adjust, &env->fp_status)) { in HELPER() 327 idx = (RtV >> 16) & 0x7f; in HELPER() 329 exp = SF_BIAS - (float32_getexp(RtV) - SF_BIAS) - 1; in HELPER() 330 RdV = build_float32(extract32(RtV, 31, 1), exp, mant); in HELPER() 921 float32 HELPER(sfadd)(CPUHexagonState *env, float32 RsV, float32 RtV) in HELPER() 925 RdV = float32_add(RsV, RtV, &env->fp_status); in HELPER() 930 float32 HELPER(sfsub)(CPUHexagonState *env, float32 RsV, float32 RtV) in HELPER() 934 RdV = float32_sub(RsV, RtV, &env->fp_status); in HELPER() 939 int32_t HELPER(sfcmpeq)(CPUHexagonState *env, float32 RsV, float32 RtV) in HELPER() [all …]
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H A D | gen_tcg_hvx.h | 241 tcg_gen_andi_tl(shift, RtV, 15); \ 250 tcg_gen_andi_tl(shift, RtV, 15); \ 260 tcg_gen_andi_tl(shift, RtV, 31); \ 269 tcg_gen_andi_tl(shift, RtV, 31); \ 279 tcg_gen_andi_tl(shift, RtV, 7); \ 287 tcg_gen_andi_tl(shift, RtV, 15); \ 295 tcg_gen_andi_tl(shift, RtV, 31); \ 304 tcg_gen_andi_tl(shift, RtV, 7); \ 312 tcg_gen_andi_tl(shift, RtV, 15); \ 321 tcg_gen_andi_tl(shift, RtV, 15); \ [all …]
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H A D | README | 63 Instruction semantics "{ RdV=RsV+RtV;}" 67 RsV, RtV are source registers 86 TCGv RtV = hex_gpr[insn->regno[2]]; 87 gen_helper_A2_add(RdV, tcg_env, RsV, RtV); 92 int32_t HELPER(A2_add)(CPUHexagonState *env, int32_t RsV, int32_t RtV) 96 { RdV=RsV+RtV;} 115 tcg_gen_add_tl(RdV, RsV, RtV)
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H A D | genptr.c | 1044 static void gen_asr_r_r_sat(DisasContext *ctx, TCGv RdV, TCGv RsV, TCGv RtV) in gen_asr_r_r_sat() argument 1050 tcg_gen_sextract_i32(shift_amt, RtV, 0, 7); in gen_asr_r_r_sat() 1066 static void gen_asl_r_r_sat(DisasContext *ctx, TCGv RdV, TCGv RsV, TCGv RtV) in gen_asl_r_r_sat() argument 1072 tcg_gen_sextract_i32(shift_amt, RtV, 0, 7); in gen_asl_r_r_sat() 1138 TCGv_i64 RssV, TCGv RtV) in gen_asr_r_svw_trun() argument 1155 tcg_gen_sextract_tl(shift_amt32, RtV, 0, 7); in gen_asr_r_svw_trun()
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/openbmc/qemu/target/hexagon/imported/ |
H A D | float.idef | 27 { RdV=fUNFLOAT(fFLOAT(RsV)+fFLOAT(RtV));}) 31 { RdV=fUNFLOAT(fFLOAT(RsV)-fFLOAT(RtV));}) 35 { RdV=fUNFLOAT(fSFMPY(fFLOAT(RsV),fFLOAT(RtV)));}) 39 { RxV=fUNFLOAT(fFMAF(fFLOAT(RsV),fFLOAT(RtV),fFLOAT(RxV)));}) 45 fCHECKSFNAN3(RxV,RxV,RsV,RtV); 46 tmp=fUNFLOAT(fFMAFX(fFLOAT(RsV),fFLOAT(RtV),fFLOAT(RxV),PuV)); 47 if (!((fFLOAT(RxV) == 0.0) && fISZEROPROD(fFLOAT(RsV),fFLOAT(RtV)))) RxV = tmp; 52 { RxV=fUNFLOAT(fFMAF(-fFLOAT(RsV),fFLOAT(RtV),fFLOAT(RxV))); }) 58 (fISINFPROD(fFLOAT(RsV),fFLOAT(RtV))) && 59 (fGETBIT(31,RsV ^ RxV ^ RtV) != 0)); [all …]
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H A D | mpy.idef | 24 …)"OSEM, ATR,"",{DST=SATSEM(RNDSEM(ACCSEM SEM( fGETHALF(1,RsV),fGETHALF(1,RtV))));})\ 25 …:<<1"OSEM, ATR,"",{DST=SATSEM(RNDSEM(ACCSEM fSCALE(1,SEM(fGETHALF(1,RsV),fGETHALF(1,RtV)))));})\ 26 …)"OSEM, ATR,"",{DST=SATSEM(RNDSEM(ACCSEM SEM( fGETHALF(1,RsV),fGETHALF(0,RtV))));})\ 27 …:<<1"OSEM, ATR,"",{DST=SATSEM(RNDSEM(ACCSEM fSCALE(1,SEM(fGETHALF(1,RsV),fGETHALF(0,RtV)))));})\ 28 …)"OSEM, ATR,"",{DST=SATSEM(RNDSEM(ACCSEM SEM( fGETHALF(0,RsV),fGETHALF(1,RtV))));})\ 29 …:<<1"OSEM, ATR,"",{DST=SATSEM(RNDSEM(ACCSEM fSCALE(1,SEM(fGETHALF(0,RsV),fGETHALF(1,RtV)))));})\ 30 …)"OSEM, ATR,"",{DST=SATSEM(RNDSEM(ACCSEM SEM( fGETHALF(0,RsV),fGETHALF(0,RtV))));})\ 31 …):<<1"OSEM, ATR,"",{DST=SATSEM(RNDSEM(ACCSEM fSCALE(1,SEM(fGETHALF(0,RsV),fGETHALF(0,RtV)))));}) 54 …OSEM, ATR,"",{DST=SATSEM(RNDSEM(ACCSEM SEM( fGETUHALF(1,RsV),fGETUHALF(1,RtV))));})\ 55 …<1"OSEM, ATR,"",{DST=SATSEM(RNDSEM(ACCSEM fSCALE(1,SEM(fGETUHALF(1,RsV),fGETUHALF(1,RtV)))));})\ [all …]
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H A D | alu.idef | 29 { RdV=RsV+RtV;}) 33 { RdV=RtV-RsV;}) 41 COND_ALU(A2_padd,"Rd32=add(Rs32,Rt32)","Conditionally Add 32-bit registers",RdV=RsV+RtV) 42 COND_ALU(A2_psub,"Rd32=sub(Rt32,Rs32)","Conditionally Subtract 32-bit registers",RdV=RtV-RsV) 44 COND_ALU(A2_pxor,"Rd32=xor(Rs32,Rt32)","Conditionally XOR registers",RdV=RsV^RtV) 45 COND_ALU(A2_pand,"Rd32=and(Rs32,Rt32)","Conditionally AND registers",RdV=RsV&RtV) 46 COND_ALU(A2_por,"Rd32=or(Rs32,Rt32)","Conditionally OR registers",RdV=RsV|RtV) 58 { RdV=fSAT(fSE32_64(RsV)+fSE32_64(RtV)); }) 62 { RdV=fSAT(fSE32_64(RtV) - fSE32_64(RsV)); }) 82 Q6INSN(A2_##TAG##_ll, OPER"(Rt.L32,Rs.L32)"AOPER, ATR,"",{SEM(fGETHALF(0,RtV),fGETHALF(0,RsV));}… [all …]
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H A D | compare.idef | 30 {PdV=f8BITSOF(RsV==RtV);}) 34 {PdV=f8BITSOF(RsV>RtV);}) 38 {PdV=f8BITSOF(fCAST4u(RsV)>fCAST4u(RtV));}) 71 {RdV=(RsV==RtV); }) 75 {RdV=(RsV!=RtV); }) 86 {PdV=f8BITSOF((RsV&RtV)==RtV);}) 90 {PdV=f8BITSOF((RsV&RtV)==0);}) 95 {PdV=f8BITSOF((RsV&RtV)!=RtV);}) 99 {PdV=f8BITSOF((RsV&RtV)!=0);}) 134 …N(C4_cmpneq,"Pd4=!cmp.eq(Rs32,Rt32)",ATTRIBS(), "And-Compare for Equal", {PdV=f8BITSOF(RsV!=RtV);}) [all …]
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H A D | ldst.idef | 25 …"(Rt32<<#u2+#U6)", ATTRIB,DESCR,{fMUST_IMMEXT(UiV); fEA_IRs(UiV,RtV,uiV); SEMANTICS;})\ 116 …rb, "Rt32", "memb","Store Byte",ATTRIBS(A_MEMSIZE_1B,A_STORE),"0",fSTORE(1,1,EA,fGETBYTE(0,RtV)),0) 117 …re Half integer",ATTRIBS(A_REGWRSIZE_2B,A_MEMSIZE_2B,A_STORE),"1",fSTORE(1,2,EA,fGETHALF(0,RtV)),1) 118 …er Half integer",ATTRIBS(A_REGWRSIZE_2B,A_MEMSIZE_2B,A_STORE),"1",fSTORE(1,2,EA,fGETHALF(1,RtV)),1) 119 … "Rt32", "memw","Store Word",ATTRIBS(A_REGWRSIZE_4B,A_MEMSIZE_4B,A_STORE),"2",fSTORE(1,4,EA,RtV),2) 143 …MSIZE_4B,A_STORE,A_RESTRICT_SLOT0ONLY),"Store Release Word", { fEA_REG(RsV); fSTORE(1,4,EA,RtV); }) 146 …MSIZE_4B,A_STORE,A_RESTRICT_SLOT0ONLY),"Store Release Word", { fEA_REG(RsV); fSTORE(1,4,EA,RtV); }) 200 { fEA_REG(RsV); fSTORE_LOCKED(1,4,EA,RtV,PdV) }) 220 Q6INSN(L4_##TAG##_rr, OPER"(Rs32+Rt32<<#u2)", ATTRIB,DESCR,{fEA_RRs(RsV,RtV,uiV); SEMAN… 227 Q6INSN(L4_p##TAG##t_rr, "if (Pv4) "OPER"(Rs32+Rt32<<#u2)", ATTRIB,DESCR,{fEA_RRs(RsV,RtV… [all …]
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H A D | shift.idef | 34 fHIDE(size4s_t) shamt=fSXTN(7,32,RtV);\ 41 fHIDE(size4s_t) shamt=fSXTN(7,32,RtV);\ 48 fHIDE(size4s_t) shamt=fSXTN(7,32,RtV);\ 55 fHIDE(size4s_t) shamt=fSXTN(7,32,RtV);\ 80 fHIDE(size4s_t) shamt=fSXTN(7,32,RtV);\ 87 fHIDE(size4s_t) shamt=fSXTN(7,32,RtV);\ 171 fHIDE(size4s_t) shamt = fSXTN(7,32,RtV); 180 { RdV = RtV + fASHIFTL(RsV,uiV,4_4); }) 309 fHIDE(size4u_t) shamt = fZXTN(5,32,RtV); 485 PdV = f8BITSOF((fCAST4_8u(RsV) & fBIDIR_LSHIFTL(1,fSXTN(7,32,RtV),4_8)) != 0); [all …]
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H A D | branch.idef | 124 STD_CMPJUMP(cmpeq,"cmp.eq(Rs16,Rt16)",(RsV==RtV)) 125 STD_CMPJUMP(cmpgt,"cmp.gt(Rs16,Rt16)",(RsV>RtV)) 126 STD_CMPJUMP(cmpgtu,"cmp.gtu(Rs16,Rt16)",(fCAST4u(RsV)>RtV)) 162 STD_CMPJUMPNEWRS(cmpeq_t, "cmp.eq(Ns8.new,Rt32)", (fNEWREG(NsN)==RtV)) 163 STD_CMPJUMPNEWRS(cmpgt_t, "cmp.gt(Ns8.new,Rt32)", (fNEWREG(NsN)>RtV)) 164 STD_CMPJUMPNEWRS(cmpgtu_t,"cmp.gtu(Ns8.new,Rt32)",(fCAST4u(fNEWREG(NsN))>fCAST4u(RtV))) 165 STD_CMPJUMPNEWRS(cmplt_t, "cmp.gt(Rt32,Ns8.new)", (RtV>fNEWREG(NsN))) 166 STD_CMPJUMPNEWRS(cmpltu_t,"cmp.gtu(Rt32,Ns8.new)",(fCAST4u(RtV)>fCAST4u(fNEWREG(NsN)))) 167 STD_CMPJUMPNEWRS(cmpeq_f, "!cmp.eq(Ns8.new,Rt32)", (fNEWREG(NsN)!=RtV)) 168 STD_CMPJUMPNEWRS(cmpgt_f, "!cmp.gt(Ns8.new,Rt32)", !(fNEWREG(NsN)>RtV)) [all …]
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H A D | system.idef | 54 (RtV&0xff), /*height*/ 55 ((RtV>>8)&0xff), /*width*/ 56 ((RtV>>16)&0xffff), /*stride*/
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H A D | subinsns.idef | 137 …REGWRSIZE_4B,A_MEMSIZE_4B,A_STORE,A_SUBINSN), "store word", {fEA_RI(RsV,uiV); fSTORE(1,4,EA,RtV);}) 138 …(A_MEMSIZE_1B,A_STORE,A_SUBINSN), "store byte", {fEA_RI(RsV,uiV); fSTORE(1,1,EA,fGETBYTE(0,RtV));}) 139 …(A_MEMSIZE_2B,A_STORE,A_SUBINSN), "store half", {fEA_RI(RsV,uiV); fSTORE(1,2,EA,fGETHALF(0,RtV));}) 141 …ZE_4B,A_MEMSIZE_4B,A_STORE,A_SUBINSN), "store word", {fEA_RI(fREAD_SP(),uiV); fSTORE(1,4,EA,RtV);})
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/openbmc/qemu/target/hexagon/imported/mmvec/ |
H A D | ext.idef | 213 fHIDE(int )shamt = RtV & SHAMTMASK; \ 236 EXTINSN(V6_##TAG##_ai, SYNTAXA "(Rt32+#s4)" NT SYNTAXB,ATTRIB,DESCR,{ fEA_RI(RtV,VEC_SCALE(siV… 242 …(Rt32+#s4)" NT SYNTAXB, ATTRIB,DESCR, { if (fLSBOLD(SYNTAXP##V)) { fEA_RI(RtV,siV*fVECSIZE()); BE… 247 …Rt32+#s4)" NT SYNTAXB,ATTRIB,DESCR, { if (fLSBOLDNOT(SYNTAXP##V)) { fEA_RI(RtV,siV*fVECSIZE()); BE… 347 unsigned shift = RtV & (fVBYTES()-1); 352 unsigned shift = fVBYTES() - (RtV & (fVBYTES()-1)); 370 VdV.ub[k] = VuV.ub[(k+RtV)&(fVBYTES()-1)]; 487 VdV.h[i] = fMPY8US( fGETUBYTE(0, VuV.uh[i]), fGETBYTE((2*i) % 4, RtV)); 488 VdV.h[i] += fMPY8US( fGETUBYTE(1, VuV.uh[i]), fGETBYTE((2*i+1)%4, RtV))) 492 VxV.h[i] += fMPY8US( fGETUBYTE(0, VuV.uh[i]), fGETBYTE((2*i) % 4, RtV)); [all …]
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/openbmc/qemu/target/hexagon/idef-parser/ |
H A D | README.rst | 18 A2_add(RdV, in RsV, in RtV) { 19 { RdV=RsV+RtV;} 28 TCGv_i32 RsV, TCGv_i32 RtV) 29 /* { RdV=RsV+RtV;} */ 32 tcg_gen_add_i32(tmp_0, RsV, RtV); 66 { RdV=RsV+RtV;} 77 will be declared, ``RsV`` and ``RtV`` will also be read and ``RdV`` will be 91 tcg_gen_add_i32(tmp_0, RsV, RtV); 514 TCGv_i32 RsV, TCGv_i32 RtV) 515 /* RdV=RsV+RtV;} */ [all …]
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