/openbmc/qemu/target/hexagon/ |
H A D | arch.c | 244 float32 RsV, RtV, RdV; in arch_sf_recip_common() local 246 RsV = *Rs; in arch_sf_recip_common() 248 if (float32_is_any_nan(RsV) && float32_is_any_nan(RtV)) { in arch_sf_recip_common() 249 if (extract32(RsV & RtV, 22, 1) == 0) { in arch_sf_recip_common() 252 RdV = RsV = RtV = float32_nan; in arch_sf_recip_common() 253 } else if (float32_is_any_nan(RsV)) { in arch_sf_recip_common() 254 if (extract32(RsV, 22, 1) == 0) { in arch_sf_recip_common() 257 RdV = RsV = RtV = float32_nan; in arch_sf_recip_common() 263 RdV = RsV = RtV = float32_nan; in arch_sf_recip_common() 264 } else if (float32_is_infinity(RsV) && float32_is_infinity(RtV)) { in arch_sf_recip_common() [all …]
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H A D | gen_tcg.h | 171 fGEN_TCG_loadbXw2(fEA_RI(RsV, siV), false) 175 fGEN_TCG_loadbXw2(fEA_RI(RsV, siV), true) 223 fGEN_TCG_loadbXw4(fEA_RI(RsV, siV), false) 227 fGEN_TCG_loadbXw4(fEA_RI(RsV, siV), true) 274 fGEN_TCG_loadalignh(fEA_RI(RsV, siV)) 301 fGEN_TCG_loadalignb(fEA_RI(RsV, siV)) 494 do { RsV = RsV; } while (0) 496 do { RsV = RsV; } while (0) 498 do { RsV = RsV; } while (0) 500 do { RsV = RsV; } while (0) [all …]
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H A D | op_helper.c | 315 uint64_t HELPER(sfrecipa)(CPUHexagonState *env, float32 RsV, float32 RtV) in HELPER() 325 if (arch_sf_recip_common(&RsV, &RtV, &RdV, &adjust, &env->fp_status)) { in HELPER() 336 uint64_t HELPER(sfinvsqrta)(CPUHexagonState *env, float32 RsV) in HELPER() 346 if (arch_sf_invsqrt_common(&RsV, &RdV, &adjust, &env->fp_status)) { in HELPER() 348 idx = (RsV >> 17) & 0x7f; in HELPER() 350 exp = SF_BIAS - ((float32_getexp(RsV) - SF_BIAS) >> 1) - 1; in HELPER() 351 RdV = build_float32(extract32(RsV, 31, 1), exp, mant); in HELPER() 591 float64 HELPER(conv_sf2df)(CPUHexagonState *env, float32 RsV) in HELPER() 595 out_f64 = float32_to_float64(RsV, &env->fp_status); in HELPER() 609 float32 HELPER(conv_uw2sf)(CPUHexagonState *env, int32_t RsV) in HELPER() [all …]
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H A D | genptr.c | 546 static inline void gen_loop0r(DisasContext *ctx, TCGv RsV, int riV) in gen_loop0r() argument 550 gen_log_reg_write(ctx, HEX_REG_LC0, RsV); in gen_loop0r() 560 static inline void gen_loop1r(DisasContext *ctx, TCGv RsV, int riV) in gen_loop1r() argument 564 gen_log_reg_write(ctx, HEX_REG_LC1, RsV); in gen_loop1r() 573 static void gen_ploopNsr(DisasContext *ctx, int N, TCGv RsV, int riV) in gen_ploopNsr() argument 577 gen_log_reg_write(ctx, HEX_REG_LC0, RsV); in gen_ploopNsr() 1044 static void gen_asr_r_r_sat(DisasContext *ctx, TCGv RdV, TCGv RsV, TCGv RtV) in gen_asr_r_r_sat() argument 1055 gen_shl_sat(ctx, RdV, RsV, shift_amt); in gen_asr_r_r_sat() 1060 gen_sar(RdV, RsV, shift_amt); in gen_asr_r_r_sat() 1066 static void gen_asl_r_r_sat(DisasContext *ctx, TCGv RdV, TCGv RsV, TCGv RtV) in gen_asl_r_r_sat() argument [all …]
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H A D | README | 63 Instruction semantics "{ RdV=RsV+RtV;}" 67 RsV, RtV are source registers 85 TCGv RsV = hex_gpr[insn->regno[1]]; 87 gen_helper_A2_add(RdV, tcg_env, RsV, RtV); 92 int32_t HELPER(A2_add)(CPUHexagonState *env, int32_t RsV, int32_t RtV) 96 { RdV=RsV+RtV;} 115 tcg_gen_add_tl(RdV, RsV, RtV) 123 Instruction semantics "{ fEA_REG(RsV); fLOAD_LOCKED(1,4,u,EA,RdV) }"
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/openbmc/qemu/target/hexagon/imported/ |
H A D | float.idef | 27 { RdV=fUNFLOAT(fFLOAT(RsV)+fFLOAT(RtV));}) 31 { RdV=fUNFLOAT(fFLOAT(RsV)-fFLOAT(RtV));}) 35 { RdV=fUNFLOAT(fSFMPY(fFLOAT(RsV),fFLOAT(RtV)));}) 39 { RxV=fUNFLOAT(fFMAF(fFLOAT(RsV),fFLOAT(RtV),fFLOAT(RxV)));}) 45 fCHECKSFNAN3(RxV,RxV,RsV,RtV); 46 tmp=fUNFLOAT(fFMAFX(fFLOAT(RsV),fFLOAT(RtV),fFLOAT(RxV),PuV)); 47 if (!((fFLOAT(RxV) == 0.0) && fISZEROPROD(fFLOAT(RsV),fFLOAT(RtV)))) RxV = tmp; 52 { RxV=fUNFLOAT(fFMAF(-fFLOAT(RsV),fFLOAT(RtV),fFLOAT(RxV))); }) 58 (fISINFPROD(fFLOAT(RsV),fFLOAT(RtV))) && 59 (fGETBIT(31,RsV ^ RxV ^ RtV) != 0)); [all …]
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H A D | branch.idef | 35 {fJUMPR(RsN,RsV,COF_TYPE_JUMPR);}) 38 {fJUMPR(RsN,RsV,COF_TYPE_JUMPR);}) 50 fJUMPR(RsN,RsV,COF_TYPE_JUMPR);) 62 fJUMPR(RsN,RsV,COF_TYPE_JUMPR);) 67 {fHINTJR(RsV);}) 74 {fBRANCH_SPECULATE_STALL((RsV!=0), , SPECULATE_NOT_TAKEN,12,0) if (RsV != 0) { fBRANCH(fREAD_PC()+r… 77 {fBRANCH_SPECULATE_STALL((RsV==0), , SPECULATE_NOT_TAKEN,12,0) if (RsV == 0) {fBRANCH(fREAD_PC()+ri… 80 {fBRANCH_SPECULATE_STALL((RsV!=0), , SPECULATE_TAKEN,12,0) if (RsV != 0) { fBRANCH(fREAD_PC()+riV,C… 83 {fBRANCH_SPECULATE_STALL((RsV==0), , SPECULATE_TAKEN,12,0) if (RsV == 0) {fBRANCH(fREAD_PC()+riV,CO… 86 {fBRANCH_SPECULATE_STALL((RsV>=0), , SPECULATE_NOT_TAKEN,12,0) if (RsV>=0) { fBRANCH(fREAD_PC()+riV… [all …]
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H A D | alu.idef | 29 { RdV=RsV+RtV;}) 33 { RdV=RtV-RsV;}) 41 COND_ALU(A2_padd,"Rd32=add(Rs32,Rt32)","Conditionally Add 32-bit registers",RdV=RsV+RtV) 42 COND_ALU(A2_psub,"Rd32=sub(Rt32,Rs32)","Conditionally Subtract 32-bit registers",RdV=RtV-RsV) 43 …A2_paddi,"Rd32=add(Rs32,#s8)","Conditionally Add Register and immediate",fIMMEXT(siV); RdV=RsV+siV) 44 COND_ALU(A2_pxor,"Rd32=xor(Rs32,Rt32)","Conditionally XOR registers",RdV=RsV^RtV) 45 COND_ALU(A2_pand,"Rd32=and(Rs32,Rt32)","Conditionally AND registers",RdV=RsV&RtV) 46 COND_ALU(A2_por,"Rd32=or(Rs32,Rt32)","Conditionally OR registers",RdV=RsV|RtV) 48 COND_ALU(A4_psxtb,"Rd32=sxtb(Rs32)","Conditionally sign-extend byte", RdV=fSXTN(8,32,RsV)) 49 COND_ALU(A4_pzxtb,"Rd32=zxtb(Rs32)","Conditionally zero-extend byte", RdV=fZXTN(8,32,RsV)) [all …]
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H A D | compare.idef | 30 {PdV=f8BITSOF(RsV==RtV);}) 34 {PdV=f8BITSOF(RsV>RtV);}) 38 {PdV=f8BITSOF(fCAST4u(RsV)>fCAST4u(RtV));}) 62 {fIMMEXT(siV); RdV=(RsV==siV); }) 66 {fIMMEXT(siV); RdV=(RsV!=siV); }) 71 {RdV=(RsV==RtV); }) 75 {RdV=(RsV!=RtV); }) 86 {PdV=f8BITSOF((RsV&RtV)==RtV);}) 90 {PdV=f8BITSOF((RsV&RtV)==0);}) 95 {PdV=f8BITSOF((RsV&RtV)!=RtV);}) [all …]
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H A D | mpy.idef | 24 …H32)"OSEM, ATR,"",{DST=SATSEM(RNDSEM(ACCSEM SEM( fGETHALF(1,RsV),fGETHALF(1,RtV))))… 25 …H32):<<1"OSEM, ATR,"",{DST=SATSEM(RNDSEM(ACCSEM fSCALE(1,SEM(fGETHALF(1,RsV),fGETHALF(1,RtV))))… 26 …L32)"OSEM, ATR,"",{DST=SATSEM(RNDSEM(ACCSEM SEM( fGETHALF(1,RsV),fGETHALF(0,RtV))))… 27 …L32):<<1"OSEM, ATR,"",{DST=SATSEM(RNDSEM(ACCSEM fSCALE(1,SEM(fGETHALF(1,RsV),fGETHALF(0,RtV))))… 28 …H32)"OSEM, ATR,"",{DST=SATSEM(RNDSEM(ACCSEM SEM( fGETHALF(0,RsV),fGETHALF(1,RtV))))… 29 …H32):<<1"OSEM, ATR,"",{DST=SATSEM(RNDSEM(ACCSEM fSCALE(1,SEM(fGETHALF(0,RsV),fGETHALF(1,RtV))))… 30 …L32)"OSEM, ATR,"",{DST=SATSEM(RNDSEM(ACCSEM SEM( fGETHALF(0,RsV),fGETHALF(0,RtV))))… 31 …L32):<<1"OSEM, ATR,"",{DST=SATSEM(RNDSEM(ACCSEM fSCALE(1,SEM(fGETHALF(0,RsV),fGETHALF(0,RtV))))… 54 …32)"OSEM, ATR,"",{DST=SATSEM(RNDSEM(ACCSEM SEM( fGETUHALF(1,RsV),fGETUHALF(1,RtV)))… 55 …32):<<1"OSEM, ATR,"",{DST=SATSEM(RNDSEM(ACCSEM fSCALE(1,SEM(fGETUHALF(1,RsV),fGETUHALF(1,RtV)))… [all …]
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H A D | subinsns.idef | 31 Q6INSN(SA1_tfr, "Rd16=Rs16", ATTRIBS(A_SUBINSN),"Tfr", { RdV=RsV;}) 40 Q6INSN(SA1_inc, "Rd16=add(Rs16,#1)", ATTRIBS(A_SUBINSN),"Inc", { RdV=RsV+1;}) 41 Q6INSN(SA1_dec, "Rd16=add(Rs16,#-1)", ATTRIBS(A_SUBINSN),"Dec", { RdV=RsV-1;}) 42 …A1_addrx, "Rx16=add(Rx16,Rs16)", ATTRIBS(A_SUBINSN,A_COMMUTES),"Add", { RxV=RxV+RsV; }) 43 …N(SA1_zxtb, "Rd16=and(Rs16,#255)", ATTRIBS(A_SUBINSN),"Zxtb", { RdV= fZXTN(8,32,RsV);}) 44 Q6INSN(SA1_and1, "Rd16=and(Rs16,#1)", ATTRIBS(A_SUBINSN),"And #1", { RdV= RsV&1;}) 45 …N(SA1_sxtb, "Rd16=sxtb(Rs16)", ATTRIBS(A_SUBINSN),"Sxtb", { RdV= fSXTN(8,32,RsV);}) 46 …(SA1_zxth, "Rd16=zxth(Rs16)", ATTRIBS(A_SUBINSN),"Zxth", { RdV= fZXTN(16,32,RsV);}) 47 …(SA1_sxth, "Rd16=sxth(Rs16)", ATTRIBS(A_SUBINSN),"Sxth", { RdV= fSXTN(16,32,RsV);}) 48 …ine(#0,Rs16)", ATTRIBS(A_SUBINSN,A_ROPS_2),"Combines", { fSETWORD(0,RddV,RsV); fSETWORD(1,RddV,0… [all …]
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H A D | system.idef | 36 …)",ATTRIBS(A_ICOP,A_ICFLUSHOP),"Instruction Cache Invalidate Address",{fEA_REG(RsV); fICINVA(EA);}) 43 …)",ATTRIBS(A_RESTRICT_PREFERSLOT0,A_DCFETCH),"Data Cache Prefetch",{fEA_RI(RsV,uiV); fDCFETCH(EA);… 46 …,A_RESTRICT_SLOT0ONLY,A_DCZEROA),"Zero an aligned 32-byte cacheline",{fEA_REG(RsV); fDCZEROA(EA);}) 47 …TTRIBS(A_RESTRICT_SLOT0ONLY,A_DCFLUSHOP),"Data Cache Clean Address",{fEA_REG(RsV); fDCCLEANA(EA);}) 48 …_SLOT0ONLY,A_DCFLUSHOP),"Data Cache Clean and Invalidate Address",{fEA_REG(RsV); fDCCLEANINVA(EA);… 49 …A_RESTRICT_SLOT0ONLY,A_DCFLUSHOP),"Data Cache Invalidate Address",{fEA_REG(RsV); fDCCLEANINVA(EA);… 53 { fL2FETCH(RsV, 63 { fL2FETCH(RsV,
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H A D | shift.idef | 158 { RdV = fASHIFTR(((fASHIFTR(RsV,uiV,4_8))+1),1,8_8); }) 180 { RdV = RtV + fASHIFTL(RsV,uiV,4_4); }) 221 fSETHALF(i,RddV, fGETHALF(0,RsV)); 231 fSETBYTE(i,RdV, fGETBYTE(0,RsV)); 240 fSETBYTE(i,RddV, fGETBYTE(0,RsV)); 258 RxV |= ((RsV & ((fCONSTLL(1)<<width)-1)) << offset); 267 fHIDE(int) field = fEXTRACTU_BIDIR(RsV,width,offset); 276 fHIDE(int) field = fEXTRACTU_BIDIR(RsV,width,offset); 285 fHIDE(int) field = fEXTRACTU_BIDIR(RsV,width,offset); 294 fHIDE(int) field = fEXTRACTU_BIDIR(RsV,width,offset); [all …]
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H A D | ldst.idef | 24 Q6INSN(L2_##TAG##_io, OPER"(Rs32+#s11:"SHFT")", ATTRIB,DESCR,{fIMMEXT(siV); fEA_RI(RsV,si… 105 Q6INSN(S2_##TAG##_io, OPER"(Rs32+#s11:"SHFT")="DEST, ATTRIB,DESCR,{fIMMEXT(siV); fEA_RI(RsV,si… 136 { fEA_REG(RsV); fLOAD(1,4,u,EA,RdV); }) 138 { fEA_REG(RsV); fLOAD(1,8,u,EA,RddV); }) 140 …AD,A_RESTRICT_NOPACKET,A_RESTRICT_SLOT0ONLY), "Release lock", {fEA_REG(RsV); fSTORE(1,0,EA,RsV); }) 141 …AD,A_RESTRICT_NOPACKET,A_RESTRICT_SLOT0ONLY), "Release lock", {fEA_REG(RsV); fSTORE(1,0,EA,RsV); }) 143 …A_MEMSIZE_4B,A_STORE,A_RESTRICT_SLOT0ONLY),"Store Release Word", { fEA_REG(RsV); fSTORE(1,4,EA,RtV… 144 …8B,A_STORE,A_RESTRICT_SLOT0ONLY),"Store Release Double integer", { fEA_REG(RsV); fSTORE(1,8,EA,Rtt… 146 …A_MEMSIZE_4B,A_STORE,A_RESTRICT_SLOT0ONLY),"Store Release Word", { fEA_REG(RsV); fSTORE(1,4,EA,RtV… 147 …8B,A_STORE,A_RESTRICT_SLOT0ONLY),"Store Release Double integer", { fEA_REG(RsV); fSTORE(1,8,EA,Rtt… [all …]
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/openbmc/qemu/target/hexagon/idef-parser/ |
H A D | README.rst | 18 A2_add(RdV, in RsV, in RtV) { 19 { RdV=RsV+RtV;} 28 TCGv_i32 RsV, TCGv_i32 RtV) 29 /* { RdV=RsV+RtV;} */ 32 tcg_gen_add_i32(tmp_0, RsV, RtV); 66 { RdV=RsV+RtV;} 77 will be declared, ``RsV`` and ``RtV`` will also be read and ``RdV`` will be 91 tcg_gen_add_i32(tmp_0, RsV, RtV); 126 """{fJUMPR(RsN,RsV,COF_TYPE_JUMPR);}""" \ 134 J2_jumpr(in RsV) { [all …]
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H A D | idef-parser.lex | 472 "fHINTJR(RsV)" { /* Emit no token */ }
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/openbmc/qemu/target/hexagon/imported/mmvec/ |
H A D | ext.idef | 2036 fHIDE(warn("RdN=%d VuN=%d RsN=%d RsV=0x%08x widx=%d",RdN,VuN,RsN,RsV,((RsV & (fVBYTES()-1)) >> 2));) 2037 RdV = VuV.uw[ (RsV & (fVBYTES()-1)) >> 2];
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