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Searched refs:R_STATUS (Results 1 – 15 of 15) sorted by relevance

/openbmc/qemu/hw/char/
H A Dxilinx_uartlite.c40 #define R_STATUS 2 macro
76 s->regs[R_STATUS] |= STATUS_IE; in uart_update_irq()
78 irq = (s->regs[R_STATUS] & STATUS_IE) && (s->regs[R_CTRL] & CONTROL_IE); in uart_update_irq()
86 r = s->regs[R_STATUS]; in uart_update_status()
91 s->regs[R_STATUS] = r; in uart_update_status()
136 case R_STATUS: in uart_write()
156 s->regs[R_STATUS] |= STATUS_IE; in uart_write()
H A Descc.c152 #define R_STATUS 0 macro
265 (s->rregs[R_STATUS] & STATUS_BRK)))) { in escc_update_irq_chn()
314 s->rregs[R_STATUS] &= STATUS_DCD | STATUS_SYNC | STATUS_CTS | STATUS_BRK; in escc_soft_reset_chn()
315 s->rregs[R_STATUS] |= STATUS_TXEMPTY | STATUS_TXUNDRN; in escc_soft_reset_chn()
317 s->rregs[R_STATUS] |= STATUS_DCD | STATUS_SYNC | STATUS_CTS; in escc_soft_reset_chn()
370 cs->rregs[R_STATUS] |= STATUS_TXEMPTY; in escc_reset()
583 s->rregs[R_STATUS] |= STATUS_SYNC; in escc_mem_write()
669 s->rregs[R_STATUS] |= STATUS_TXEMPTY; /* Tx buffer empty */ in escc_mem_write()
697 s->rregs[R_STATUS] &= ~STATUS_RXAV; in escc_mem_read()
729 || ((s->rregs[R_STATUS] & STATUS_RXAV) == STATUS_RXAV)) { in serial_can_receive()
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H A Dibex_uart.c286 case R_STATUS: in ibex_uart_read()
401 case R_STATUS: in ibex_uart_write()
/openbmc/qemu/hw/misc/
H A Daspeed_sbc.c20 #define R_STATUS (0x014 / 4) macro
75 case R_STATUS: in aspeed_sbc_write()
105 s->regs[R_STATUS] = OTP_IDLE | OTP_MEM_IDLE; in aspeed_sbc_reset()
108 s->regs[R_STATUS] &= ABR_EN; in aspeed_sbc_reset()
112 s->regs[R_STATUS] &= SECURE_BOOT_EN; in aspeed_sbc_reset()
H A Daspeed_hace.c24 #define R_STATUS (0x1c / 4) macro
299 s->regs[R_STATUS] |= HASH_IRQ; in do_hash_operation()
334 case R_STATUS: in aspeed_hace_write()
H A Dxlnx-versal-trng.c314 uint32_t st = s->regs[R_STATUS]; in trng_core_int_update()
349 s->regs[R_STATUS] &= ~clr_mask; in trng_int_ctrl_postw()
392 s->regs[R_STATUS] = 0; in trng_soft_reset()
/openbmc/linux/drivers/net/ethernet/arc/
H A Demac_mdio.c29 unsigned int status = arc_reg_get(priv, R_STATUS); in arc_mdio_complete_wait()
35 arc_reg_set(priv, R_STATUS, status); in arc_mdio_complete_wait()
H A Demac.h55 R_STATUS, enumerator
H A Demac_main.c361 status = arc_reg_get(priv, R_STATUS); in arc_emac_intr()
365 arc_reg_set(priv, R_STATUS, status); in arc_emac_intr()
743 arc_reg_set(priv, R_STATUS, TXPL_MASK); in arc_emac_tx()
/openbmc/qemu/hw/nvram/
H A Dxlnx-versal-efuse-ctrl.c262 uint32_t val = s->regs[R_STATUS]; in efuse_status_tbits_sync()
268 s->regs[R_STATUS] = val; in efuse_status_tbits_sync()
308 r = s->regs[R_STATUS] | done_mask | pass_mask; in efuse_key_crc_check()
315 s->regs[R_STATUS] = r ^ pass_mask; in efuse_key_crc_check()
H A Dxlnx-zynqmp-efuse.c275 uint32_t val = s->regs[R_STATUS]; in update_tbit_status()
281 s->regs[R_STATUS] = val; in update_tbit_status()
/openbmc/linux/drivers/isdn/hardware/mISDN/
H A Dhfc_multi_8xx.h62 writeb(R_STATUS, hc->xhfc_memaddr); in HFC_wait_embsd()
H A Dhfc_multi.h411 #define R_STATUS 0x1C macro
H A Dhfcmulti.c308 while (readb(hc->pci_membase + R_STATUS) & V_BUSY) in HFC_wait_pcimem()
351 outb(R_STATUS, hc->pci_iobase + 4); in HFC_wait_regio()
2688 status = HFC_inb_nodebug(hc, R_STATUS); in hfcmulti_interrupt()
/openbmc/qemu/hw/dma/
H A Dxlnx_csu_dma.c254 s->regs[R_STATUS] &= ~R_STATUS_BUSY_MASK; in xlnx_csu_dma_done()
367 s->regs[R_STATUS] |= R_STATUS_BUSY_MASK; in size_post_write()