Searched refs:R_INT_STATUS (Results 1 – 2 of 2) sorted by relevance
189 qemu_set_irq(s->irq, !!(s->regs[R_INT_STATUS] & ~s->regs[R_INT_MASK])); in xlnx_csu_dma_update_irq()216 s->regs[R_INT_STATUS] |= R_INT_STATUS_AXI_BRESP_ERR_MASK; in xlnx_csu_dma_read()246 s->regs[R_INT_STATUS] |= R_INT_STATUS_AXI_BRESP_ERR_MASK; in xlnx_csu_dma_write()255 s->regs[R_INT_STATUS] |= R_INT_STATUS_DONE_MASK; in xlnx_csu_dma_done()258 s->regs[R_INT_STATUS] |= R_INT_STATUS_MEM_DONE_MASK; in xlnx_csu_dma_done()414 if ((val & s->regs[R_INT_STATUS] & R_INT_STATUS_DONE_MASK)) { in int_status_pre_write()418 return s->regs[R_INT_STATUS] & ~val; in int_status_pre_write()582 s->regs[R_INT_STATUS] |= R_INT_STATUS_TIMEOUT_STRM_MASK; in xlnx_csu_dma_src_timeout_hit()603 s->regs[R_INT_STATUS] |= R_INT_STATUS_FIFO_OVERFLOW_MASK; in xlnx_csu_dma_stream_push()
60 #define R_INT_STATUS (0x04 / 4) macro595 case R_INT_STATUS: in aspeed_2700_sdmc_write()