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Searched refs:RREG32_PCIE (Results 1 – 25 of 38) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dnbio_v6_1.c169 def = data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v6_1_update_medium_grain_clock_gating()
197 def = data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v6_1_update_medium_grain_light_sleep()
218 data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v6_1_get_clockgating_state()
223 data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v6_1_get_clockgating_state()
267 def = data = RREG32_PCIE(smnPCIE_CONFIG_CNTL); in nbio_v6_1_init_registers()
274 def = data = RREG32_PCIE(smnPCIE_CI_CNTL); in nbio_v6_1_init_registers()
292 def = data = RREG32_PCIE(smnRCC_BIF_STRAP2); in nbio_v6_1_program_ltr()
297 def = data = RREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL); in nbio_v6_1_program_ltr()
302 def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2); in nbio_v6_1_program_ltr()
314 def = data = RREG32_PCIE(smnPCIE_LC_CNTL); in nbio_v6_1_program_aspm()
[all …]
H A Dnbio_v7_4.c260 def = data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v7_4_update_medium_grain_light_sleep()
281 data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v7_4_get_clockgating_state()
286 data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v7_4_get_clockgating_state()
595 global_sts = RREG32_PCIE(smnRAS_GLOBAL_STATUS_LO_ALDE); in nbio_v7_4_query_ras_error_count()
597 global_sts = RREG32_PCIE(smnRAS_GLOBAL_STATUS_LO); in nbio_v7_4_query_ras_error_count()
605 parity_sts = RREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2_ALDE); in nbio_v7_4_query_ras_error_count()
607 parity_sts = RREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2); in nbio_v7_4_query_ras_error_count()
615 central_sts = RREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS); in nbio_v7_4_query_ras_error_count()
636 int_eoi = RREG32_PCIE(smnIOHC_INTERRUPT_EOI); in nbio_v7_4_query_ras_error_count()
683 def = data = RREG32_PCIE(smnRCC_BIF_STRAP2); in nbio_v7_4_program_ltr()
[all …]
H A Dnbio_v2_3.c237 def = data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v2_3_update_medium_grain_clock_gating()
266 def = data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v2_3_update_medium_grain_light_sleep()
287 data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v2_3_get_clockgating_state()
292 data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v2_3_get_clockgating_state()
336 def = data = RREG32_PCIE(smnPCIE_CONFIG_CNTL); in nbio_v2_3_init_registers()
357 def = data = RREG32_PCIE(smnPCIE_LC_CNTL); in nbio_v2_3_enable_aspm()
396 def = data = RREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL); in nbio_v2_3_program_ltr()
401 def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2); in nbio_v2_3_program_ltr()
413 def = data = RREG32_PCIE(smnPCIE_LC_CNTL); in nbio_v2_3_program_aspm()
420 def = data = RREG32_PCIE(smnPCIE_LC_CNTL7); in nbio_v2_3_program_aspm()
[all …]
H A Dumc_v6_1.c50 rsmu_umc_val = RREG32_PCIE(rsmu_umc_addr * 4); in umc_v6_1_enable_umc_index_mode()
65 rsmu_umc_val = RREG32_PCIE(rsmu_umc_addr * 4); in umc_v6_1_disable_umc_index_mode()
80 rsmu_umc_val = RREG32_PCIE(rsmu_umc_addr * 4); in umc_v6_1_get_umc_index_mode_state()
119 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + in umc_v6_1_clear_error_count_per_channel()
132 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + in umc_v6_1_clear_error_count_per_channel()
197 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); in umc_v6_1_query_correctable_error_count()
202 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v6_1_query_correctable_error_count()
212 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v6_1_query_correctable_error_count()
412 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); in umc_v6_1_err_cnt_init_per_channel()
H A Dcik.c1550 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); in cik_pcie_gen3_enable()
1580 tmp = RREG32_PCIE(ixPCIE_LC_STATUS1); in cik_pcie_gen3_enable()
1587 tmp = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL); in cik_pcie_gen3_enable()
1620 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); in cik_pcie_gen3_enable()
1624 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); in cik_pcie_gen3_enable()
1664 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); in cik_pcie_gen3_enable()
1688 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); in cik_pcie_gen3_enable()
1693 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); in cik_pcie_gen3_enable()
1716 orig = data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL); in cik_program_aspm()
1723 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL3); in cik_program_aspm()
[all …]
H A Dvi.c1110 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL); in vi_enable_aspm()
1134 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL); in vi_program_aspm()
1141 orig = data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL); in vi_program_aspm()
1148 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL3); in vi_program_aspm()
1153 orig = data = RREG32_PCIE(ixPCIE_P_CNTL); in vi_program_aspm()
1158 data = RREG32_PCIE(ixPCIE_LC_L1_PM_SUBSTATE); in vi_program_aspm()
1173 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL6); in vi_program_aspm()
1178 orig = data = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL); in vi_program_aspm()
1220 orig = data = RREG32_PCIE(ixCPM_CONTROL); in vi_program_aspm()
1226 orig = data = RREG32_PCIE(ixPCIE_CONFIG_CNTL); in vi_program_aspm()
[all …]
H A Dumc_v8_7.c192 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + in umc_v8_7_clear_error_count_per_channel()
205 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + in umc_v8_7_clear_error_count_per_channel()
252 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); in umc_v8_7_query_correctable_error_count()
257 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v8_7_query_correctable_error_count()
267 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v8_7_query_correctable_error_count()
402 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); in umc_v8_7_err_cnt_init_per_channel()
H A Dnbio_v7_0.c154 def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK); in nbio_v7_0_update_medium_grain_clock_gating()
192 def = data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v7_0_update_medium_grain_light_sleep()
213 data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v7_0_get_clockgating_state()
218 data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v7_0_get_clockgating_state()
H A Dumc_v6_7.c281 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); in umc_v6_7_query_correctable_error_count()
286 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v6_7_query_correctable_error_count()
296 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v6_7_query_correctable_error_count()
378 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + in umc_v6_7_reset_error_count_per_channel()
391 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + in umc_v6_7_reset_error_count_per_channel()
499 ecc_ctrl = RREG32_PCIE((ecc_ctrl_addr + in umc_v6_7_query_ras_poison_mode_per_channel()
H A Dnbio_v7_9.c474 val = RREG32_PCIE(smnPCIEP_NAK_COUNTER); in nbio_v7_9_get_pcie_replay_count()
529 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | in nbio_v7_9_get_pcie_usage()
530 ((uint64_t)RREG32_PCIE(smnPCIE_PERF_COUNT0_UPVAL_TXCLK3) << 32); in nbio_v7_9_get_pcie_usage()
531 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK7) | in nbio_v7_9_get_pcie_usage()
532 ((uint64_t)RREG32_PCIE(smnPCIE_PERF_COUNT0_UPVAL_TXCLK7) << 32); in nbio_v7_9_get_pcie_usage()
H A Damdgpu_xgmi.c1003 data = RREG32_PCIE(xgmi_pcs_err_status_reg_arct[i]); in amdgpu_xgmi_query_ras_error_count()
1010 data = RREG32_PCIE(wafl_pcs_err_status_reg_arct[i]); in amdgpu_xgmi_query_ras_error_count()
1019 data = RREG32_PCIE(xgmi_pcs_err_status_reg_vg20[i]); in amdgpu_xgmi_query_ras_error_count()
1026 data = RREG32_PCIE(wafl_pcs_err_status_reg_vg20[i]); in amdgpu_xgmi_query_ras_error_count()
1035 data = RREG32_PCIE(xgmi3x16_pcs_err_status_reg_aldebaran[i]); in amdgpu_xgmi_query_ras_error_count()
1037 RREG32_PCIE(xgmi3x16_pcs_err_noncorrectable_mask_reg_aldebaran[i]); in amdgpu_xgmi_query_ras_error_count()
1044 data = RREG32_PCIE(walf_pcs_err_status_reg_aldebaran[i]); in amdgpu_xgmi_query_ras_error_count()
1046 RREG32_PCIE(walf_pcs_err_noncorrectable_mask_reg_aldebaran[i]); in amdgpu_xgmi_query_ras_error_count()
H A Dsoc15.c765 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK); in soc15_get_pcie_usage()
770 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); in soc15_get_pcie_usage()
771 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); in soc15_get_pcie_usage()
814 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3); in vega20_get_pcie_usage()
819 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32); in vega20_get_pcie_usage()
820 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32); in vega20_get_pcie_usage()
855 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK); in soc15_get_pcie_replay_count()
856 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED); in soc15_get_pcie_replay_count()
H A Dsi.c1617 tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK); in si_get_pcie_usage()
1622 *count0 = RREG32_PCIE(ixPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); in si_get_pcie_usage()
1623 *count1 = RREG32_PCIE(ixPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); in si_get_pcie_usage()
1631 nak_r = RREG32_PCIE(ixPCIE_RX_NUM_NAK); in si_get_pcie_replay_count()
1632 nak_g = RREG32_PCIE(ixPCIE_RX_NUM_NAK_GENERATED); in si_get_pcie_replay_count()
2282 tmp = RREG32_PCIE(PCIE_LC_STATUS1); in si_pcie_gen3_enable()
2456 orig = data = RREG32_PCIE(PCIE_P_CNTL); in si_program_aspm()
2619 orig = data = RREG32_PCIE(PCIE_CNTL2); in si_program_aspm()
2627 data = RREG32_PCIE(PCIE_LC_STATUS1); in si_program_aspm()
H A Dpsp_v3_1.c302 reg = RREG32_PCIE(smnMP1_FIRMWARE_FLAGS | 0x03b00000); in psp_v3_1_smu_reload_quirk()
H A Dumc_v8_10.c308 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); in umc_v8_10_err_cnt_init_per_channel()
H A Damdgpu_cgs.c64 return RREG32_PCIE(index); in amdgpu_cgs_read_ind_register()
H A Dgmc_v7_0.c858 orig = data = RREG32_PCIE(ixPCIE_CNTL2); in gmc_v7_0_enable_bif_mgls()
/openbmc/linux/drivers/gpu/drm/radeon/
H A Dr300.c93 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_tlb_flush()
95 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_tlb_flush()
178 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_enable()
198 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_disable()
537 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_set_pcie_lanes()
553 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_set_pcie_lanes()
555 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_set_pcie_lanes()
571 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_get_pcie_lanes()
596 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_debugfs_pcie_gart_info_show()
598 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BAS in rv370_debugfs_pcie_gart_info_show()
[all...]
H A Dsi.c5571 orig = data = RREG32_PCIE(PCIE_CNTL2); in si_enable_bif_mgls()
7141 tmp = RREG32_PCIE(PCIE_LC_STATUS1); in si_pcie_gen3_enable()
7276 orig = data = RREG32_PCIE(PCIE_P_CNTL); in si_program_aspm()
7439 orig = data = RREG32_PCIE(PCIE_CNTL2); in si_program_aspm()
7447 data = RREG32_PCIE(PCIE_LC_STATUS1); in si_program_aspm()
/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dsmu9_smumgr.c44 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu9_is_smc_ram_running()
H A Dvega20_smumgr.c54 mp1_fw_flags = RREG32_PCIE(MP1_Public | in vega20_is_smc_ram_running()
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0.c166 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v13_0_load_microcode()
240 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v13_0_check_fw_status()
244 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v13_0_check_fw_status()
2028 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & in smu_v13_0_get_current_pcie_link_width_level()
2048 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & in smu_v13_0_get_current_pcie_link_speed_level()
H A Dsmu_v13_0_6_ppt.c581 RREG32_PCIE(MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); in smu_v13_0_6_check_fw_status()
1932 return REG_GET_FIELD(RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL), in smu_v13_0_6_get_current_pcie_link_width_level()
1943 esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL); in smu_v13_0_6_get_current_pcie_link_speed()
1947 speed_level = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & in smu_v13_0_6_get_current_pcie_link_speed()
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/smu12/
H A Dsmu_v12_0.c63 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v12_0_check_fw_status()
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dsmu_v11_0.c169 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v11_0_load_microcode()
188 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v11_0_check_fw_status()
2080 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & in smu_v11_0_get_current_pcie_link_width_level()
2100 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & in smu_v11_0_get_current_pcie_link_speed_level()

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