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Searched refs:RREG32_NO_KIQ (Results 1 – 18 of 18) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmxgpu_vi.c325 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_send_ack()
330 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_send_ack()
339 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_send_ack()
347 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_set_valid()
358 reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0); in xgpu_vi_mailbox_trans_msg()
374 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_rcv_msg()
379 reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0); in xgpu_vi_mailbox_rcv_msg()
395 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_poll_ack()
405 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_poll_ack()
504 u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL); in xgpu_vi_set_mailbox_ack_irq()
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H A Dmxgpu_ai.c58 return RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_mailbox_peek_msg()
68 reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_mailbox_rcv_msg()
140 reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_mailbox_trans_msg()
182 RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_send_access_requests()
243 u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL)); in xgpu_ai_set_mailbox_ack_irq()
303 u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL)); in xgpu_ai_set_mailbox_rcv_irq()
H A Dmxgpu_nv.c57 return RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0); in xgpu_nv_mailbox_peek_msg()
66 reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0); in xgpu_nv_mailbox_rcv_msg()
191 RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW1); in xgpu_nv_send_access_requests()
202 RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW2); in xgpu_nv_send_access_requests()
262 u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL); in xgpu_nv_set_mailbox_ack_irq()
328 u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL); in xgpu_nv_set_mailbox_rcv_irq()
H A Dvega10_ih.c356 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); in vega10_ih_get_wptr()
372 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); in vega10_ih_get_wptr()
403 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); in vega10_ih_irq_rearm()
H A Dvega20_ih.c431 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); in vega20_ih_get_wptr()
447 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); in vega20_ih_get_wptr()
479 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); in vega20_ih_irq_rearm()
H A Dnavi10_ih.c427 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); in navi10_ih_get_wptr()
442 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); in navi10_ih_get_wptr()
473 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); in navi10_ih_irq_rearm()
H A Dih_v6_1.c403 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); in ih_v6_1_get_wptr()
418 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); in ih_v6_1_get_wptr()
450 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); in ih_v6_1_irq_rearm()
H A Dih_v6_0.c431 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); in ih_v6_0_get_wptr()
446 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); in ih_v6_0_get_wptr()
477 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); in ih_v6_0_irq_rearm()
H A Dhdp_v5_2.c37 RREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2); in hdp_v5_2_flush_hdp()
H A Dvi.c305 (void)RREG32_NO_KIQ(mmPCIE_INDEX); in vi_pcie_rreg()
306 r = RREG32_NO_KIQ(mmPCIE_DATA); in vi_pcie_rreg()
317 (void)RREG32_NO_KIQ(mmPCIE_INDEX); in vi_pcie_wreg()
319 (void)RREG32_NO_KIQ(mmPCIE_DATA); in vi_pcie_wreg()
330 r = RREG32_NO_KIQ(mmSMC_IND_DATA_11); in vi_smc_rreg()
H A Dgmc_v11_0.c258 inv_req = RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); in gmc_v11_0_flush_vm_hub()
264 RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); in gmc_v11_0_flush_vm_hub()
H A Damdgpu_virt.c50 return RREG32_NO_KIQ(0xc040) == 0xffffffff; in amdgpu_virt_mmio_blocked()
1109 return RREG32_NO_KIQ(offset); in amdgpu_sriov_rreg()
H A Damdgpu.h1163 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) macro
H A Dgmc_v9_0.c898 RREG32_NO_KIQ(hub->vm_inv_eng0_req + in gmc_v9_0_flush_gpu_tlb()
H A Dgfx_v9_4_3.c1329 data = RREG32_NO_KIQ(reg); in gfx_v9_4_3_update_spm_vmid()
H A Damdgpu_device.c273 *data++ = RREG32_NO_KIQ(mmMM_DATA); in amdgpu_device_mm_access()
H A Dgfx_v8_0.c5589 data = RREG32_NO_KIQ(mmRLC_SPM_VMID); in gfx_v8_0_update_spm_vmid()
H A Dgfx_v9_0.c4893 data = RREG32_NO_KIQ(reg); in gfx_v9_0_update_spm_vmid_internal()