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Searched refs:RING_HWS_PGA (Results 1 – 9 of 9) sorted by relevance

/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dintel_engine_regs.h66 #define RING_HWS_PGA(base) _MMIO((base) + 0x80) macro
H A Dintel_ring_submission.c109 hwsp = RING_HWS_PGA(engine->mmio_base); in set_hwsp()
H A Dintel_execlists_submission.c2948 RING_HWS_PGA, in enable_execlists()
2950 ENGINE_POSTING_READ(engine, RING_HWS_PGA); in enable_execlists()
/openbmc/linux/drivers/gpu/drm/i915/gt/uc/
H A Dintel_guc_ads.c373 ret |= GUC_MMIO_REG_ADD(gt, regset, RING_HWS_PGA(base), false); in guc_mmio_regset_init()
H A Dintel_guc_capture.c72 { RING_HWS_PGA(0), 0, 0, "HWS" }, \
H A Dintel_guc_submission.c4176 RING_HWS_PGA, in setup_hwsp()
/openbmc/linux/drivers/gpu/drm/i915/
H A Dintel_gvt_mmio_table.c813 MMIO_RING_D(RING_HWS_PGA); in iterate_bdw_plus_mmio()
H A Di915_gpu_error.c1315 mmio = RING_HWS_PGA(engine->mmio_base); in engine_record_registers()
/openbmc/linux/drivers/gpu/drm/i915/gvt/
H A Dhandlers.c2534 MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write); in init_bdw_mmio_info()