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Searched refs:RESET_CTRL (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/arch/arm/mach-versatile/
H A Dtc2_pm.c30 #define RESET_CTRL 0x018 macro
118 return !(readl_relaxed(scc + RESET_CTRL) & mask); in tc2_core_in_reset()
134 readl_relaxed(scc + RESET_CTRL)); in tc2_pm_wait_for_powerdown()
/openbmc/qemu/hw/i3c/
H A Daspeed_i3c.c163 REG32(RESET_CTRL, 0x34)
164 FIELD(RESET_CTRL, CORE_RESET, 0, 1)
165 FIELD(RESET_CTRL, CMD_QUEUE_RESET, 1, 1)
166 FIELD(RESET_CTRL, RESP_QUEUE_RESET, 2, 1)
167 FIELD(RESET_CTRL, TX_BUF_RESET, 3, 1)
168 FIELD(RESET_CTRL, RX_BUF_RESET, 4, 1)
169 FIELD(RESET_CTRL, IBI_QUEUE_RESET, 5, 1)
1023 if (FIELD_EX32(val, RESET_CTRL, CORE_RESET)) { in aspeed_i3c_device_reset_ctrl_w()
1026 if (FIELD_EX32(val, RESET_CTRL, CMD_QUEUE_RESET)) { in aspeed_i3c_device_reset_ctrl_w()
1029 if (FIELD_EX32(val, RESET_CTRL, RESP_QUEUE_RESET)) { in aspeed_i3c_device_reset_ctrl_w()
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/openbmc/linux/include/linux/mfd/
H A Didt8a340_reg.h98 #define RESET_CTRL 0xc000 macro
/openbmc/linux/drivers/i3c/master/
H A Ddw-i3c-master.c106 #define RESET_CTRL 0x34 macro
438 master->regs + RESET_CTRL); in dw_i3c_master_dequeue_xfer_locked()
440 readl_poll_timeout_atomic(master->regs + RESET_CTRL, status, in dw_i3c_master_dequeue_xfer_locked()
/openbmc/linux/drivers/ptp/
H A Dptp_clockmatrix.c1072 err = idtcm_write(idtcm, RESET_CTRL, in idtcm_state_machine_reset()