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Searched refs:RESET (Results 1 – 25 of 181) sorted by relevance

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/openbmc/u-boot/drivers/clk/sunxi/
H A Dclk_r40.c57 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
58 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
59 [RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
61 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
62 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
63 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
64 [RST_BUS_MMC3] = RESET(0x2c0, BIT(11)),
65 [RST_BUS_GMAC] = RESET(0x2c0, BIT(17)),
66 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
67 [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
[all …]
H A Dclk_h3.c53 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
54 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
55 [RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
56 [RST_USB_PHY3] = RESET(0x0cc, BIT(3)),
58 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
59 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
60 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
61 [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)),
62 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
63 [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
[all …]
H A Dclk_a31.c53 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
54 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
55 [RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
57 [RST_AHB1_MMC0] = RESET(0x2c0, BIT(8)),
58 [RST_AHB1_MMC1] = RESET(0x2c0, BIT(9)),
59 [RST_AHB1_MMC2] = RESET(0x2c0, BIT(10)),
60 [RST_AHB1_MMC3] = RESET(0x2c0, BIT(11)),
61 [RST_AHB1_EMAC] = RESET(0x2c0, BIT(17)),
62 [RST_AHB1_SPI0] = RESET(0x2c0, BIT(20)),
63 [RST_AHB1_SPI1] = RESET(0x2c0, BIT(21)),
[all …]
H A Dclk_a64.c46 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
47 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
48 [RST_USB_HSIC] = RESET(0x0cc, BIT(2)),
50 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
51 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
52 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
53 [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)),
54 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
55 [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
56 [RST_BUS_OTG] = RESET(0x2c0, BIT(23)),
[all …]
H A Dclk_a83t.c44 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
45 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
46 [RST_USB_HSIC] = RESET(0x0cc, BIT(2)),
48 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
49 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
50 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
51 [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)),
52 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
53 [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
54 [RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
[all …]
H A Dclk_a23.c42 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
43 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
44 [RST_USB_HSIC] = RESET(0x0cc, BIT(2)),
46 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
47 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
48 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
49 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
50 [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
51 [RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
52 [RST_BUS_EHCI] = RESET(0x2c0, BIT(26)),
[all …]
H A Dclk_h6.c34 [RST_BUS_MMC0] = RESET(0x84c, BIT(16)),
35 [RST_BUS_MMC1] = RESET(0x84c, BIT(17)),
36 [RST_BUS_MMC2] = RESET(0x84c, BIT(18)),
37 [RST_BUS_UART0] = RESET(0x90c, BIT(16)),
38 [RST_BUS_UART1] = RESET(0x90c, BIT(17)),
39 [RST_BUS_UART2] = RESET(0x90c, BIT(18)),
40 [RST_BUS_UART3] = RESET(0x90c, BIT(19)),
42 [RST_BUS_SPI0] = RESET(0x96c, BIT(16)),
43 [RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
45 [RST_BUS_EMAC] = RESET(0x97c, BIT(16)),
H A Dclk_a80.c36 [RST_BUS_MMC] = RESET(0x5a0, BIT(8)),
37 [RST_BUS_SPI0] = RESET(0x5a0, BIT(20)),
38 [RST_BUS_SPI1] = RESET(0x5a0, BIT(21)),
39 [RST_BUS_SPI2] = RESET(0x5a0, BIT(22)),
40 [RST_BUS_SPI3] = RESET(0x5a0, BIT(23)),
42 [RST_BUS_UART0] = RESET(0x5b4, BIT(16)),
43 [RST_BUS_UART1] = RESET(0x5b4, BIT(17)),
44 [RST_BUS_UART2] = RESET(0x5b4, BIT(18)),
45 [RST_BUS_UART3] = RESET(0x5b4, BIT(19)),
46 [RST_BUS_UART4] = RESET(0x5b4, BIT(20)),
[all …]
H A Dclk_v3s.c32 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
34 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
35 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
36 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
37 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
38 [RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
40 [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
41 [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
42 [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
H A Dclk_a10.c54 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
55 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
56 [RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
H A Dclk_a10s.c42 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
43 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
/openbmc/qemu/include/hw/misc/
H A Dxlnx-versal-crl.h39 FIELD(RPLL_CTRL, RESET, 0, 1)
160 FIELD(RST_ADMA, RESET, 0, 1)
162 FIELD(RST_GEM0, RESET, 0, 1)
164 FIELD(RST_GEM1, RESET, 0, 1)
166 FIELD(RST_SPARE, RESET, 0, 1)
168 FIELD(RST_USB0, RESET, 0, 1)
170 FIELD(RST_UART0, RESET, 0, 1)
172 FIELD(RST_UART1, RESET, 0, 1)
174 FIELD(RST_SPI0, RESET, 0, 1)
176 FIELD(RST_SPI1, RESET, 0, 1)
[all …]
/openbmc/linux/drivers/reset/
H A Dreset-rzg2l-usbphy-ctrl.c16 #define RESET 0x000 macro
51 val = readl(base + RESET); in rzg2l_usbphy_ctrl_assert()
55 writel(val, base + RESET); in rzg2l_usbphy_ctrl_assert()
70 val = readl(base + RESET); in rzg2l_usbphy_ctrl_deassert()
74 writel(val, base + RESET); in rzg2l_usbphy_ctrl_deassert()
88 return !!(readl(priv->base + RESET) & port_mask); in rzg2l_usbphy_ctrl_status()
151 val = readl(priv->base + RESET); in rzg2l_usbphy_ctrl_probe()
153 writel(val, priv->base + RESET); in rzg2l_usbphy_ctrl_probe()
/openbmc/u-boot/arch/arm/mach-exynos/
H A Dsec_boot.S88 .word 0x1 @ CPU0_STATE : RESET
89 .word 0x2 @ CPU1_STATE : SECONDARY RESET
90 .word 0x2 @ CPU2_STATE : SECONDARY RESET
91 .word 0x2 @ CPU3_STATE : SECONDARY RESET
/openbmc/qemu/docs/spin/
H A Dwin32-qemu-event.promela26 #define RESET RAW_RESET
31 * primitives. SET/RESET/WAIT have exactly the same semantics as
52 #define RESET if :: state == EV_SET -> atomic { state = state | EV_FREE; } \
84 RESET;
/openbmc/linux/arch/mips/cobalt/
H A Dreset.c21 #define RESET 0x0f macro
48 writeb(RESET, RESET_PORT); in cobalt_machine_restart()
/openbmc/u-boot/tools/patman/
H A Dterminal.py99 RESET = '\033[0m' variable in Color
138 return self.RESET
161 return start + text + self.RESET
/openbmc/qemu/hw/misc/
H A Dxlnx-versal-crl.c103 REGFIELD_RESET(dev, s, RST_ADMA, RESET, val64, s->cfg.adma[i]); in crl_rst_adma_prew()
112 REGFIELD_RESET(dev, s, RST_UART0, RESET, val64, s->cfg.uart[0]); in crl_rst_uart0_prew()
120 REGFIELD_RESET(dev, s, RST_UART1, RESET, val64, s->cfg.uart[1]); in crl_rst_uart1_prew()
128 REGFIELD_RESET(dev, s, RST_GEM0, RESET, val64, s->cfg.gem[0]); in crl_rst_gem0_prew()
136 REGFIELD_RESET(dev, s, RST_GEM1, RESET, val64, s->cfg.gem[1]); in crl_rst_gem1_prew()
144 REGFIELD_RESET(dev, s, RST_USB0, RESET, val64, s->cfg.usb); in crl_rst_usb_prew()
/openbmc/u-boot/drivers/fpga/
H A Divm_core.c251 { RESET, RESET, 0xFC, 6 }, /* Transitions from RESET */
252 { RESET, IDLE, 0x00, 1 },
253 { RESET, DRPAUSE, 0x50, 5 },
254 { RESET, IRPAUSE, 0x68, 6 },
255 { IDLE, RESET, 0xE0, 3 }, /* Transitions from IDLE */
258 { DRPAUSE, RESET, 0xF8, 5 }, /* Transitions from DRPAUSE */
262 { IRPAUSE, RESET, 0xF8, 5 }, /* Transitions from IRPAUSE */
333 case RESET: in GetState()
2441 (cNextJTAGState != RESET)) { in ispVMStateMachine()
2496 ispVMStateMachine(RESET); /*step devices to RESET state*/ in ispVMStart()
[all …]
/openbmc/linux/drivers/misc/altera-stapl/
H A Daltera-jtag.c35 /* RESET */ { RESET, IDLE },
44 /* IRSELECT */ { RESET, IRCAPTURE },
307 } else if (state == RESET) in altera_goto_jstate()
354 tms = (wait_state == RESET) ? TMS_HIGH : TMS_LOW; in altera_wait_cycles()
598 case RESET: in altera_irscan()
697 case RESET: in altera_swap_ir()
801 case RESET: in altera_drscan()
892 case RESET: in altera_swap_dr()
/openbmc/linux/arch/arm/boot/dts/intel/pxa/
H A Dpxa300-raumfeld-tuneable-clock.dtsi74 MFP_PIN_PXA300(120) MFP_AF0 /* RESET */
81 MFP_PIN_PXA300(111) MFP_AF0 /* RESET */
/openbmc/u-boot/drivers/rtc/
H A Dds1302.c18 #define RESET rtc_go_low(RST), rtc_go_low(SCLK) macro
164 RESET; in read_ser_drv()
184 RESET; in write_ser_drv()
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dcs4271.txt20 !RESET pin
24 The CS4271 requires its LRCLK and MCLK to be stable before its RESET
/openbmc/linux/drivers/media/i2c/
H A Dov2640.c126 #define RESET 0xE0 /* Reset */ macro
384 { RESET, RESET_JPEG | RESET_DVP },
502 { RESET, RESET_DVP },
527 { RESET, 0x00}
603 { RESET, 0x00 },
613 { RESET, 0x00 },
621 { RESET, 0x00 },
629 { RESET, 0x00 },
/openbmc/linux/drivers/iio/chemical/
H A Dsps30.c35 RESET, enumerator
72 if (state->state == RESET) { in sps30_do_meas()
98 state->state = RESET; in sps30_do_reset()

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