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Searched refs:RENDER_RING_BASE (Results 1 – 14 of 14) sorted by relevance

/openbmc/linux/drivers/gpu/drm/i915/gvt/
H A Dmmio_context.c50 {RCS0, RING_MODE_GEN7(RENDER_RING_BASE), 0xffff, false}, /* 0x229c */
54 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
55 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
56 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
57 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
58 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
59 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
60 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
61 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
62 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
[all …]
H A Dhandlers.c2159 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
2215 MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL); in init_generic_mmio_info()
2781 MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS, in init_bxt_mmio_info()
/openbmc/linux/drivers/gpu/drm/i915/
H A Di915_cmd_parser.c619 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
620 REG64_IDX(MI_PREDICATE_SRC0, RENDER_RING_BASE),
621 REG64_IDX(MI_PREDICATE_SRC1, RENDER_RING_BASE),
651 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 0),
652 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 1),
653 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 2),
654 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 3),
655 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 4),
656 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 5),
657 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 6),
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H A Di915_ioctl.c32 .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
33 .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
H A Dintel_clock_gating.c529 intel_uncore_write(&i915->uncore, RING_PSMI_CTL(RENDER_RING_BASE), in bdw_init_clock_gating()
666 intel_uncore_write(&i915->uncore, RING_PSMI_CTL(RENDER_RING_BASE), in chv_init_clock_gating()
737 intel_uncore_write(&i915->uncore, ECOSKPD(RENDER_RING_BASE), in gen3_init_clock_gating()
741 intel_uncore_write(&i915->uncore, ECOSKPD(RENDER_RING_BASE), in gen3_init_clock_gating()
H A Dintel_gvt_mmio_table.c36 MMIO_F(prefix(RENDER_RING_BASE), s); \
73 MMIO_D(CCID(RENDER_RING_BASE)); in iterate_generic_mmio()
598 MMIO_D(ECOSKPD(RENDER_RING_BASE)); in iterate_generic_mmio()
1241 MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40); in iterate_bxt_mmio()
H A Di915_perf.c1989 MI_PREDICATE_RESULT_1(RENDER_RING_BASE); in alloc_noa_wait()
2795 GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE), in lrc_configure_all_contexts()
H A Dintel_uncore.c1899 __raw_uncore_write32(uncore, RING_MI_MODE(RENDER_RING_BASE), 0); in ilk_dummy_write()
H A Di915_reg.h896 #define RENDER_RING_BASE 0x02000 macro
/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dintel_engine_regs.h35 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
36 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
37 #define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
H A Dintel_workarounds.c358 wa_masked_en(wal, RING_MI_MODE(RENDER_RING_BASE), ASYNC_FLIP_PERF_DISABLE); in gen8_ctx_workarounds_init()
2401 RING_PSMI_CTL(RENDER_RING_BASE), in rcs_engine_wa_init()
2653 RING_MODE_GEN7(RENDER_RING_BASE), in rcs_engine_wa_init()
2691 RING_MI_MODE(RENDER_RING_BASE), in rcs_engine_wa_init()
2750 wa_add(wal, RING_MI_MODE(RENDER_RING_BASE), in rcs_engine_wa_init()
2766 wa_add(wal, ECOSKPD(RENDER_RING_BASE), in rcs_engine_wa_init()
H A Dintel_gt.c248 intel_uncore_write(uncore, IPEIR(RENDER_RING_BASE), 0); in intel_gt_clear_error_registers()
437 RING_HEAD(RENDER_RING_BASE)); in intel_gt_flush_ggtt_writes()
H A Dintel_rc6.c471 if (!((intel_uncore_read(uncore, PWRCTX_MAXCNT(RENDER_RING_BASE)) & IDLE_TIME_MASK) > 1 && in bxt_check_bios_rc6_setup()
H A Dintel_engine_cs.c68 { .graphics_ver = 1, .base = RENDER_RING_BASE }